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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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vfio: Remove VFIO_TYPE1_NESTING_IOMMU
This control causes the ARM SMMU drivers to choose a stage 2
implementation for the IO pagetable (vs the stage 1 usual default),
however this choice has no significant visible impact to the VFIO
user. Further qemu never implemented this and no other userspace user is
known.
The original description in commit f5c9ecebaf
("vfio/iommu_type1: add
new VFIO_TYPE1_NESTING_IOMMU IOMMU type") suggested this was to "provide
SMMU translation services to the guest operating system" however the rest
of the API to set the guest table pointer for the stage 1 and manage
invalidation was never completed, or at least never upstreamed, rendering
this part useless dead code.
Upstream has now settled on iommufd as the uAPI for controlling nested
translation. Choosing the stage 2 implementation should be done by through
the IOMMU_HWPT_ALLOC_NEST_PARENT flag during domain allocation.
Remove VFIO_TYPE1_NESTING_IOMMU and everything under it including the
enable_nesting iommu_domain_op.
Just in-case there is some userspace using this continue to treat
requesting it as a NOP, but do not advertise support any more.
Acked-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Reviewed-by: Donald Dutile <ddutile@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/1-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
parent
8e929cb546
commit
35890f8557
@ -3378,21 +3378,6 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev)
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return group;
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}
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static int arm_smmu_enable_nesting(struct iommu_domain *domain)
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{
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struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
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int ret = 0;
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mutex_lock(&smmu_domain->init_mutex);
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if (smmu_domain->smmu)
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ret = -EPERM;
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else
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smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
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mutex_unlock(&smmu_domain->init_mutex);
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return ret;
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}
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static int arm_smmu_of_xlate(struct device *dev,
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const struct of_phandle_args *args)
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{
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@ -3514,7 +3499,6 @@ static struct iommu_ops arm_smmu_ops = {
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.flush_iotlb_all = arm_smmu_flush_iotlb_all,
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.iotlb_sync = arm_smmu_iotlb_sync,
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.iova_to_phys = arm_smmu_iova_to_phys,
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.enable_nesting = arm_smmu_enable_nesting,
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.free = arm_smmu_domain_free_paging,
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}
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};
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@ -1558,21 +1558,6 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev)
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return group;
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}
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static int arm_smmu_enable_nesting(struct iommu_domain *domain)
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{
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struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
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int ret = 0;
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mutex_lock(&smmu_domain->init_mutex);
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if (smmu_domain->smmu)
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ret = -EPERM;
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else
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smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
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mutex_unlock(&smmu_domain->init_mutex);
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return ret;
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}
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static int arm_smmu_set_pgtable_quirks(struct iommu_domain *domain,
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unsigned long quirks)
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{
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@ -1656,7 +1641,6 @@ static struct iommu_ops arm_smmu_ops = {
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.flush_iotlb_all = arm_smmu_flush_iotlb_all,
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.iotlb_sync = arm_smmu_iotlb_sync,
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.iova_to_phys = arm_smmu_iova_to_phys,
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.enable_nesting = arm_smmu_enable_nesting,
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.set_pgtable_quirks = arm_smmu_set_pgtable_quirks,
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.free = arm_smmu_domain_free,
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}
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@ -2723,16 +2723,6 @@ static int __init iommu_init(void)
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}
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core_initcall(iommu_init);
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int iommu_enable_nesting(struct iommu_domain *domain)
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{
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if (domain->type != IOMMU_DOMAIN_UNMANAGED)
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return -EINVAL;
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if (!domain->ops->enable_nesting)
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return -EINVAL;
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return domain->ops->enable_nesting(domain);
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}
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EXPORT_SYMBOL_GPL(iommu_enable_nesting);
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int iommu_set_pgtable_quirks(struct iommu_domain *domain,
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unsigned long quirk)
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{
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@ -291,12 +291,7 @@ static int iommufd_vfio_check_extension(struct iommufd_ctx *ictx,
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case VFIO_DMA_CC_IOMMU:
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return iommufd_vfio_cc_iommu(ictx);
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/*
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* This is obsolete, and to be removed from VFIO. It was an incomplete
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* idea that got merged.
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* https://lore.kernel.org/kvm/0-v1-0093c9b0e345+19-vfio_no_nesting_jgg@nvidia.com/
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*/
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case VFIO_TYPE1_NESTING_IOMMU:
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case __VFIO_RESERVED_TYPE1_NESTING_IOMMU:
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return 0;
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/*
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@ -72,7 +72,6 @@ struct vfio_iommu {
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uint64_t pgsize_bitmap;
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uint64_t num_non_pinned_groups;
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bool v2;
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bool nesting;
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bool dirty_page_tracking;
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struct list_head emulated_iommu_groups;
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};
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@ -2195,12 +2194,6 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
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goto out_free_domain;
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}
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if (iommu->nesting) {
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ret = iommu_enable_nesting(domain->domain);
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if (ret)
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goto out_domain;
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}
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ret = iommu_attach_group(domain->domain, group->iommu_group);
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if (ret)
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goto out_domain;
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@ -2541,9 +2534,7 @@ static void *vfio_iommu_type1_open(unsigned long arg)
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switch (arg) {
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case VFIO_TYPE1_IOMMU:
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break;
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case VFIO_TYPE1_NESTING_IOMMU:
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iommu->nesting = true;
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fallthrough;
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case __VFIO_RESERVED_TYPE1_NESTING_IOMMU:
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case VFIO_TYPE1v2_IOMMU:
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iommu->v2 = true;
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break;
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@ -2638,7 +2629,6 @@ static int vfio_iommu_type1_check_extension(struct vfio_iommu *iommu,
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switch (arg) {
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case VFIO_TYPE1_IOMMU:
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case VFIO_TYPE1v2_IOMMU:
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case VFIO_TYPE1_NESTING_IOMMU:
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case VFIO_UNMAP_ALL:
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return 1;
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case VFIO_UPDATE_VADDR:
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@ -635,7 +635,6 @@ struct iommu_ops {
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* @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE,
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* including no-snoop TLPs on PCIe or other platform
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* specific mechanisms.
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* @enable_nesting: Enable nesting
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* @set_pgtable_quirks: Set io page table quirks (IO_PGTABLE_QUIRK_*)
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* @free: Release the domain after use.
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*/
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@ -663,7 +662,6 @@ struct iommu_domain_ops {
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dma_addr_t iova);
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bool (*enforce_cache_coherency)(struct iommu_domain *domain);
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int (*enable_nesting)(struct iommu_domain *domain);
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int (*set_pgtable_quirks)(struct iommu_domain *domain,
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unsigned long quirks);
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@ -844,7 +842,6 @@ extern void iommu_group_put(struct iommu_group *group);
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extern int iommu_group_id(struct iommu_group *group);
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extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *);
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int iommu_enable_nesting(struct iommu_domain *domain);
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int iommu_set_pgtable_quirks(struct iommu_domain *domain,
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unsigned long quirks);
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@ -35,7 +35,7 @@
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#define VFIO_EEH 5
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/* Two-stage IOMMU */
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#define VFIO_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
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#define __VFIO_RESERVED_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
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#define VFIO_SPAPR_TCE_v2_IOMMU 7
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