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kbuild: fix for some typos in Documentation/makefiles.txt
I noticed a few typos while reading makefiles.txt to learn about the kbuild system. Attached is a patch against 2.6.18 to fix them. Remove trailing whitespace while we are there.. Signed-off-by: Bryce Harrington <bryce@osdl.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
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@ -22,7 +22,7 @@ This document describes the Linux kernel Makefiles.
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=== 4 Host Program support
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--- 4.1 Simple Host Program
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--- 4.2 Composite Host Programs
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--- 4.3 Defining shared libraries
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--- 4.3 Defining shared libraries
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--- 4.4 Using C++ for host programs
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--- 4.5 Controlling compiler options for host programs
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--- 4.6 When host programs are actually built
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@ -69,7 +69,7 @@ architecture-specific information to the top Makefile.
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Each subdirectory has a kbuild Makefile which carries out the commands
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passed down from above. The kbuild Makefile uses information from the
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.config file to construct various file lists used by kbuild to build
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.config file to construct various file lists used by kbuild to build
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any built-in or modular targets.
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scripts/Makefile.* contains all the definitions/rules etc. that
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@ -203,9 +203,9 @@ more details, with real examples.
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Example:
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#fs/ext2/Makefile
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obj-$(CONFIG_EXT2_FS) += ext2.o
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ext2-y := balloc.o bitmap.o
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ext2-y := balloc.o bitmap.o
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ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
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In this example, xattr.o is only part of the composite object
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ext2.o if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
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@ -244,7 +244,7 @@ more details, with real examples.
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For kbuild to actually recognize that there is a lib.a being built,
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the directory shall be listed in libs-y.
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See also "6.3 List directories to visit when descending".
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Use of lib-y is normally restricted to lib/ and arch/*/lib.
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--- 3.6 Descending down in directories
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@ -408,7 +408,7 @@ more details, with real examples.
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if first argument is not supported.
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ld-option
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ld-option is used to check if $(CC) when used to link object files
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ld-option is used to check if $(CC) when used to link object files
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supports the given option. An optional second option may be
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specified if first option are not supported.
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@ -435,7 +435,7 @@ more details, with real examples.
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cflags-y will be assigned no value if first option is not supported.
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cc-option-yn
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cc-option-yn is used to check if gcc supports a given option
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cc-option-yn is used to check if gcc supports a given option
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and return 'y' if supported, otherwise 'n'.
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Example:
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@ -443,7 +443,7 @@ more details, with real examples.
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biarch := $(call cc-option-yn, -m32)
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aflags-$(biarch) += -a32
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cflags-$(biarch) += -m32
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In the above example, $(biarch) is set to y if $(CC) supports the -m32
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option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
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and $(cflags-y) will be assigned the values -a32 and -m32,
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@ -457,13 +457,13 @@ more details, with real examples.
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cc-option-align = -malign
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gcc >= 3.00
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cc-option-align = -falign
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Example:
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CFLAGS += $(cc-option-align)-functions=4
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In the above example, the option -falign-functions=4 is used for
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gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
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cc-version
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cc-version returns a numerical version of the $(CC) compiler version.
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The format is <major><minor> where both are two digits. So for example
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@ -491,7 +491,7 @@ more details, with real examples.
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In this example, EXTRA_CFLAGS will be assigned the value -O1 if the
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$(CC) version is less than 4.2.
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cc-ifversion takes all the shell operators:
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cc-ifversion takes all the shell operators:
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-eq, -ne, -lt, -le, -gt, and -ge
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The third parameter may be a text as in this example, but it may also
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be an expanded variable or a macro.
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@ -507,7 +507,7 @@ The first step is to tell kbuild that a host program exists. This is
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done utilising the variable hostprogs-y.
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The second step is to add an explicit dependency to the executable.
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This can be done in two ways. Either add the dependency in a rule,
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This can be done in two ways. Either add the dependency in a rule,
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or utilise the variable $(always).
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Both possibilities are described in the following.
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@ -524,7 +524,7 @@ Both possibilities are described in the following.
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Kbuild assumes in the above example that bin2hex is made from a single
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c-source file named bin2hex.c located in the same directory as
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the Makefile.
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--- 4.2 Composite Host Programs
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Host programs can be made up based on composite objects.
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@ -535,7 +535,7 @@ Both possibilities are described in the following.
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Example:
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#scripts/lxdialog/Makefile
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hostprogs-y := lxdialog
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hostprogs-y := lxdialog
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lxdialog-objs := checklist.o lxdialog.o
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Objects with extension .o are compiled from the corresponding .c
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@ -544,8 +544,8 @@ Both possibilities are described in the following.
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Finally, the two .o files are linked to the executable, lxdialog.
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Note: The syntax <executable>-y is not permitted for host-programs.
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--- 4.3 Defining shared libraries
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--- 4.3 Defining shared libraries
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Objects with extension .so are considered shared libraries, and
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will be compiled as position independent objects.
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Kbuild provides support for shared libraries, but the usage
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@ -558,7 +558,7 @@ Both possibilities are described in the following.
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hostprogs-y := conf
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conf-objs := conf.o libkconfig.so
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libkconfig-objs := expr.o type.o
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Shared libraries always require a corresponding -objs line, and
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in the example above the shared library libkconfig is composed by
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the two objects expr.o and type.o.
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@ -579,7 +579,7 @@ Both possibilities are described in the following.
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In the example above the executable is composed of the C++ file
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qconf.cc - identified by $(qconf-cxxobjs).
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If qconf is composed by a mixture of .c and .cc files, then an
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additional line can be used to identify this.
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@ -588,7 +588,7 @@ Both possibilities are described in the following.
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hostprogs-y := qconf
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qconf-cxxobjs := qconf.o
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qconf-objs := check.o
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--- 4.5 Controlling compiler options for host programs
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When compiling host programs, it is possible to set specific flags.
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@ -600,23 +600,23 @@ Both possibilities are described in the following.
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Example:
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#scripts/lxdialog/Makefile
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HOST_EXTRACFLAGS += -I/usr/include/ncurses
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To set specific flags for a single file the following construction
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is used:
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Example:
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#arch/ppc64/boot/Makefile
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HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
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It is also possible to specify additional options to the linker.
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Example:
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#scripts/kconfig/Makefile
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HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
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When linking qconf, it will be passed the extra option
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"-L$(QTDIR)/lib".
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--- 4.6 When host programs are actually built
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Kbuild will only build host-programs when they are referenced
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@ -631,7 +631,7 @@ Both possibilities are described in the following.
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$(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
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( cd $(obj); ./gen-devlist ) < $<
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The target $(obj)/devlist.h will not be built before
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The target $(obj)/devlist.h will not be built before
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$(obj)/gen-devlist is updated. Note that references to
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the host programs in special rules must be prefixed with $(obj).
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@ -650,7 +650,7 @@ Both possibilities are described in the following.
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--- 4.7 Using hostprogs-$(CONFIG_FOO)
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A typcal pattern in a Kbuild file looks like this:
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A typical pattern in a Kbuild file looks like this:
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Example:
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#scripts/Makefile
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@ -682,7 +682,8 @@ When executing "make clean", the two files "devlist.h classlist.h" will
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be deleted. Kbuild will assume files to be in same relative directory as the
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Makefile except if an absolute path is specified (path starting with '/').
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To delete a directory hirachy use:
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To delete a directory hierarchy use:
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Example:
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#scripts/package/Makefile
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clean-dirs := $(objtree)/debian/
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@ -740,7 +741,7 @@ When kbuild executes, the following steps are followed (roughly):
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5) Recursively descend down in all directories listed in
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init-* core* drivers-* net-* libs-* and build all targets.
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- The values of the above variables are expanded in arch/$(ARCH)/Makefile.
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6) All object files are then linked and the resulting file vmlinux is
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6) All object files are then linked and the resulting file vmlinux is
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located at the root of the obj tree.
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The very first objects linked are listed in head-y, assigned by
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arch/$(ARCH)/Makefile.
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@ -762,7 +763,7 @@ When kbuild executes, the following steps are followed (roughly):
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LDFLAGS := -m elf_s390
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Note: EXTRA_LDFLAGS and LDFLAGS_$@ can be used to further customise
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the flags used. See chapter 7.
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LDFLAGS_MODULE Options for $(LD) when linking modules
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LDFLAGS_MODULE is used to set specific flags for $(LD) when
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@ -845,7 +846,7 @@ When kbuild executes, the following steps are followed (roughly):
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$(CFLAGS_MODULE) contains extra C compiler flags used to compile code
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for loadable kernel modules.
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--- 6.2 Add prerequisites to archprepare:
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The archprepare: rule is used to list prerequisites that need to be
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@ -869,7 +870,7 @@ When kbuild executes, the following steps are followed (roughly):
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corresponding arch-specific section for modules; the module-building
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machinery is all architecture-independent.
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head-y, init-y, core-y, libs-y, drivers-y, net-y
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$(head-y) lists objects to be linked first in vmlinux.
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@ -926,7 +927,7 @@ When kbuild executes, the following steps are followed (roughly):
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#arch/i386/Makefile
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define archhelp
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echo '* bzImage - Image (arch/$(ARCH)/boot/bzImage)'
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endef
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endif
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When make is executed without arguments, the first goal encountered
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will be built. In the top level Makefile the first goal present
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@ -938,7 +939,7 @@ When kbuild executes, the following steps are followed (roughly):
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Example:
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#arch/i386/Makefile
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all: bzImage
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all: bzImage
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When "make" is executed without arguments, bzImage will be built.
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@ -961,7 +962,7 @@ When kbuild executes, the following steps are followed (roughly):
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In this example, extra-y is used to list object files that
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shall be built, but shall not be linked as part of built-in.o.
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--- 6.6 Commands useful for building a boot image
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Kbuild provides a few macros that are useful when building a
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@ -995,7 +996,7 @@ When kbuild executes, the following steps are followed (roughly):
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ld
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Link target. Often, LDFLAGS_$@ is used to set specific options to ld.
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objcopy
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Copy binary. Uses OBJCOPYFLAGS usually specified in
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arch/$(ARCH)/Makefile.
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@ -1053,7 +1054,7 @@ When kbuild executes, the following steps are followed (roughly):
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BUILD arch/i386/boot/bzImage
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will be displayed with "make KBUILD_VERBOSE=0".
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--- 6.8 Preprocessing linker scripts
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@ -1062,19 +1063,19 @@ When kbuild executes, the following steps are followed (roughly):
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The script is a preprocessed variant of the file vmlinux.lds.S
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located in the same directory.
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kbuild knows .lds files and includes a rule *lds.S -> *lds.
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Example:
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#arch/i386/kernel/Makefile
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always := vmlinux.lds
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#Makefile
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export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
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The assigment to $(always) is used to tell kbuild to build the
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The assignment to $(always) is used to tell kbuild to build the
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target vmlinux.lds.
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The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
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specified options when building the target vmlinux.lds.
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When building the *.lds target, kbuild uses the variables:
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CPPFLAGS : Set in top-level Makefile
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EXTRA_CPPFLAGS : May be set in the kbuild makefile
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@ -1180,3 +1181,5 @@ Language QA by Jan Engelhardt <jengelh@gmx.de>
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- Generating offset header files.
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- Add more variables to section 7?
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