Some pin control fixes for the v6.7 cycle:

- Fix a really interesting potential core bug in the list iterator
   requireing the use of READ_ONCE() discovered when testing kernel
   compiles with clang.
 
 - Check devm_kcalloc() return value and an array bounds in the STM32
   driver.
 
 - Fix an exotic string truncation issue in the s32cc driver, found
   by the kernel test robot (impressive!)
 
 - Fix an undocumented struct member in the cy8c95x0 driver.
 
 - Fix a symbol overlap with MIPS in the Lochnagar driver, MIPS
   defines a global symbol "RST" which is a bit too generic and
   collide with stuff. OK this one should be renamed too, we will
   fix that as well.
 
 - Fix erroneous branch taking in the Realtek driver.
 
 - Fix the mail address in MAINTAINERS for the s32g2 driver.
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Merge tag 'pinctrl-v6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

 - Fix a really interesting potential core bug in the list iterator
   requireing the use of READ_ONCE() discovered when testing kernel
   compiles with clang.

 - Check devm_kcalloc() return value and an array bounds in the STM32
   driver.

 - Fix an exotic string truncation issue in the s32cc driver, found by
   the kernel test robot (impressive!)

 - Fix an undocumented struct member in the cy8c95x0 driver.

 - Fix a symbol overlap with MIPS in the Lochnagar driver, MIPS defines
   a global symbol "RST" which is a bit too generic and collide with
   stuff. OK this one should be renamed too, we will fix that as well.

 - Fix erroneous branch taking in the Realtek driver.

 - Fix the mail address in MAINTAINERS for the s32g2 driver.

* tag 'pinctrl-v6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  dt-bindings: pinctrl: s32g2: change a maintainer email address
  pinctrl: realtek: Fix logical error when finding descriptor
  pinctrl: lochnagar: Don't build on MIPS
  pinctrl: avoid reload of p state in list iteration
  pinctrl: cy8c95x0: Fix doc warning
  pinctrl: s32cc: Avoid possible string truncation
  pinctrl: stm32: fix array read out of bound
  pinctrl: stm32: Add check for devm_kcalloc

Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml

@@ -9,7 +9,7 @@ title: NXP S32G2 pin controller
 
 maintainers:
   - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
-  - Chester Lin <clin@suse.com>
+  - Chester Lin <chester62515@gmail.com>
 
 description: |
   S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),

drivers/pinctrl/cirrus/Kconfig

@@ -12,7 +12,8 @@ config PINCTRL_CS42L43
 
 config PINCTRL_LOCHNAGAR
 	tristate "Cirrus Logic Lochnagar pinctrl driver"
-	depends on MFD_LOCHNAGAR
+	# Avoid clash caused by MIPS defining RST, which is used in the driver
+	depends on MFD_LOCHNAGAR && !MIPS
 	select GPIOLIB
 	select PINMUX
 	select PINCONF

drivers/pinctrl/core.c

@@ -1262,17 +1262,17 @@ static void pinctrl_link_add(struct pinctrl_dev *pctldev,
 static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
 {
 	struct pinctrl_setting *setting, *setting2;
-	struct pinctrl_state *old_state = p->state;
+	struct pinctrl_state *old_state = READ_ONCE(p->state);
 	int ret;
 
-	if (p->state) {
+	if (old_state) {
 		/*
 		 * For each pinmux setting in the old state, forget SW's record
 		 * of mux owner for that pingroup. Any pingroups which are
 		 * still owned by the new state will be re-acquired by the call
 		 * to pinmux_enable_setting() in the loop below.
 		 */
-		list_for_each_entry(setting, &p->state->settings, node) {
+		list_for_each_entry(setting, &old_state->settings, node) {
 			if (setting->type != PIN_MAP_TYPE_MUX_GROUP)
 				continue;
 			pinmux_disable_setting(setting);

drivers/pinctrl/nxp/pinctrl-s32cc.c

@@ -843,8 +843,8 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev,
 	if (!np)
 		return -ENODEV;
 
-	if (mem_regions == 0) {
-		dev_err(&pdev->dev, "mem_regions is 0\n");
+	if (mem_regions == 0 || mem_regions >= 10000) {
+		dev_err(&pdev->dev, "mem_regions is invalid: %u\n", mem_regions);
 		return -EINVAL;
 	}
 

drivers/pinctrl/pinctrl-cy8c95x0.c

@@ -143,6 +143,7 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
  * @pinctrl_desc:   pin controller description
  * @name:           Chip controller name
  * @tpin:           Total number of pins
+ * @gpio_reset:     GPIO line handler that can reset the IC
  */
 struct cy8c95x0_pinctrl {
 	struct regmap *regmap;

drivers/pinctrl/realtek/pinctrl-rtd.c

@@ -146,7 +146,7 @@ static int rtd_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
 
 static const struct rtd_pin_desc *rtd_pinctrl_find_mux(struct rtd_pinctrl *data, unsigned int pin)
 {
-	if (!data->info->muxes[pin].name)
+	if (data->info->muxes[pin].name)
 		return &data->info->muxes[pin];
 
 	return NULL;
@@ -249,7 +249,7 @@ static const struct pinctrl_pin_desc
 static const struct rtd_pin_config_desc
 	*rtd_pinctrl_find_config(struct rtd_pinctrl *data, unsigned int pin)
 {
-	if (!data->info->configs[pin].name)
+	if (data->info->configs[pin].name)
 		return &data->info->configs[pin];
 
 	return NULL;

drivers/pinctrl/stm32/pinctrl-stm32.c

@@ -1273,9 +1273,11 @@ static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pi
 	int i;
 
 	/* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
-	pin_desc = pctl->pins + stm32_pin_nb;
-	if (pin_desc->pin.number == stm32_pin_nb)
-		return pin_desc;
+	if (stm32_pin_nb < pctl->npins) {
+		pin_desc = pctl->pins + stm32_pin_nb;
+		if (pin_desc->pin.number == stm32_pin_nb)
+			return pin_desc;
+	}
 
 	/* Otherwise, loop all array to find the pin with the right number */
 	for (i = 0; i < pctl->npins; i++) {
@@ -1368,6 +1370,11 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
 	}
 
 	names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
+	if (!names) {
+		err = -ENOMEM;
+		goto err_clk;
+	}
+
 	for (i = 0; i < npins; i++) {
 		stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
 		if (stm32_pin && stm32_pin->pin.name)