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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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net: ethernet: mtk_eth_soc: ppe: add support for flow accounting
The PPE units found in MT7622 and newer support packet and byte
accounting of hw-offloaded flows. Add support for reading those counters
as found in MediaTek's SDK[1].
[1]: bc6a6a375c
Tested-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle
Jakub Kicinski
parent
c0a440031d
commit
3fbe4d8c0e
@ -4697,8 +4697,8 @@ static int mtk_probe(struct platform_device *pdev)
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for (i = 0; i < num_ppe; i++) {
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u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
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eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr,
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eth->soc->offload_version, i);
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eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
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if (!eth->ppe[i]) {
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err = -ENOMEM;
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goto err_deinit_ppe;
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@ -4820,6 +4820,7 @@ static const struct mtk_soc_data mt7622_data = {
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.required_pctl = false,
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.offload_version = 2,
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.hash_offset = 2,
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.has_accounting = true,
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.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma),
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@ -4857,6 +4858,7 @@ static const struct mtk_soc_data mt7629_data = {
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7629_CLKS_BITMAP,
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.required_pctl = false,
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.has_accounting = true,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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@ -4877,6 +4879,7 @@ static const struct mtk_soc_data mt7981_data = {
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.offload_version = 2,
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.hash_offset = 4,
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.foe_entry_size = sizeof(struct mtk_foe_entry),
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.has_accounting = true,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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.rxd_size = sizeof(struct mtk_rx_dma_v2),
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@ -4897,6 +4900,7 @@ static const struct mtk_soc_data mt7986_data = {
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.offload_version = 2,
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.hash_offset = 4,
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.foe_entry_size = sizeof(struct mtk_foe_entry),
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.has_accounting = true,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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.rxd_size = sizeof(struct mtk_rx_dma_v2),
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@ -1070,6 +1070,8 @@ struct mtk_reg_map {
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* the extra setup for those pins used by GMAC.
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* @hash_offset Flow table hash offset.
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* @foe_entry_size Foe table entry size.
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* @has_accounting Bool indicating support for accounting of
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* offloaded flows.
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* @txd_size Tx DMA descriptor size.
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* @rxd_size Rx DMA descriptor size.
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* @rx_irq_done_mask Rx irq done register mask.
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@ -1087,6 +1089,7 @@ struct mtk_soc_data {
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u8 hash_offset;
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u16 foe_entry_size;
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netdev_features_t hw_features;
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bool has_accounting;
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struct {
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u32 txd_size;
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u32 rxd_size;
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@ -74,6 +74,48 @@ static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)
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return ret;
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}
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static int mtk_ppe_mib_wait_busy(struct mtk_ppe *ppe)
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{
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int ret;
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u32 val;
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ret = readl_poll_timeout(ppe->base + MTK_PPE_MIB_SER_CR, val,
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!(val & MTK_PPE_MIB_SER_CR_ST),
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20, MTK_PPE_WAIT_TIMEOUT_US);
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if (ret)
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dev_err(ppe->dev, "MIB table busy");
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return ret;
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}
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static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
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{
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u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high;
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u32 val, cnt_r0, cnt_r1, cnt_r2;
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int ret;
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val = FIELD_PREP(MTK_PPE_MIB_SER_CR_ADDR, index) | MTK_PPE_MIB_SER_CR_ST;
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ppe_w32(ppe, MTK_PPE_MIB_SER_CR, val);
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ret = mtk_ppe_mib_wait_busy(ppe);
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if (ret)
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return ret;
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cnt_r0 = readl(ppe->base + MTK_PPE_MIB_SER_R0);
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cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
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cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2);
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byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
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byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
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pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
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pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
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*bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
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*packets = (pkt_cnt_high << 16) | pkt_cnt_low;
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return 0;
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}
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static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
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{
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ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
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@ -458,6 +500,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
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hwe->ib1 &= ~MTK_FOE_IB1_STATE;
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hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID);
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dma_wmb();
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if (ppe->accounting) {
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struct mtk_foe_accounting *acct;
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acct = ppe->acct_table + entry->hash * sizeof(*acct);
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acct->packets = 0;
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acct->bytes = 0;
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}
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}
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entry->hash = 0xffff;
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@ -565,6 +614,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
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wmb();
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hwe->ib1 = entry->ib1;
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if (ppe->accounting)
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*mtk_foe_entry_ib2(eth, hwe) |= MTK_FOE_IB2_MIB_CNT;
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dma_wmb();
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mtk_ppe_cache_clear(ppe);
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@ -756,11 +808,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe *ppe)
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return mtk_ppe_wait_busy(ppe);
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}
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struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
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int version, int index)
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struct mtk_foe_accounting *mtk_foe_entry_get_mib(struct mtk_ppe *ppe, u32 index,
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struct mtk_foe_accounting *diff)
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{
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struct mtk_foe_accounting *acct;
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int size = sizeof(struct mtk_foe_accounting);
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u64 bytes, packets;
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if (!ppe->accounting)
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return NULL;
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if (mtk_mib_entry_read(ppe, index, &bytes, &packets))
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return NULL;
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acct = ppe->acct_table + index * size;
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acct->bytes += bytes;
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acct->packets += packets;
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if (diff) {
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diff->bytes = bytes;
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diff->packets = packets;
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}
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return acct;
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}
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struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index)
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{
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bool accounting = eth->soc->has_accounting;
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const struct mtk_soc_data *soc = eth->soc;
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struct mtk_foe_accounting *acct;
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struct device *dev = eth->dev;
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struct mtk_mib_entry *mib;
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struct mtk_ppe *ppe;
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u32 foe_flow_size;
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void *foe;
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@ -777,7 +857,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
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ppe->base = base;
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ppe->eth = eth;
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ppe->dev = dev;
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ppe->version = version;
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ppe->version = eth->soc->offload_version;
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ppe->accounting = accounting;
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foe = dmam_alloc_coherent(ppe->dev,
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MTK_PPE_ENTRIES * soc->foe_entry_size,
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@ -793,6 +874,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
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if (!ppe->foe_flow)
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goto err_free_l2_flows;
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if (accounting) {
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mib = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*mib),
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&ppe->mib_phys, GFP_KERNEL);
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if (!mib)
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return NULL;
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ppe->mib_table = mib;
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acct = devm_kzalloc(dev, MTK_PPE_ENTRIES * sizeof(*acct),
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GFP_KERNEL);
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if (!acct)
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return NULL;
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ppe->acct_table = acct;
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}
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mtk_ppe_debugfs_init(ppe, index);
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return ppe;
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@ -922,6 +1020,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
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ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
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ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
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}
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if (ppe->accounting && ppe->mib_phys) {
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ppe_w32(ppe, MTK_PPE_MIB_TB_BASE, ppe->mib_phys);
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ppe_m32(ppe, MTK_PPE_MIB_CFG, MTK_PPE_MIB_CFG_EN,
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MTK_PPE_MIB_CFG_EN);
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ppe_m32(ppe, MTK_PPE_MIB_CFG, MTK_PPE_MIB_CFG_RD_CLR,
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MTK_PPE_MIB_CFG_RD_CLR);
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ppe_m32(ppe, MTK_PPE_MIB_CACHE_CTL, MTK_PPE_MIB_CACHE_CTL_EN,
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MTK_PPE_MIB_CFG_RD_CLR);
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}
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}
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int mtk_ppe_stop(struct mtk_ppe *ppe)
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@ -57,6 +57,7 @@ enum {
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#define MTK_FOE_IB2_MULTICAST BIT(8)
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#define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12)
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#define MTK_FOE_IB2_MIB_CNT BIT(15)
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#define MTK_FOE_IB2_WDMA_DEVIDX BIT(16)
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#define MTK_FOE_IB2_WDMA_WINFO BIT(17)
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@ -285,16 +286,34 @@ struct mtk_flow_entry {
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unsigned long cookie;
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};
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struct mtk_mib_entry {
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u32 byt_cnt_l;
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u16 byt_cnt_h;
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u32 pkt_cnt_l;
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u8 pkt_cnt_h;
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u8 _rsv0;
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u32 _rsv1;
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} __packed;
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struct mtk_foe_accounting {
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u64 bytes;
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u64 packets;
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};
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struct mtk_ppe {
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struct mtk_eth *eth;
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struct device *dev;
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void __iomem *base;
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int version;
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char dirname[5];
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bool accounting;
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void *foe_table;
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dma_addr_t foe_phys;
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struct mtk_mib_entry *mib_table;
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dma_addr_t mib_phys;
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u16 foe_check_time[MTK_PPE_ENTRIES];
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struct hlist_head *foe_flow;
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@ -303,8 +322,8 @@ struct mtk_ppe {
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void *acct_table;
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};
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struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
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int version, int index);
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struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index);
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void mtk_ppe_deinit(struct mtk_eth *eth);
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void mtk_ppe_start(struct mtk_ppe *ppe);
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int mtk_ppe_stop(struct mtk_ppe *ppe);
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@ -359,5 +378,7 @@ int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
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void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
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int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
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int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index);
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struct mtk_foe_accounting *mtk_foe_entry_get_mib(struct mtk_ppe *ppe, u32 index,
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struct mtk_foe_accounting *diff);
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#endif
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@ -82,6 +82,7 @@ mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind)
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struct mtk_foe_entry *entry = mtk_foe_get_entry(ppe, i);
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struct mtk_foe_mac_info *l2;
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struct mtk_flow_addr_info ai = {};
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struct mtk_foe_accounting *acct;
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unsigned char h_source[ETH_ALEN];
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unsigned char h_dest[ETH_ALEN];
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int type, state;
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@ -95,6 +96,8 @@ mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind)
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if (bind && state != MTK_FOE_STATE_BIND)
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continue;
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acct = mtk_foe_entry_get_mib(ppe, i, NULL);
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type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
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seq_printf(m, "%05x %s %7s", i,
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mtk_foe_entry_state_str(state),
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@ -153,9 +156,11 @@ mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind)
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*((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo);
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seq_printf(m, " eth=%pM->%pM etype=%04x"
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" vlan=%d,%d ib1=%08x ib2=%08x\n",
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" vlan=%d,%d ib1=%08x ib2=%08x"
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" packets=%llu bytes=%llu\n",
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h_source, h_dest, ntohs(l2->etype),
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l2->vlan1, l2->vlan2, entry->ib1, ib2);
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l2->vlan1, l2->vlan2, entry->ib1, ib2,
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acct ? acct->packets : 0, acct ? acct->bytes : 0);
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}
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return 0;
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@ -497,6 +497,7 @@ static int
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mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f)
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{
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struct mtk_flow_entry *entry;
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struct mtk_foe_accounting diff;
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u32 idle;
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entry = rhashtable_lookup(ð->flow_table, &f->cookie,
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@ -507,6 +508,13 @@ mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f)
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idle = mtk_foe_entry_idle_time(eth->ppe[entry->ppe_index], entry);
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f->stats.lastused = jiffies - idle * HZ;
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if (entry->hash != 0xFFFF &&
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mtk_foe_entry_get_mib(eth->ppe[entry->ppe_index], entry->hash,
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&diff)) {
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f->stats.pkts += diff.packets;
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f->stats.bytes += diff.bytes;
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}
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return 0;
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}
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@ -149,6 +149,20 @@ enum {
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#define MTK_PPE_MIB_TB_BASE 0x338
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#define MTK_PPE_MIB_SER_CR 0x33C
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#define MTK_PPE_MIB_SER_CR_ST BIT(16)
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#define MTK_PPE_MIB_SER_CR_ADDR GENMASK(13, 0)
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#define MTK_PPE_MIB_SER_R0 0x340
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#define MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW GENMASK(31, 0)
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#define MTK_PPE_MIB_SER_R1 0x344
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#define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW GENMASK(31, 16)
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#define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0)
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#define MTK_PPE_MIB_SER_R2 0x348
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#define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0)
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#define MTK_PPE_MIB_CACHE_CTL 0x350
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#define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
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#define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
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