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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge series "spi: spi-sun6i: One fix and some improvements" from Marc Kleine-Budde <mkl@pengutronix.de>:
Hello, this series first fixes the calculation of the clock rate. The driver will round up to the nearest clock rate instead of rounding down. Resulting in SPI devices accessed with a too high SPI clock. The remaining patches improve the performance of the driver. The changes range from micro-optimizations like reducing MMIO writes to the controller to reducing the number of needed interrupts in some use cases. regards, Marc changes since v1: - added Maxime Ripard's to the existing patches - 06/10: (was 05/10 in v1) "spi: spi-sun6i: sun6i_spi_drain_fifo(): introduce sun6i_spi_get_rx_fifo_count() and make use of it" use FIELD_GET instead of open coding it (tnx: Maxime Ripard) - 05/10: "spi: spi-sun6i: sun6i_spi_get_tx_fifo_count: Convert manual shift+mask to FIELD_GET()" new patch _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
This commit is contained in:
Mark Brown
commit
411b0f305b
@ -1109,6 +1109,8 @@ static int dspi_suspend(struct device *dev)
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struct spi_controller *ctlr = dev_get_drvdata(dev);
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struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
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if (dspi->irq)
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disable_irq(dspi->irq);
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spi_controller_suspend(ctlr);
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clk_disable_unprepare(dspi->clk);
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@ -1129,6 +1131,8 @@ static int dspi_resume(struct device *dev)
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if (ret)
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return ret;
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spi_controller_resume(ctlr);
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if (dspi->irq)
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enable_irq(dspi->irq);
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return 0;
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}
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@ -1385,22 +1389,22 @@ static int dspi_probe(struct platform_device *pdev)
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goto poll_mode;
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}
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ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
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IRQF_SHARED, pdev->name, dspi);
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init_completion(&dspi->xfer_done);
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ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
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IRQF_SHARED, pdev->name, dspi);
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if (ret < 0) {
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dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
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goto out_clk_put;
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}
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init_completion(&dspi->xfer_done);
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poll_mode:
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if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
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ret = dspi_request_dma(dspi, res->start);
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if (ret < 0) {
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dev_err(&pdev->dev, "can't get dma channels\n");
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goto out_clk_put;
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goto out_free_irq;
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}
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}
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@ -1415,11 +1419,14 @@ poll_mode:
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ret = spi_register_controller(ctlr);
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if (ret != 0) {
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dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
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goto out_clk_put;
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goto out_free_irq;
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}
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return ret;
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out_free_irq:
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if (dspi->irq)
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free_irq(dspi->irq, dspi);
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out_clk_put:
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clk_disable_unprepare(dspi->clk);
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out_ctlr_put:
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@ -1434,18 +1441,8 @@ static int dspi_remove(struct platform_device *pdev)
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struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
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/* Disconnect from the SPI framework */
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dspi_release_dma(dspi);
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clk_disable_unprepare(dspi->clk);
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spi_unregister_controller(dspi->ctlr);
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return 0;
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}
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static void dspi_shutdown(struct platform_device *pdev)
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{
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struct spi_controller *ctlr = platform_get_drvdata(pdev);
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struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
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/* Disable RX and TX */
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regmap_update_bits(dspi->regmap, SPI_MCR,
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SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
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@ -1455,8 +1452,16 @@ static void dspi_shutdown(struct platform_device *pdev)
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regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
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dspi_release_dma(dspi);
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if (dspi->irq)
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free_irq(dspi->irq, dspi);
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clk_disable_unprepare(dspi->clk);
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spi_unregister_controller(dspi->ctlr);
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return 0;
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}
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static void dspi_shutdown(struct platform_device *pdev)
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{
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dspi_remove(pdev);
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}
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static struct platform_driver fsl_dspi_driver = {
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@ -36,7 +36,6 @@
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
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#define SPI_CFG0_CS_SETUP_OFFSET 24
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#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
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#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
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#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
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@ -48,6 +47,8 @@
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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#define SPI_CFG2_SCK_HIGH_OFFSET 0
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#define SPI_CFG2_SCK_LOW_OFFSET 16
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#define SPI_CMD_ACT BIT(0)
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#define SPI_CMD_RESUME BIT(1)
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@ -283,7 +284,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
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static void mtk_spi_prepare_transfer(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
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u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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spi_clk_hz = clk_get_rate(mdata->spi_clk);
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@ -296,18 +297,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master,
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cs_time = sck_time * 2;
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if (mdata->dev_comp->enhance_timing) {
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reg_val = (((sck_time - 1) & 0xffff)
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<< SPI_CFG2_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xffff)
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<< SPI_CFG0_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
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<< SPI_CFG2_SCK_LOW_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG2_REG);
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reg_val |= (((cs_time - 1) & 0xffff)
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reg_val = (((cs_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
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reg_val |= (((cs_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG0_REG);
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} else {
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reg_val |= (((sck_time - 1) & 0xff)
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reg_val = (((sck_time - 1) & 0xff)
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<< SPI_CFG0_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
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reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
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@ -1485,6 +1485,11 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
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{ PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
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/* TGL-H */
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{ PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
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/* APL */
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{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
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{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
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@ -553,20 +553,6 @@ static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
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.exec_op = stm32_qspi_exec_op,
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};
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static void stm32_qspi_release(struct stm32_qspi *qspi)
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{
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pm_runtime_get_sync(qspi->dev);
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/* disable qspi */
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writel_relaxed(0, qspi->io_base + QSPI_CR);
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stm32_qspi_dma_free(qspi);
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mutex_destroy(&qspi->lock);
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pm_runtime_put_noidle(qspi->dev);
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pm_runtime_disable(qspi->dev);
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pm_runtime_set_suspended(qspi->dev);
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pm_runtime_dont_use_autosuspend(qspi->dev);
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clk_disable_unprepare(qspi->clk);
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}
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static int stm32_qspi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -642,7 +628,7 @@ static int stm32_qspi_probe(struct platform_device *pdev)
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if (IS_ERR(rstc)) {
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ret = PTR_ERR(rstc);
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if (ret == -EPROBE_DEFER)
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goto err_qspi_release;
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goto err_clk_disable;
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} else {
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reset_control_assert(rstc);
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udelay(2);
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@ -653,7 +639,7 @@ static int stm32_qspi_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, qspi);
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ret = stm32_qspi_dma_setup(qspi);
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if (ret)
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goto err_qspi_release;
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goto err_dma_free;
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mutex_init(&qspi->lock);
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@ -673,15 +659,26 @@ static int stm32_qspi_probe(struct platform_device *pdev)
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ret = devm_spi_register_master(dev, ctrl);
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if (ret)
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goto err_qspi_release;
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goto err_pm_runtime_free;
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return 0;
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err_qspi_release:
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stm32_qspi_release(qspi);
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err_pm_runtime_free:
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pm_runtime_get_sync(qspi->dev);
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/* disable qspi */
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writel_relaxed(0, qspi->io_base + QSPI_CR);
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mutex_destroy(&qspi->lock);
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pm_runtime_put_noidle(qspi->dev);
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pm_runtime_disable(qspi->dev);
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pm_runtime_set_suspended(qspi->dev);
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pm_runtime_dont_use_autosuspend(qspi->dev);
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err_dma_free:
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stm32_qspi_dma_free(qspi);
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err_clk_disable:
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clk_disable_unprepare(qspi->clk);
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err_master_put:
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spi_master_put(qspi->ctrl);
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@ -692,7 +689,16 @@ static int stm32_qspi_remove(struct platform_device *pdev)
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{
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struct stm32_qspi *qspi = platform_get_drvdata(pdev);
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stm32_qspi_release(qspi);
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pm_runtime_get_sync(qspi->dev);
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/* disable qspi */
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writel_relaxed(0, qspi->io_base + QSPI_CR);
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stm32_qspi_dma_free(qspi);
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mutex_destroy(&qspi->lock);
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pm_runtime_put_noidle(qspi->dev);
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pm_runtime_disable(qspi->dev);
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pm_runtime_set_suspended(qspi->dev);
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pm_runtime_dont_use_autosuspend(qspi->dev);
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clk_disable_unprepare(qspi->clk);
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return 0;
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}
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@ -7,6 +7,7 @@
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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@ -58,10 +59,8 @@
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#define SUN6I_FIFO_CTL_TF_RST BIT(31)
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#define SUN6I_FIFO_STA_REG 0x1c
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#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
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#define SUN6I_FIFO_STA_RF_CNT_BITS 0
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#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
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#define SUN6I_FIFO_STA_TF_CNT_BITS 16
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#define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
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#define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
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#define SUN6I_CLK_CTL_REG 0x24
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#define SUN6I_CLK_CTL_CDR2_MASK 0xff
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@ -73,13 +72,10 @@
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#define SUN6I_MAX_XFER_SIZE 0xffffff
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#define SUN6I_BURST_CNT_REG 0x30
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#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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#define SUN6I_XMIT_CNT_REG 0x34
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#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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#define SUN6I_BURST_CTL_CNT_REG 0x38
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#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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#define SUN6I_TXDATA_REG 0x200
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#define SUN6I_RXDATA_REG 0x300
|
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@ -109,21 +105,18 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
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writel(value, sspi->base_addr + reg);
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}
|
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|
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static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
|
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{
|
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u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
|
||||
|
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return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
|
||||
}
|
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|
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static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
|
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{
|
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u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
|
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|
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reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
|
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|
||||
return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
|
||||
}
|
||||
|
||||
static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
|
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{
|
||||
u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
|
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|
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reg |= mask;
|
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
|
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return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
|
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}
|
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|
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static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
|
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@ -134,18 +127,13 @@ static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
|
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
|
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}
|
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|
||||
static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
|
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static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
|
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{
|
||||
u32 reg, cnt;
|
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u32 len;
|
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u8 byte;
|
||||
|
||||
/* See how much data is available */
|
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reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
|
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reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
|
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cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
|
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|
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if (len > cnt)
|
||||
len = cnt;
|
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len = sun6i_spi_get_rx_fifo_count(sspi);
|
||||
|
||||
while (len--) {
|
||||
byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
|
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@ -154,15 +142,16 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
|
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}
|
||||
}
|
||||
|
||||
static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
|
||||
static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
|
||||
{
|
||||
u32 cnt;
|
||||
int len;
|
||||
u8 byte;
|
||||
|
||||
/* See how much data we can fit */
|
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cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
|
||||
|
||||
len = min3(len, (int)cnt, sspi->len);
|
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len = min((int)cnt, sspi->len);
|
||||
|
||||
while (len--) {
|
||||
byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
|
||||
@ -198,10 +187,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
|
||||
struct spi_transfer *tfr)
|
||||
{
|
||||
struct sun6i_spi *sspi = spi_master_get_devdata(master);
|
||||
unsigned int mclk_rate, div, timeout;
|
||||
unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
|
||||
unsigned int start, end, tx_time;
|
||||
unsigned int trig_level;
|
||||
unsigned int tx_len = 0;
|
||||
unsigned int tx_len = 0, rx_len = 0;
|
||||
int ret = 0;
|
||||
u32 reg;
|
||||
|
||||
@ -256,10 +245,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
|
||||
* If it's a TX only transfer, we don't want to fill the RX
|
||||
* FIFO with bogus data
|
||||
*/
|
||||
if (sspi->rx_buf)
|
||||
if (sspi->rx_buf) {
|
||||
reg &= ~SUN6I_TFR_CTL_DHB;
|
||||
else
|
||||
rx_len = tfr->len;
|
||||
} else {
|
||||
reg |= SUN6I_TFR_CTL_DHB;
|
||||
}
|
||||
|
||||
/* We want to control the chip select manually */
|
||||
reg |= SUN6I_TFR_CTL_CS_MANUAL;
|
||||
@ -287,15 +278,15 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
|
||||
* First try CDR2, and if we can't reach the expected
|
||||
* frequency, fall back to CDR1.
|
||||
*/
|
||||
div = mclk_rate / (2 * tfr->speed_hz);
|
||||
if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
|
||||
if (div > 0)
|
||||
div--;
|
||||
|
||||
reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
|
||||
div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
|
||||
div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
|
||||
if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
|
||||
reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
|
||||
tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
|
||||
} else {
|
||||
div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
|
||||
div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
|
||||
reg = SUN6I_CLK_CTL_CDR1(div);
|
||||
tfr->effective_speed_hz = mclk_rate / (1 << div);
|
||||
}
|
||||
|
||||
sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
|
||||
@ -305,20 +296,22 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
|
||||
tx_len = tfr->len;
|
||||
|
||||
/* Setup the counters */
|
||||
sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
|
||||
sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
|
||||
sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
|
||||
SUN6I_BURST_CTL_CNT_STC(tx_len));
|
||||
sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
|
||||
sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
|
||||
sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
|
||||
|
||||
/* Fill the TX FIFO */
|
||||
sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
|
||||
sun6i_spi_fill_fifo(sspi);
|
||||
|
||||
/* Enable the interrupts */
|
||||
sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
|
||||
sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
|
||||
SUN6I_INT_CTL_RF_RDY);
|
||||
reg = SUN6I_INT_CTL_TC;
|
||||
|
||||
if (rx_len > sspi->fifo_depth)
|
||||
reg |= SUN6I_INT_CTL_RF_RDY;
|
||||
if (tx_len > sspi->fifo_depth)
|
||||
sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
|
||||
reg |= SUN6I_INT_CTL_TF_ERQ;
|
||||
|
||||
sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
|
||||
|
||||
/* Start the transfer */
|
||||
reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
|
||||
@ -335,10 +328,8 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
|
||||
dev_name(&spi->dev), tfr->len, tfr->speed_hz,
|
||||
jiffies_to_msecs(end - start), tx_time);
|
||||
ret = -ETIMEDOUT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
|
||||
|
||||
return ret;
|
||||
@ -352,14 +343,14 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
|
||||
/* Transfer complete */
|
||||
if (status & SUN6I_INT_CTL_TC) {
|
||||
sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
|
||||
sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
|
||||
sun6i_spi_drain_fifo(sspi);
|
||||
complete(&sspi->done);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* Receive FIFO 3/4 full */
|
||||
if (status & SUN6I_INT_CTL_RF_RDY) {
|
||||
sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
|
||||
sun6i_spi_drain_fifo(sspi);
|
||||
/* Only clear the interrupt _after_ draining the FIFO */
|
||||
sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
|
||||
return IRQ_HANDLED;
|
||||
@ -367,7 +358,7 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
|
||||
|
||||
/* Transmit FIFO 3/4 empty */
|
||||
if (status & SUN6I_INT_CTL_TF_ERQ) {
|
||||
sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
|
||||
sun6i_spi_fill_fifo(sspi);
|
||||
|
||||
if (!sspi->len)
|
||||
/* nothing left to transmit */
|
||||
|
||||
@ -609,15 +609,20 @@ err_find_dev:
|
||||
static int spidev_release(struct inode *inode, struct file *filp)
|
||||
{
|
||||
struct spidev_data *spidev;
|
||||
int dofree;
|
||||
|
||||
mutex_lock(&device_list_lock);
|
||||
spidev = filp->private_data;
|
||||
filp->private_data = NULL;
|
||||
|
||||
spin_lock_irq(&spidev->spi_lock);
|
||||
/* ... after we unbound from the underlying device? */
|
||||
dofree = (spidev->spi == NULL);
|
||||
spin_unlock_irq(&spidev->spi_lock);
|
||||
|
||||
/* last close? */
|
||||
spidev->users--;
|
||||
if (!spidev->users) {
|
||||
int dofree;
|
||||
|
||||
kfree(spidev->tx_buffer);
|
||||
spidev->tx_buffer = NULL;
|
||||
@ -625,19 +630,14 @@ static int spidev_release(struct inode *inode, struct file *filp)
|
||||
kfree(spidev->rx_buffer);
|
||||
spidev->rx_buffer = NULL;
|
||||
|
||||
spin_lock_irq(&spidev->spi_lock);
|
||||
if (spidev->spi)
|
||||
spidev->speed_hz = spidev->spi->max_speed_hz;
|
||||
|
||||
/* ... after we unbound from the underlying device? */
|
||||
dofree = (spidev->spi == NULL);
|
||||
spin_unlock_irq(&spidev->spi_lock);
|
||||
|
||||
if (dofree)
|
||||
kfree(spidev);
|
||||
else
|
||||
spidev->speed_hz = spidev->spi->max_speed_hz;
|
||||
}
|
||||
#ifdef CONFIG_SPI_SLAVE
|
||||
spi_slave_abort(spidev->spi);
|
||||
if (!dofree)
|
||||
spi_slave_abort(spidev->spi);
|
||||
#endif
|
||||
mutex_unlock(&device_list_lock);
|
||||
|
||||
@ -787,13 +787,13 @@ static int spidev_remove(struct spi_device *spi)
|
||||
{
|
||||
struct spidev_data *spidev = spi_get_drvdata(spi);
|
||||
|
||||
/* prevent new opens */
|
||||
mutex_lock(&device_list_lock);
|
||||
/* make sure ops on existing fds can abort cleanly */
|
||||
spin_lock_irq(&spidev->spi_lock);
|
||||
spidev->spi = NULL;
|
||||
spin_unlock_irq(&spidev->spi_lock);
|
||||
|
||||
/* prevent new opens */
|
||||
mutex_lock(&device_list_lock);
|
||||
list_del(&spidev->device_entry);
|
||||
device_destroy(spidev_class, spidev->devt);
|
||||
clear_bit(MINOR(spidev->devt), minors);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user