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scsi: ufs: exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option

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This option is intended to be set on platforms whose ufspr registers are
only accessible via smc call (such as gs101).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-3-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Peter Griffin 2024-04-26 13:20:00 +01:00 committed by Martin K. Petersen
parent 438e23b61c
commit 449adb00d4
2 changed files with 5 additions and 1 deletions
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5
drivers/ufs/host/ufs-exynos.c
View File

@ -1186,7 +1186,10 @@ static int exynos_ufs_init(struct ufs_hba *hba)
if (ret)
goto out;
exynos_ufs_specify_phy_time_attr(ufs);
exynos_ufs_config_smu(ufs);
if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE))
exynos_ufs_config_smu(ufs);
hba->host->dma_alignment = SZ_4K - 1;
return 0;
out:

1
drivers/ufs/host/ufs-exynos.h
View File

@ -221,6 +221,7 @@ struct exynos_ufs {
#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
};
#define for_each_ufs_rx_lane(ufs, i) \