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mfd: cs42l43: Correct SoundWire port list

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Two ports are missing from the port list, and the wrong port is set
to 4 channels. Also the attempt to list them by function is rather
misguided, there is nothing in the hardware that fixes a particular
port to one function. Factor out the port properties to an actual
struct, fixing the missing ports and correcting the port set to 4
channels.

Fixes: ace6d14481 ("mfd: cs42l43: Add support for cs42l43 core driver")
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20231130115712.669180-1-ckeepax@opensource.cirrus.com
Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Charles Keepax 2023-11-30 11:57:11 +00:00 committed by Lee Jones
parent 1fe13d83e2
commit 47b1b03dc5
1 changed files with 28 additions and 46 deletions
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74
drivers/mfd/cs42l43-sdw.c
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@ -17,13 +17,12 @@
#include "cs42l43.h"
enum cs42l43_sdw_ports {
CS42L43_DMIC_DEC_ASP_PORT = 1,
CS42L43_SPK_TX_PORT,
CS42L43_SPDIF_HP_PORT,
CS42L43_SPK_RX_PORT,
CS42L43_ASP_PORT,
};
#define CS42L43_SDW_PORT(port, chans) { \
.num = port, \
.max_ch = chans, \
.type = SDW_DPN_FULL, \
.max_word = 24, \
}
static const struct regmap_config cs42l43_sdw_regmap = {
.reg_bits = 32,
@ -42,65 +41,48 @@ static const struct regmap_config cs42l43_sdw_regmap = {
.num_reg_defaults = ARRAY_SIZE(cs42l43_reg_default),
};
static const struct sdw_dpn_prop cs42l43_src_port_props[] = {
CS42L43_SDW_PORT(1, 4),
CS42L43_SDW_PORT(2, 2),
CS42L43_SDW_PORT(3, 2),
CS42L43_SDW_PORT(4, 2),
};
static const struct sdw_dpn_prop cs42l43_sink_port_props[] = {
CS42L43_SDW_PORT(5, 2),
CS42L43_SDW_PORT(6, 2),
CS42L43_SDW_PORT(7, 2),
};
static int cs42l43_read_prop(struct sdw_slave *sdw)
{
struct sdw_slave_prop *prop = &sdw->prop;
struct device *dev = &sdw->dev;
struct sdw_dpn_prop *dpn;
unsigned long addr;
int nval;
int i;
u32 bit;
prop->use_domain_irq = true;
prop->paging_support = true;
prop->wake_capable = true;
prop->source_ports = BIT(CS42L43_DMIC_DEC_ASP_PORT) | BIT(CS42L43_SPK_TX_PORT);
prop->sink_ports = BIT(CS42L43_SPDIF_HP_PORT) |
BIT(CS42L43_SPK_RX_PORT) | BIT(CS42L43_ASP_PORT);
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY |
SDW_SCP_INT1_IMPL_DEF;
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
for (i = 0; i < ARRAY_SIZE(cs42l43_src_port_props); i++)
prop->source_ports |= BIT(cs42l43_src_port_props[i].num);
prop->src_dpn_prop = devm_kmemdup(dev, cs42l43_src_port_props,
sizeof(cs42l43_src_port_props), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].max_ch = 2;
dpn[i].type = SDW_DPN_FULL;
dpn[i].max_word = 24;
i++;
}
/*
* All ports are 2 channels max, except the first one,
* CS42L43_DMIC_DEC_ASP_PORT.
*/
dpn[CS42L43_DMIC_DEC_ASP_PORT].max_ch = 4;
for (i = 0; i < ARRAY_SIZE(cs42l43_sink_port_props); i++)
prop->sink_ports |= BIT(cs42l43_sink_port_props[i].num);
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
prop->sink_dpn_prop = devm_kmemdup(dev, cs42l43_sink_port_props,
sizeof(cs42l43_sink_port_props), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].max_ch = 2;
dpn[i].type = SDW_DPN_FULL;
dpn[i].max_word = 24;
i++;
}
return 0;
}