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sh: Add sh7264 device
This is an sh2a device with FPU, video display controller (VDC), 8 serial ports, 3 I2C channels, 2 CAN ports, SD and on-chip USB. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Phil Edworthy
Paul Mundt
parent
7ee94d97aa
commit
51ce30684e
@ -288,6 +288,13 @@ config CPU_SUBTYPE_SH7263
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select SYS_SUPPORTS_CMT
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select SYS_SUPPORTS_MTU2
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config CPU_SUBTYPE_SH7264
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bool "Support SH7264 processor"
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select CPU_SH2A
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select CPU_HAS_FPU
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select SYS_SUPPORTS_CMT
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select SYS_SUPPORTS_MTU2
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config CPU_SUBTYPE_MXG
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bool "Support MX-G processor"
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select CPU_SH2A
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@ -584,7 +591,8 @@ config SH_CLK_CPG
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config SH_CLK_CPG_LEGACY
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depends on SH_CLK_CPG
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def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
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!CPU_SHX3 && !CPU_SUBTYPE_SH7757
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!CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \
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!CPU_SUBTYPE_SH7264
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source "kernel/time/Kconfig"
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@ -18,7 +18,7 @@ enum cpu_type {
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CPU_SH7619,
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/* SH-2A types */
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CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
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CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_MXG,
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/* SH-3 types */
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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@ -7,6 +7,7 @@
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static const char *cpu_name[] = {
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[CPU_SH7201] = "SH7201",
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[CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
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[CPU_SH7264] = "SH7264",
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[CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
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[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
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[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
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@ -11,6 +11,7 @@ obj-$(CONFIG_SH_FPU) += fpu.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
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153
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
Normal file
153
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
Normal file
@ -0,0 +1,153 @@
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/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7264.c
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*
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* SH7264 clock framework support
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*
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* Copyright (C) 2012 Phil Edworthy
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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/* SH7264 registers */
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#define FRQCR 0xfffe0010
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#define STBCR3 0xfffe0408
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#define STBCR4 0xfffe040c
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#define STBCR5 0xfffe0410
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#define STBCR6 0xfffe0414
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#define STBCR7 0xfffe0418
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#define STBCR8 0xfffe041c
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static const unsigned int pll1rate[] = {8, 12};
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static unsigned int pll1_div;
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/* Fixed 32 KHz root clock for RTC */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.rate = 18000000,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long rate = clk->parent->rate / pll1_div;
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return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];
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}
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static struct sh_clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&pll_clk,
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};
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static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_P,
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DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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/* The mask field specifies the div2 entries that are valid */
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
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| CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
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};
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enum { MSTP77, MSTP74, MSTP72,
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MSTP60,
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MSTP35, MSTP34, MSTP33, MSTP32, MSTP30,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
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[MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
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[MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
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[MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
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[MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
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[MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
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[MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
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[MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
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[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("rclk", &r_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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/* MSTP clocks */
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CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
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CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
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CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
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CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
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CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
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CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
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CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
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CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
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CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
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};
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int __init arch_clk_init(void)
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{
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int k, ret = 0;
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if (test_mode_pin(MODE_PIN0)) {
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if (test_mode_pin(MODE_PIN1))
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pll1_div = 3;
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else
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pll1_div = 4;
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} else
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pll1_div = 1;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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return ret;
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}
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@ -29,6 +29,9 @@ void __cpuinit cpu_probe(void)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7263)
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boot_cpu_data.type = CPU_SH7263;
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boot_cpu_data.flags |= CPU_HAS_FPU;
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#elif defined(CONFIG_CPU_SUBTYPE_SH7264)
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boot_cpu_data.type = CPU_SH7264;
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boot_cpu_data.flags |= CPU_HAS_FPU;
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
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boot_cpu_data.type = CPU_SH7206;
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boot_cpu_data.flags |= CPU_HAS_DSP;
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606
arch/sh/kernel/cpu/sh2a/setup-sh7264.c
Normal file
606
arch/sh/kernel/cpu/sh2a/setup-sh7264.c
Normal file
@ -0,0 +1,606 @@
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/*
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* SH7264 Setup
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*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/usb/r8a66597.h>
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#include <linux/sh_timer.h>
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#include <linux/io.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
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USB, VDC3, CMT0, CMT1, BSC, WDT,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
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PWMT1, PWMT2, ADC_ADI,
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SSIF0, SSII1, SSII2, SSII3,
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RSPDIF,
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IIC30, IIC31, IIC32, IIC33,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
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SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
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SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
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SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
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SIO_FIFO, RSPIC0, RSPIC1,
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RCAN0, RCAN1, IEBC, CD_ROMD,
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NFMC, SDHI, RTC,
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SRCC0, SRCC1, DCOMU, OFFI, IFEI,
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/* interrupt groups */
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PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
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INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
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INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
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INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
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INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
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INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
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INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
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INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
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INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
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INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
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INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
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INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
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INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
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INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
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INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
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INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
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INTC_IRQ(USB, 170),
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INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
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INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
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INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
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INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
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INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
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INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
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INTC_IRQ(MTU0_VEF, 183),
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INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
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INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
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INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
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INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
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INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
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INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
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INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
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INTC_IRQ(MTU3_TCI3V, 198),
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INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
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INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
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INTC_IRQ(MTU4_TCI4V, 203),
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INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
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INTC_IRQ(ADC_ADI, 206),
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INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
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INTC_IRQ(SSIF0, 209),
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INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
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INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
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INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
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INTC_IRQ(RSPDIF, 216),
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INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
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INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
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INTC_IRQ(IIC30, 221),
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INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
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INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
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INTC_IRQ(IIC31, 226),
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INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
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INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
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INTC_IRQ(IIC32, 231),
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INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
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INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
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INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
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INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
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INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
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INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
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INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
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INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
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INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
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INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
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||||
INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
|
||||
INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
|
||||
INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
|
||||
INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
|
||||
INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
|
||||
INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
|
||||
|
||||
INTC_IRQ(SIO_FIFO, 264),
|
||||
|
||||
INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
|
||||
INTC_IRQ(RSPIC0, 267),
|
||||
INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
|
||||
INTC_IRQ(RSPIC1, 270),
|
||||
|
||||
INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
|
||||
INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
|
||||
INTC_IRQ(RCAN0, 275),
|
||||
INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
|
||||
INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
|
||||
INTC_IRQ(RCAN1, 280),
|
||||
|
||||
INTC_IRQ(IEBC, 281),
|
||||
|
||||
INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
|
||||
INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
|
||||
INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
|
||||
|
||||
INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
|
||||
INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
|
||||
|
||||
INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
|
||||
INTC_IRQ(SDHI, 294),
|
||||
|
||||
INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
|
||||
INTC_IRQ(RTC, 298),
|
||||
|
||||
INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
|
||||
INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
|
||||
INTC_IRQ(SRCC0, 303),
|
||||
INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
|
||||
INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
|
||||
INTC_IRQ(SRCC1, 308),
|
||||
|
||||
INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
|
||||
INTC_IRQ(DCOMU, 312),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
|
||||
INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
|
||||
INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
|
||||
INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
|
||||
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
|
||||
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
|
||||
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
|
||||
DMAC10, DMAC11 } },
|
||||
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
|
||||
DMAC14, DMAC15 } },
|
||||
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
|
||||
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
|
||||
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
|
||||
MTU2_AB, MTU2_VU } },
|
||||
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
|
||||
MTU4_ABCD, MTU4_TCI4V } },
|
||||
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
|
||||
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
|
||||
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
|
||||
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
|
||||
{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
|
||||
{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
|
||||
{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
|
||||
{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
|
||||
{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe0808, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xfffe8000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 233, 234, 235, 232 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.mapbase = 0xfffe8800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 237, 238, 239, 236 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.mapbase = 0xfffe9000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 241, 242, 243, 240 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.mapbase = 0xfffe9800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 245, 246, 247, 244 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif4_platform_data = {
|
||||
.mapbase = 0xfffea000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 249, 250, 251, 248 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
.platform_data = &scif4_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif5_platform_data = {
|
||||
.mapbase = 0xfffea800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 253, 254, 255, 252 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 5,
|
||||
.dev = {
|
||||
.platform_data = &scif5_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif6_platform_data = {
|
||||
.mapbase = 0xfffeb000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 257, 258, 259, 256 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif6_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 6,
|
||||
.dev = {
|
||||
.platform_data = &scif6_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif7_platform_data = {
|
||||
.mapbase = 0xfffeb800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 261, 262, 263, 260 },
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct platform_device scif7_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 7,
|
||||
.dev = {
|
||||
.platform_data = &scif7_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt0_platform_data = {
|
||||
.channel_offset = 0x02,
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||
};
|
||||
|
||||
static struct resource cmt0_resources[] = {
|
||||
[0] = {
|
||||
.name = "CMT0",
|
||||
.start = 0xfffec002,
|
||||
.end = 0xfffec007,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 175,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt0_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt0_platform_data,
|
||||
},
|
||||
.resource = cmt0_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt0_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt1_platform_data = {
|
||||
.name = "CMT1",
|
||||
.channel_offset = 0x08,
|
||||
.timer_bit = 1,
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||||
};
|
||||
|
||||
static struct resource cmt1_resources[] = {
|
||||
[0] = {
|
||||
.name = "CMT1",
|
||||
.start = 0xfffec008,
|
||||
.end = 0xfffec00d,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 176,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt1_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &cmt1_platform_data,
|
||||
},
|
||||
.resource = cmt1_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt1_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config mtu2_0_platform_data = {
|
||||
.name = "MTU2_0",
|
||||
.channel_offset = -0x80,
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource mtu2_0_resources[] = {
|
||||
[0] = {
|
||||
.name = "MTU2_0",
|
||||
.start = 0xfffe4300,
|
||||
.end = 0xfffe4326,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 179,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_0_device = {
|
||||
.name = "sh_mtu2",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mtu2_0_platform_data,
|
||||
},
|
||||
.resource = mtu2_0_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_0_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config mtu2_1_platform_data = {
|
||||
.name = "MTU2_1",
|
||||
.channel_offset = -0x100,
|
||||
.timer_bit = 1,
|
||||
.clockevent_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource mtu2_1_resources[] = {
|
||||
[0] = {
|
||||
.name = "MTU2_1",
|
||||
.start = 0xfffe4380,
|
||||
.end = 0xfffe4390,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 186,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_1_device = {
|
||||
.name = "sh_mtu2",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &mtu2_1_platform_data,
|
||||
},
|
||||
.resource = mtu2_1_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_1_resources),
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe6000,
|
||||
.end = 0xfffe6000 + 0x30 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 296,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
/* USB Host */
|
||||
static void usb_port_power(int port, int power)
|
||||
{
|
||||
__raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
|
||||
}
|
||||
|
||||
static struct r8a66597_platdata r8a66597_data = {
|
||||
.on_chip = 1,
|
||||
.endian = 1,
|
||||
.port_power = usb_port_power,
|
||||
};
|
||||
|
||||
static struct resource r8a66597_usb_host_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffffc000,
|
||||
.end = 0xffffc0e4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 170,
|
||||
.end = 170,
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device r8a66597_usb_host_device = {
|
||||
.name = "r8a66597_hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = NULL, /* not use dma */
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &r8a66597_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
|
||||
.resource = r8a66597_usb_host_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7264_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt0_device,
|
||||
&cmt1_device,
|
||||
&mtu2_0_device,
|
||||
&mtu2_1_device,
|
||||
&rtc_device,
|
||||
&r8a66597_usb_host_device,
|
||||
};
|
||||
|
||||
static int __init sh7264_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7264_devices,
|
||||
ARRAY_SIZE(sh7264_devices));
|
||||
}
|
||||
arch_initcall(sh7264_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *sh7264_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt0_device,
|
||||
&cmt1_device,
|
||||
&mtu2_0_device,
|
||||
&mtu2_1_device,
|
||||
};
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
early_platform_add_devices(sh7264_early_devices,
|
||||
ARRAY_SIZE(sh7264_early_devices));
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user