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ASoC: mediatek: mt8186: support audio clock control in platform driver
Add audio clock control with CCF interface. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Link: https://lore.kernel.org/r/20220523132858.22166-12-jiaxin.yu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jiaxin Yu
Mark Brown
parent
ae92dcbee8
commit
55b423d562
651
sound/soc/mediatek/mt8186/mt8186-afe-clk.c
Normal file
651
sound/soc/mediatek/mt8186/mt8186-afe-clk.c
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@ -0,0 +1,651 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include "mt8186-afe-common.h"
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#include "mt8186-afe-clk.h"
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#include "mt8186-audsys-clk.h"
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static DEFINE_MUTEX(mutex_request_dram);
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static const char *aud_clks[CLK_NUM] = {
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[CLK_AFE] = "aud_afe_clk",
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[CLK_DAC] = "aud_dac_clk",
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[CLK_DAC_PREDIS] = "aud_dac_predis_clk",
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[CLK_ADC] = "aud_adc_clk",
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[CLK_TML] = "aud_tml_clk",
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[CLK_APLL22M] = "aud_apll22m_clk",
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[CLK_APLL24M] = "aud_apll24m_clk",
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[CLK_APLL1_TUNER] = "aud_apll_tuner_clk",
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[CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
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[CLK_TDM] = "aud_tdm_clk",
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[CLK_NLE] = "aud_nle_clk",
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[CLK_DAC_HIRES] = "aud_dac_hires_clk",
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[CLK_ADC_HIRES] = "aud_adc_hires_clk",
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[CLK_I2S1_BCLK] = "aud_i2s1_bclk",
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[CLK_I2S2_BCLK] = "aud_i2s2_bclk",
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[CLK_I2S3_BCLK] = "aud_i2s3_bclk",
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[CLK_I2S4_BCLK] = "aud_i2s4_bclk",
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[CLK_CONNSYS_I2S_ASRC] = "aud_connsys_i2s_asrc",
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[CLK_GENERAL1_ASRC] = "aud_general1_asrc",
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[CLK_GENERAL2_ASRC] = "aud_general2_asrc",
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[CLK_ADC_HIRES_TML] = "aud_adc_hires_tml",
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[CLK_ADDA6_ADC] = "aud_adda6_adc",
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[CLK_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
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[CLK_3RD_DAC] = "aud_3rd_dac",
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[CLK_3RD_DAC_PREDIS] = "aud_3rd_dac_predis",
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[CLK_3RD_DAC_TML] = "aud_3rd_dac_tml",
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[CLK_3RD_DAC_HIRES] = "aud_3rd_dac_hires",
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[CLK_ETDM_IN1_BCLK] = "aud_etdm_in1_bclk",
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[CLK_ETDM_OUT1_BCLK] = "aud_etdm_out1_bclk",
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[CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
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[CLK_INFRA_AUDIO_26M] = "mtkaif_26m_clk",
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[CLK_MUX_AUDIO] = "top_mux_audio",
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[CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int",
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[CLK_TOP_MAINPLL_D2_D4] = "top_mainpll_d2_d4",
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[CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
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[CLK_TOP_APLL1_CK] = "top_apll1_ck",
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[CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
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[CLK_TOP_APLL2_CK] = "top_apll2_ck",
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[CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
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[CLK_TOP_APLL1_D8] = "top_apll1_d8",
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[CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
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[CLK_TOP_APLL2_D8] = "top_apll2_d8",
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[CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h",
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[CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
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[CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
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[CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
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[CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
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[CLK_TOP_TDM_M_SEL] = "top_tdm_m_sel",
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[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
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[CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
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[CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
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[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
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[CLK_TOP_APLL12_DIV_TDM] = "top_apll12_div_tdm",
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[CLK_CLK26M] = "top_clk26m_clk",
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};
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int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe,
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int clk_id)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int ret;
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ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
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afe_priv->clk[clk_id]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_MUX_AUDIOINTBUS],
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aud_clks[clk_id], ret);
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return ret;
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}
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return 0;
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}
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static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int ret;
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if (enable) {
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
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return ret;
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}
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
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afe_priv->clk[CLK_TOP_APLL1_CK]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_1],
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aud_clks[CLK_TOP_APLL1_CK], ret);
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return ret;
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}
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/* 180.6336 / 8 = 22.5792MHz */
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
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return ret;
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}
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
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afe_priv->clk[CLK_TOP_APLL1_D8]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
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aud_clks[CLK_TOP_APLL1_D8], ret);
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return ret;
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}
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} else {
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
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afe_priv->clk[CLK_CLK26M]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
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aud_clks[CLK_CLK26M], ret);
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return ret;
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}
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
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afe_priv->clk[CLK_CLK26M]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_1],
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aud_clks[CLK_CLK26M], ret);
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return ret;
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}
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
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}
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return 0;
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}
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static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int ret;
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if (enable) {
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
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return ret;
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}
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
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afe_priv->clk[CLK_TOP_APLL2_CK]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_2],
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aud_clks[CLK_TOP_APLL2_CK], ret);
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return ret;
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}
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/* 196.608 / 8 = 24.576MHz */
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ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
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return ret;
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}
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
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afe_priv->clk[CLK_TOP_APLL2_D8]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
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aud_clks[CLK_TOP_APLL2_D8], ret);
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return ret;
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}
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} else {
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
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afe_priv->clk[CLK_CLK26M]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
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aud_clks[CLK_CLK26M], ret);
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return ret;
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}
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
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afe_priv->clk[CLK_CLK26M]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUD_2],
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aud_clks[CLK_CLK26M], ret);
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return ret;
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}
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clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
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}
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return 0;
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}
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int mt8186_afe_enable_cgs(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int ret = 0;
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int i;
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for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++) {
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ret = clk_prepare_enable(afe_priv->clk[i]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[i], ret);
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return ret;
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}
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}
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return 0;
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}
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void mt8186_afe_disable_cgs(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int i;
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for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++)
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clk_disable_unprepare(afe_priv->clk[i]);
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}
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int mt8186_afe_enable_clock(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int ret = 0;
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ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
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goto clk_infra_sys_audio_err;
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}
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ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
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goto clk_infra_audio_26m_err;
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}
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ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_MUX_AUDIO], ret);
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goto clk_mux_audio_err;
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}
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ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
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afe_priv->clk[CLK_CLK26M]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_MUX_AUDIO],
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aud_clks[CLK_CLK26M], ret);
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goto clk_mux_audio_err;
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}
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ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
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goto clk_mux_audio_intbus_err;
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}
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ret = mt8186_set_audio_int_bus_parent(afe,
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CLK_TOP_MAINPLL_D2_D4);
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if (ret)
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goto clk_mux_audio_intbus_parent_err;
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ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
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afe_priv->clk[CLK_TOP_APLL2_CK]);
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if (ret) {
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dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
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__func__, aud_clks[CLK_TOP_MUX_AUDIO_H],
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aud_clks[CLK_TOP_APLL2_CK], ret);
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goto clk_mux_audio_h_parent_err;
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}
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ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
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if (ret) {
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dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_AFE], ret);
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goto clk_afe_err;
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}
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return 0;
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clk_afe_err:
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clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
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clk_mux_audio_h_parent_err:
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clk_mux_audio_intbus_parent_err:
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mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
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clk_mux_audio_intbus_err:
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
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clk_mux_audio_err:
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
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clk_infra_sys_audio_err:
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clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
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clk_infra_audio_26m_err:
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clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
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return ret;
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}
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void mt8186_afe_disable_clock(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
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mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
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clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
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clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
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}
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int mt8186_afe_suspend_clock(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int ret;
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/* set audio int bus to 26M */
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ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
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if (ret) {
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dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
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goto clk_mux_audio_intbus_err;
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}
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ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
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if (ret)
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goto clk_mux_audio_intbus_parent_err;
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
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return 0;
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clk_mux_audio_intbus_parent_err:
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mt8186_set_audio_int_bus_parent(afe, CLK_TOP_MAINPLL_D2_D4);
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clk_mux_audio_intbus_err:
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clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
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return ret;
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}
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int mt8186_afe_resume_clock(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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int ret;
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/* set audio int bus to normal working clock */
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ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
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if (ret) {
|
||||
dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
||||
__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
|
||||
goto clk_mux_audio_intbus_err;
|
||||
}
|
||||
ret = mt8186_set_audio_int_bus_parent(afe,
|
||||
CLK_TOP_MAINPLL_D2_D4);
|
||||
if (ret)
|
||||
goto clk_mux_audio_intbus_parent_err;
|
||||
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
|
||||
|
||||
return 0;
|
||||
|
||||
clk_mux_audio_intbus_parent_err:
|
||||
mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
|
||||
clk_mux_audio_intbus_err:
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mt8186_apll1_enable(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8186_afe_private *afe_priv = afe->platform_priv;
|
||||
int ret;
|
||||
|
||||
/* setting for APLL */
|
||||
apll1_mux_setting(afe, true);
|
||||
|
||||
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
||||
__func__, aud_clks[CLK_APLL22M], ret);
|
||||
goto err_clk_apll22m;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
||||
__func__, aud_clks[CLK_APLL1_TUNER], ret);
|
||||
goto err_clk_apll1_tuner;
|
||||
}
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832);
|
||||
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
|
||||
AFE_22M_ON_MASK_SFT, BIT(AFE_22M_ON_SFT));
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_apll1_tuner:
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
|
||||
err_clk_apll22m:
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void mt8186_apll1_disable(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8186_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
|
||||
AFE_22M_ON_MASK_SFT, 0);
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0);
|
||||
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
|
||||
|
||||
apll1_mux_setting(afe, false);
|
||||
}
|
||||
|
||||
int mt8186_apll2_enable(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8186_afe_private *afe_priv = afe->platform_priv;
|
||||
int ret;
|
||||
|
||||
/* setting for APLL */
|
||||
apll2_mux_setting(afe, true);
|
||||
|
||||
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
||||
__func__, aud_clks[CLK_APLL24M], ret);
|
||||
goto err_clk_apll24m;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
||||
__func__, aud_clks[CLK_APLL2_TUNER], ret);
|
||||
goto err_clk_apll2_tuner;
|
||||
}
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634);
|
||||
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
|
||||
AFE_24M_ON_MASK_SFT, BIT(AFE_24M_ON_SFT));
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_apll2_tuner:
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
|
||||
err_clk_apll24m:
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void mt8186_apll2_disable(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8186_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
|
||||
AFE_24M_ON_MASK_SFT, 0);
|
||||
|
||||
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0);
|
||||
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
|
||||
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
|
||||
|
||||
apll2_mux_setting(afe, false);
|
||||
}
|
||||
|
||||
int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll)
|
||||
{
|
||||
return (apll == MT8186_APLL1) ? 180633600 : 196608000;
|
||||
}
|
||||
|
||||
int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
|
||||
{
|
||||
return ((rate % 8000) == 0) ? MT8186_APLL2 : MT8186_APLL1;
|
||||
}
|
||||
|
||||
int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
|
||||
{
|
||||
if (strcmp(name, APLL1_W_NAME) == 0)
|
||||
return MT8186_APLL1;
|
||||
|
||||
return MT8186_APLL2;
|
||||
}
|
||||
|
||||
/* mck */
|
||||
struct mt8186_mck_div {
|
||||
u32 m_sel_id;
|
||||
u32 div_clk_id;
|
||||
};
|
||||
|
||||
static const struct mt8186_mck_div mck_div[MT8186_MCK_NUM] = {
|
||||
[MT8186_I2S0_MCK] = {
|
||||
.m_sel_id = CLK_TOP_I2S0_M_SEL,
|
||||
.div_clk_id = CLK_TOP_APLL12_DIV0,
|
||||
},
|
||||
[MT8186_I2S1_MCK] = {
|
||||
.m_sel_id = CLK_TOP_I2S1_M_SEL,
|
||||
.div_clk_id = CLK_TOP_APLL12_DIV1,
|
||||
},
|
||||
[MT8186_I2S2_MCK] = {
|
||||
.m_sel_id = CLK_TOP_I2S2_M_SEL,
|
||||
.div_clk_id = CLK_TOP_APLL12_DIV2,
|
||||
},
|
||||
[MT8186_I2S4_MCK] = {
|
||||
.m_sel_id = CLK_TOP_I2S4_M_SEL,
|
||||
.div_clk_id = CLK_TOP_APLL12_DIV4,
|
||||
},
|
||||
[MT8186_TDM_MCK] = {
|
||||
.m_sel_id = CLK_TOP_TDM_M_SEL,
|
||||
.div_clk_id = CLK_TOP_APLL12_DIV_TDM,
|
||||
},
|
||||
};
|
||||
|
||||
int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
|
||||
{
|
||||
struct mt8186_afe_private *afe_priv = afe->platform_priv;
|
||||
int apll = mt8186_get_apll_by_rate(afe, rate);
|
||||
int apll_clk_id = apll == MT8186_APLL1 ?
|
||||
CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
|
||||
int m_sel_id = mck_div[mck_id].m_sel_id;
|
||||
int div_clk_id = mck_div[mck_id].div_clk_id;
|
||||
int ret;
|
||||
|
||||
/* select apll */
|
||||
if (m_sel_id >= 0) {
|
||||
ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
|
||||
__func__, aud_clks[m_sel_id], ret);
|
||||
return ret;
|
||||
}
|
||||
ret = clk_set_parent(afe_priv->clk[m_sel_id],
|
||||
afe_priv->clk[apll_clk_id]);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
|
||||
__func__, aud_clks[m_sel_id],
|
||||
aud_clks[apll_clk_id], ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* enable div, set rate */
|
||||
ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
|
||||
__func__, aud_clks[div_clk_id], ret);
|
||||
return ret;
|
||||
}
|
||||
ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
|
||||
__func__, aud_clks[div_clk_id], rate, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id)
|
||||
{
|
||||
struct mt8186_afe_private *afe_priv = afe->platform_priv;
|
||||
int m_sel_id = mck_div[mck_id].m_sel_id;
|
||||
int div_clk_id = mck_div[mck_id].div_clk_id;
|
||||
|
||||
clk_disable_unprepare(afe_priv->clk[div_clk_id]);
|
||||
if (m_sel_id >= 0)
|
||||
clk_disable_unprepare(afe_priv->clk[m_sel_id]);
|
||||
}
|
||||
|
||||
int mt8186_init_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8186_afe_private *afe_priv = afe->platform_priv;
|
||||
struct device_node *of_node = afe->dev->of_node;
|
||||
int i = 0;
|
||||
|
||||
mt8186_audsys_clk_register(afe);
|
||||
|
||||
afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
|
||||
GFP_KERNEL);
|
||||
if (!afe_priv->clk)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < CLK_NUM; i++) {
|
||||
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
|
||||
if (IS_ERR(afe_priv->clk[i])) {
|
||||
dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
|
||||
__func__,
|
||||
aud_clks[i], PTR_ERR(afe_priv->clk[i]));
|
||||
afe_priv->clk[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
|
||||
"mediatek,apmixedsys");
|
||||
if (IS_ERR(afe_priv->apmixedsys)) {
|
||||
dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
|
||||
__func__, PTR_ERR(afe_priv->apmixedsys));
|
||||
return PTR_ERR(afe_priv->apmixedsys);
|
||||
}
|
||||
|
||||
afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
|
||||
"mediatek,topckgen");
|
||||
if (IS_ERR(afe_priv->topckgen)) {
|
||||
dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
|
||||
__func__, PTR_ERR(afe_priv->topckgen));
|
||||
return PTR_ERR(afe_priv->topckgen);
|
||||
}
|
||||
|
||||
afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
|
||||
"mediatek,infracfg");
|
||||
if (IS_ERR(afe_priv->infracfg)) {
|
||||
dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",
|
||||
__func__, PTR_ERR(afe_priv->infracfg));
|
||||
return PTR_ERR(afe_priv->infracfg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mt8186_deinit_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
mt8186_audsys_clk_unregister(afe);
|
||||
}
|
||||
106
sound/soc/mediatek/mt8186/mt8186-afe-clk.h
Normal file
106
sound/soc/mediatek/mt8186/mt8186-afe-clk.h
Normal file
@ -0,0 +1,106 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* mt8186-afe-clk.h -- Mediatek 8186 afe clock ctrl definition
|
||||
*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT8186_AFE_CLOCK_CTRL_H_
|
||||
#define _MT8186_AFE_CLOCK_CTRL_H_
|
||||
|
||||
#define PERI_BUS_DCM_CTRL 0x74
|
||||
|
||||
/* APLL */
|
||||
#define APLL1_W_NAME "APLL1"
|
||||
#define APLL2_W_NAME "APLL2"
|
||||
enum {
|
||||
MT8186_APLL1 = 0,
|
||||
MT8186_APLL2,
|
||||
};
|
||||
|
||||
enum {
|
||||
CLK_AFE = 0,
|
||||
CLK_DAC,
|
||||
CLK_DAC_PREDIS,
|
||||
CLK_ADC,
|
||||
CLK_TML,
|
||||
CLK_APLL22M,
|
||||
CLK_APLL24M,
|
||||
CLK_APLL1_TUNER,
|
||||
CLK_APLL2_TUNER,
|
||||
CLK_TDM,
|
||||
CLK_NLE,
|
||||
CLK_DAC_HIRES,
|
||||
CLK_ADC_HIRES,
|
||||
CLK_I2S1_BCLK,
|
||||
CLK_I2S2_BCLK,
|
||||
CLK_I2S3_BCLK,
|
||||
CLK_I2S4_BCLK,
|
||||
CLK_CONNSYS_I2S_ASRC,
|
||||
CLK_GENERAL1_ASRC,
|
||||
CLK_GENERAL2_ASRC,
|
||||
CLK_ADC_HIRES_TML,
|
||||
CLK_ADDA6_ADC,
|
||||
CLK_ADDA6_ADC_HIRES,
|
||||
CLK_3RD_DAC,
|
||||
CLK_3RD_DAC_PREDIS,
|
||||
CLK_3RD_DAC_TML,
|
||||
CLK_3RD_DAC_HIRES,
|
||||
CLK_ETDM_IN1_BCLK,
|
||||
CLK_ETDM_OUT1_BCLK,
|
||||
CLK_INFRA_SYS_AUDIO,
|
||||
CLK_INFRA_AUDIO_26M,
|
||||
CLK_MUX_AUDIO,
|
||||
CLK_MUX_AUDIOINTBUS,
|
||||
CLK_TOP_MAINPLL_D2_D4,
|
||||
/* apll related mux */
|
||||
CLK_TOP_MUX_AUD_1,
|
||||
CLK_TOP_APLL1_CK,
|
||||
CLK_TOP_MUX_AUD_2,
|
||||
CLK_TOP_APLL2_CK,
|
||||
CLK_TOP_MUX_AUD_ENG1,
|
||||
CLK_TOP_APLL1_D8,
|
||||
CLK_TOP_MUX_AUD_ENG2,
|
||||
CLK_TOP_APLL2_D8,
|
||||
CLK_TOP_MUX_AUDIO_H,
|
||||
CLK_TOP_I2S0_M_SEL,
|
||||
CLK_TOP_I2S1_M_SEL,
|
||||
CLK_TOP_I2S2_M_SEL,
|
||||
CLK_TOP_I2S4_M_SEL,
|
||||
CLK_TOP_TDM_M_SEL,
|
||||
CLK_TOP_APLL12_DIV0,
|
||||
CLK_TOP_APLL12_DIV1,
|
||||
CLK_TOP_APLL12_DIV2,
|
||||
CLK_TOP_APLL12_DIV4,
|
||||
CLK_TOP_APLL12_DIV_TDM,
|
||||
CLK_CLK26M,
|
||||
CLK_NUM
|
||||
};
|
||||
|
||||
struct mtk_base_afe;
|
||||
int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, int clk_id);
|
||||
int mt8186_init_clock(struct mtk_base_afe *afe);
|
||||
void mt8186_deinit_clock(struct mtk_base_afe *afe);
|
||||
int mt8186_afe_enable_cgs(struct mtk_base_afe *afe);
|
||||
void mt8186_afe_disable_cgs(struct mtk_base_afe *afe);
|
||||
int mt8186_afe_enable_clock(struct mtk_base_afe *afe);
|
||||
void mt8186_afe_disable_clock(struct mtk_base_afe *afe);
|
||||
int mt8186_afe_suspend_clock(struct mtk_base_afe *afe);
|
||||
int mt8186_afe_resume_clock(struct mtk_base_afe *afe);
|
||||
|
||||
int mt8186_apll1_enable(struct mtk_base_afe *afe);
|
||||
void mt8186_apll1_disable(struct mtk_base_afe *afe);
|
||||
|
||||
int mt8186_apll2_enable(struct mtk_base_afe *afe);
|
||||
void mt8186_apll2_disable(struct mtk_base_afe *afe);
|
||||
|
||||
int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll);
|
||||
int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
|
||||
int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
|
||||
|
||||
/* these will be replaced by using CCF */
|
||||
int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
|
||||
void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user