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powerpc: Fix setting FSCR for HV=0 and on secondary CPUs

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Currently we only set the FSCR (Facility Status and Control Register) when HV=1
but this feature is available when HV=0 also.  This patch sets FSCR when HV=0.

Also, we currently only set the FSCR on the master CPU.  This patch also sets
the FSCR on secondary CPUs.

Signed-off-by: Michael Neuling <mikey@neuling.org>
cc: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Michael Neuling 2013-03-04 19:45:50 +00:00 committed by Benjamin Herrenschmidt
parent 8170a83f15
commit 57d231678a
1 changed files with 2 additions and 1 deletions
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3
arch/powerpc/kernel/cpu_setup_power.S
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@ -48,6 +48,7 @@ _GLOBAL(__restore_cpu_power7)
_GLOBAL(__setup_cpu_power8) _GLOBAL(__setup_cpu_power8)
mflr r11 mflr r11
bl __init_FSCR
bl __init_hvmode_206 bl __init_hvmode_206
mtlr r11 mtlr r11
beqlr beqlr
@ -56,13 +57,13 @@ _GLOBAL(__setup_cpu_power8)
mfspr r3,SPRN_LPCR mfspr r3,SPRN_LPCR
oris r3, r3, LPCR_AIL_3@h oris r3, r3, LPCR_AIL_3@h
bl __init_LPCR bl __init_LPCR
bl __init_FSCR
bl __init_TLB bl __init_TLB
mtlr r11 mtlr r11
blr blr
_GLOBAL(__restore_cpu_power8) _GLOBAL(__restore_cpu_power8)
mflr r11 mflr r11
bl __init_FSCR
mfmsr r3 mfmsr r3
rldicl. r0,r3,4,63 rldicl. r0,r3,4,63
beqlr beqlr