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clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()
Code in rzg2l_cpg_reset() is equivalent with the combined code of rzg2l_cpg_assert() and rzg2l_cpg_deassert(). There is no need to have different versions thus re-use rzg2l_cpg_assert() and rzg2l_cpg_deassert(). Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231120070024.4079344-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -1410,29 +1410,6 @@ fail:
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#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
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#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
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static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
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const struct rzg2l_cpg_info *info = priv->info;
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unsigned int reg = info->resets[id].off;
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u32 dis = BIT(info->resets[id].bit);
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u32 we = dis << 16;
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dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
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/* Reset module */
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writel(we, priv->base + CLK_RST_R(reg));
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/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
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udelay(35);
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/* Release module from reset state */
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writel(we | dis, priv->base + CLK_RST_R(reg));
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return 0;
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}
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static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
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static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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unsigned long id)
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{
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{
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@ -1463,6 +1440,21 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
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return 0;
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return 0;
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}
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}
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static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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ret = rzg2l_cpg_assert(rcdev, id);
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if (ret)
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return ret;
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/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
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udelay(35);
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return rzg2l_cpg_deassert(rcdev, id);
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}
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static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
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static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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unsigned long id)
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{
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{
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