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ASoC: tlv320aic3x: Clear BIT_CLK_MASTER and WORD_CLK_MASTER bits for for slave mode

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According to the datasheet:

Page0 / Register8: Audio Serial Data interface Control Register A
BIT 7: Bit Clock Directional Control
        0: Bit clock is an input (slave mode)
        1: Bit clock is an output (master mode)

BIT 6: Word Clock Directional Control
        0: Word clock is an input (slave mode)
        1: Word clock is an output (master mode)

Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode,
but does not clear these bits for slave mode.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Axel Lin 2011-10-27 16:38:42 +08:00 committed by Mark Brown
parent b01a3d69f8
commit 68e4798143
1 changed files with 1 additions and 0 deletions
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1
sound/soc/codecs/tlv320aic3x.c
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@ -1023,6 +1023,7 @@ static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
break;
case SND_SOC_DAIFMT_CBS_CFS:
aic3x->master = 0;
iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
break;
default:
return -EINVAL;