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Watchdog: fix clearing of the watchdog interrupt

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The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to
clear.  If we read the register, mask off the watchdog bit, and
write it back, we're actually clearing every interrupt which wasn't
pending at the time we read the register - and that is racy.

Fix this to only write ~WATCHDOG_BIT to the register, which means
we write as zero only the watchdog bit.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Russell King 2013-06-18 17:20:32 +01:00 committed by Wim Van Sebroeck
parent fa142ff5b3
commit 6910ceb5ca
1 changed files with 1 additions and 3 deletions
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4
drivers/watchdog/orion_wdt.c
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@ -70,9 +70,7 @@ static int orion_wdt_start(struct watchdog_device *wdt_dev)
writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL);
/* Clear watchdog timer interrupt */
reg = readl(BRIDGE_CAUSE);
reg &= ~WDT_INT_REQ;
writel(reg, BRIDGE_CAUSE);
writel(~WDT_INT_REQ, BRIDGE_CAUSE);
/* Enable watchdog timer */
reg = readl(wdt_reg + TIMER_CTRL);