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bpf, docs: Add table captions
As suggested by Ines Robles in his IETF GENART review at https://datatracker.ietf.org/doc/review-ietf-bpf-isa-02-genart-lc-robles-2024-05-16/ Signed-off-by: Dave Thaler <dthaler1968@gmail.com> Link: https://lore.kernel.org/r/20240524164618.18894-1-dthaler1968@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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Dave Thaler
Alexei Starovoitov
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6a6d8b6f00
@ -32,7 +32,7 @@ Types
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This document refers to integer types with the notation `SN` to specify
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This document refers to integer types with the notation `SN` to specify
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a type's signedness (`S`) and bit width (`N`), respectively.
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a type's signedness (`S`) and bit width (`N`), respectively.
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.. table:: Meaning of signedness notation.
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.. table:: Meaning of signedness notation
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==== =========
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==== =========
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S Meaning
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S Meaning
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@ -41,7 +41,7 @@ a type's signedness (`S`) and bit width (`N`), respectively.
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s signed
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s signed
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==== =========
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==== =========
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.. table:: Meaning of bit-width notation.
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.. table:: Meaning of bit-width notation
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===== =========
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===== =========
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N Bit width
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N Bit width
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@ -263,18 +263,20 @@ Instruction classes
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The three least significant bits of the 'opcode' field store the instruction class:
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The three least significant bits of the 'opcode' field store the instruction class:
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===== ===== =============================== ===================================
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.. table:: Instruction class
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class value description reference
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===== ===== =============================== ===================================
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===== ===== =============================== ===================================
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LD 0x0 non-standard load operations `Load and store instructions`_
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class value description reference
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LDX 0x1 load into register operations `Load and store instructions`_
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===== ===== =============================== ===================================
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ST 0x2 store from immediate operations `Load and store instructions`_
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LD 0x0 non-standard load operations `Load and store instructions`_
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STX 0x3 store from register operations `Load and store instructions`_
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LDX 0x1 load into register operations `Load and store instructions`_
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ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_
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ST 0x2 store from immediate operations `Load and store instructions`_
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JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_
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STX 0x3 store from register operations `Load and store instructions`_
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JMP32 0x6 32-bit jump operations `Arithmetic and jump instructions`_
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ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_
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ALU64 0x7 64-bit arithmetic operations `Arithmetic and jump instructions`_
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JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_
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===== ===== =============================== ===================================
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JMP32 0x6 32-bit jump operations `Arithmetic and jump instructions`_
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ALU64 0x7 64-bit arithmetic operations `Arithmetic and jump instructions`_
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===== ===== =============================== ===================================
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Arithmetic and jump instructions
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Arithmetic and jump instructions
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================================
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================================
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@ -292,6 +294,8 @@ For arithmetic and jump instructions (``ALU``, ``ALU64``, ``JMP`` and
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**s (source)**
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**s (source)**
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the source operand location, which unless otherwise specified is one of:
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the source operand location, which unless otherwise specified is one of:
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.. table:: Source operand location
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====== ===== ==============================================
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====== ===== ==============================================
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source value description
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source value description
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====== ===== ==============================================
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====== ===== ==============================================
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@ -312,27 +316,29 @@ The 'code' field encodes the operation as below, where 'src' refers to the
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the source operand and 'dst' refers to the value of the destination
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the source operand and 'dst' refers to the value of the destination
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register.
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register.
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===== ===== ======= ==========================================================
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.. table:: Arithmetic instructions
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name code offset description
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===== ===== ======= ==========================================================
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===== ===== ======= ==========================================================
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ADD 0x0 0 dst += src
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name code offset description
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SUB 0x1 0 dst -= src
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===== ===== ======= ==========================================================
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MUL 0x2 0 dst \*= src
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ADD 0x0 0 dst += src
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DIV 0x3 0 dst = (src != 0) ? (dst / src) : 0
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SUB 0x1 0 dst -= src
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SDIV 0x3 1 dst = (src != 0) ? (dst s/ src) : 0
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MUL 0x2 0 dst \*= src
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OR 0x4 0 dst \|= src
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DIV 0x3 0 dst = (src != 0) ? (dst / src) : 0
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AND 0x5 0 dst &= src
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SDIV 0x3 1 dst = (src != 0) ? (dst s/ src) : 0
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LSH 0x6 0 dst <<= (src & mask)
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OR 0x4 0 dst \|= src
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RSH 0x7 0 dst >>= (src & mask)
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AND 0x5 0 dst &= src
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NEG 0x8 0 dst = -dst
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LSH 0x6 0 dst <<= (src & mask)
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MOD 0x9 0 dst = (src != 0) ? (dst % src) : dst
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RSH 0x7 0 dst >>= (src & mask)
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SMOD 0x9 1 dst = (src != 0) ? (dst s% src) : dst
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NEG 0x8 0 dst = -dst
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XOR 0xa 0 dst ^= src
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MOD 0x9 0 dst = (src != 0) ? (dst % src) : dst
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MOV 0xb 0 dst = src
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SMOD 0x9 1 dst = (src != 0) ? (dst s% src) : dst
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MOVSX 0xb 8/16/32 dst = (s8,s16,s32)src
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XOR 0xa 0 dst ^= src
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ARSH 0xc 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask)
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MOV 0xb 0 dst = src
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END 0xd 0 byte swap operations (see `Byte swap instructions`_ below)
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MOVSX 0xb 8/16/32 dst = (s8,s16,s32)src
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===== ===== ======= ==========================================================
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ARSH 0xc 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask)
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END 0xd 0 byte swap operations (see `Byte swap instructions`_ below)
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===== ===== ======= ==========================================================
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Underflow and overflow are allowed during arithmetic operations, meaning
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Underflow and overflow are allowed during arithmetic operations, meaning
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the 64-bit or 32-bit value will wrap. If BPF program execution would
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the 64-bit or 32-bit value will wrap. If BPF program execution would
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@ -426,13 +432,15 @@ select what byte order the operation converts from or to. For
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``ALU64``, the 1-bit source operand field in the opcode is reserved
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``ALU64``, the 1-bit source operand field in the opcode is reserved
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and MUST be set to 0.
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and MUST be set to 0.
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===== ======== ===== =================================================
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.. table:: Byte swap instructions
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class source value description
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===== ======== ===== =================================================
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===== ======== ===== =================================================
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ALU TO_LE 0 convert between host byte order and little endian
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class source value description
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ALU TO_BE 1 convert between host byte order and big endian
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===== ======== ===== =================================================
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ALU64 Reserved 0 do byte swap unconditionally
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ALU TO_LE 0 convert between host byte order and little endian
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===== ======== ===== =================================================
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ALU TO_BE 1 convert between host byte order and big endian
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ALU64 Reserved 0 do byte swap unconditionally
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===== ======== ===== =================================================
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The 'imm' field encodes the width of the swap operations. The following widths
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The 'imm' field encodes the width of the swap operations. The following widths
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are supported: 16, 32 and 64. Width 64 operations belong to the base64
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are supported: 16, 32 and 64. Width 64 operations belong to the base64
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@ -468,27 +476,29 @@ otherwise identical operations, and indicates the base64 conformance
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group unless otherwise specified.
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group unless otherwise specified.
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The 'code' field encodes the operation as below:
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The 'code' field encodes the operation as below:
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======== ===== ======= ================================= ===================================================
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.. table:: Jump instructions
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code value src_reg description notes
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======== ===== ======= ================================= ===================================================
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======== ===== ======= ================================= ===================================================
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JA 0x0 0x0 PC += offset {JA, K, JMP} only
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code value src_reg description notes
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JA 0x0 0x0 PC += imm {JA, K, JMP32} only
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======== ===== ======= ================================= ===================================================
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JEQ 0x1 any PC += offset if dst == src
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JA 0x0 0x0 PC += offset {JA, K, JMP} only
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JGT 0x2 any PC += offset if dst > src unsigned
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JA 0x0 0x0 PC += imm {JA, K, JMP32} only
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JGE 0x3 any PC += offset if dst >= src unsigned
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JEQ 0x1 any PC += offset if dst == src
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JSET 0x4 any PC += offset if dst & src
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JGT 0x2 any PC += offset if dst > src unsigned
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JNE 0x5 any PC += offset if dst != src
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JGE 0x3 any PC += offset if dst >= src unsigned
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JSGT 0x6 any PC += offset if dst > src signed
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JSET 0x4 any PC += offset if dst & src
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JSGE 0x7 any PC += offset if dst >= src signed
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JNE 0x5 any PC += offset if dst != src
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CALL 0x8 0x0 call helper function by static ID {CALL, K, JMP} only, see `Helper functions`_
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JSGT 0x6 any PC += offset if dst > src signed
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CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_
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JSGE 0x7 any PC += offset if dst >= src signed
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CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_
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CALL 0x8 0x0 call helper function by static ID {CALL, K, JMP} only, see `Helper functions`_
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EXIT 0x9 0x0 return {CALL, K, JMP} only
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CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_
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JLT 0xa any PC += offset if dst < src unsigned
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CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_
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JLE 0xb any PC += offset if dst <= src unsigned
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EXIT 0x9 0x0 return {CALL, K, JMP} only
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JSLT 0xc any PC += offset if dst < src signed
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JLT 0xa any PC += offset if dst < src unsigned
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JSLE 0xd any PC += offset if dst <= src signed
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JLE 0xb any PC += offset if dst <= src unsigned
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======== ===== ======= ================================= ===================================================
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JSLT 0xc any PC += offset if dst < src signed
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JSLE 0xd any PC += offset if dst <= src signed
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======== ===== ======= ================================= ===================================================
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where 'PC' denotes the program counter, and the offset to increment by
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where 'PC' denotes the program counter, and the offset to increment by
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is in units of 64-bit instructions relative to the instruction following
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is in units of 64-bit instructions relative to the instruction following
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@ -559,6 +569,8 @@ For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the
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**mode**
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**mode**
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The mode modifier is one of:
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The mode modifier is one of:
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.. table:: Mode modifier
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============= ===== ==================================== =============
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============= ===== ==================================== =============
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mode modifier value description reference
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mode modifier value description reference
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============= ===== ==================================== =============
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============= ===== ==================================== =============
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@ -573,6 +585,8 @@ For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the
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**sz (size)**
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**sz (size)**
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The size modifier is one of:
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The size modifier is one of:
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.. table:: Size modifier
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==== ===== =====================
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==== ===== =====================
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size value description
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size value description
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==== ===== =====================
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==== ===== =====================
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@ -641,14 +655,16 @@ The 'imm' field is used to encode the actual atomic operation.
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Simple atomic operation use a subset of the values defined to encode
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Simple atomic operation use a subset of the values defined to encode
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arithmetic operations in the 'imm' field to encode the atomic operation:
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arithmetic operations in the 'imm' field to encode the atomic operation:
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======== ===== ===========
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.. table:: Simple atomic operations
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imm value description
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======== ===== ===========
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======== ===== ===========
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ADD 0x00 atomic add
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imm value description
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OR 0x40 atomic or
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======== ===== ===========
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AND 0x50 atomic and
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ADD 0x00 atomic add
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XOR 0xa0 atomic xor
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OR 0x40 atomic or
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======== ===== ===========
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AND 0x50 atomic and
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XOR 0xa0 atomic xor
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======== ===== ===========
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``{ATOMIC, W, STX}`` with 'imm' = ADD means::
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``{ATOMIC, W, STX}`` with 'imm' = ADD means::
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@ -662,6 +678,8 @@ XOR 0xa0 atomic xor
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In addition to the simple atomic operations, there also is a modifier and
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In addition to the simple atomic operations, there also is a modifier and
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two complex atomic operations:
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two complex atomic operations:
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.. table:: Complex atomic operations
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=========== ================ ===========================
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=========== ================ ===========================
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imm value description
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imm value description
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=========== ================ ===========================
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=========== ================ ===========================
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@ -695,17 +713,19 @@ The following table defines a set of ``{IMM, DW, LD}`` instructions
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with opcode subtypes in the 'src_reg' field, using new terms such as "map"
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with opcode subtypes in the 'src_reg' field, using new terms such as "map"
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defined further below:
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defined further below:
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======= ========================================= =========== ==============
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.. table:: 64-bit immediate instructions
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src_reg pseudocode imm type dst type
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======= ========================================= =========== ==============
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======= ========================================= =========== ==============
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0x0 dst = (next_imm << 32) | imm integer integer
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src_reg pseudocode imm type dst type
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0x1 dst = map_by_fd(imm) map fd map
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======= ========================================= =========== ==============
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0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data address
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0x0 dst = (next_imm << 32) | imm integer integer
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0x3 dst = var_addr(imm) variable id data address
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0x1 dst = map_by_fd(imm) map fd map
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0x4 dst = code_addr(imm) integer code address
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0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data address
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0x5 dst = map_by_idx(imm) map index map
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0x3 dst = var_addr(imm) variable id data address
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0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data address
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0x4 dst = code_addr(imm) integer code address
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======= ========================================= =========== ==============
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0x5 dst = map_by_idx(imm) map index map
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0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data address
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======= ========================================= =========== ==============
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where
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where
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