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MIPS: Sanitise Cavium switch cases in TLB handler synthesizers

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It makes no sense to fall through to `break'.  Therefore reorder the
switch statements so as to have the Cavium cases first, followed by the
default case, which improves readability and pacifies code analysis
tools.  No change in semantics, assembly produced is exactly the same.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Fixes: bc431d2153cc ("MIPS: Fix fall-through warnings for Clang")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Maciej W. Rozycki 2022-03-04 21:13:11 +00:00 committed by Thomas Bogendoerfer
parent 244eae91a9
commit 6ddcba9d48
1 changed files with 10 additions and 13 deletions
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23
arch/mips/mm/tlbex.c
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@ -2159,16 +2159,14 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
default:
if (cpu_has_mips_r2_exec_hazard) {
uasm_i_ehb(&p);
fallthrough;
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
}
break;
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
/* Examine entrylo 0 or 1 based on ptr. */
@ -2235,15 +2233,14 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
default:
if (cpu_has_mips_r2_exec_hazard) {
uasm_i_ehb(&p);
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
}
break;
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
/* Examine entrylo 0 or 1 based on ptr. */