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clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9

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There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.

Signed-off-by: Terry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Terry Zhou 2020-11-06 11:00:39 +01:00 committed by Stephen Boyd
parent 3650b228f8
commit 6f37689cf6
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/mvebu/armada-37xx-xtal.c
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@ -13,8 +13,8 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define NB_GPIO1_LATCH 0xC
#define XTAL_MODE BIT(31)
#define NB_GPIO1_LATCH 0x8
#define XTAL_MODE BIT(9)
static int armada_3700_xtal_clock_probe(struct platform_device *pdev)
{