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octeontx2-af: RPM: fix stale FCFEC counters
The corrected words register(FCFECX_VL0_CCW_LO)/Uncorrected words
register (FCFECX_VL0_NCCW_LO) of FCFEC counter has different LMAC
offset which needs to be accessed differently.
Fixes: 84ad364211
("octeontx2-af: Add FEC stats for RPM/RPM_USX block")
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
parent
07cd1eb166
commit
6fc2164108
@ -704,27 +704,27 @@ int rpm_get_fec_stats(void *rpmd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
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*/
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mutex_lock(&rpm->lock);
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if (rpm->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
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val_lo = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_VL0_CCW_LO);
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val_hi = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_CW_HI);
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val_lo = rpm_read(rpm, 0, RPMX_MTI_FCFECX_VL0_CCW_LO(lmac_id));
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val_hi = rpm_read(rpm, 0, RPMX_MTI_FCFECX_CW_HI(lmac_id));
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rsp->fec_corr_blks = (val_hi << 16 | val_lo);
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val_lo = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_VL0_NCCW_LO);
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val_hi = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_CW_HI);
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val_lo = rpm_read(rpm, 0, RPMX_MTI_FCFECX_VL0_NCCW_LO(lmac_id));
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val_hi = rpm_read(rpm, 0, RPMX_MTI_FCFECX_CW_HI(lmac_id));
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rsp->fec_uncorr_blks = (val_hi << 16 | val_lo);
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/* 50G uses 2 Physical serdes lines */
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if (rpm->lmac_idmap[lmac_id]->link_info.lmac_type_id ==
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LMAC_MODE_50G_R) {
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val_lo = rpm_read(rpm, lmac_id,
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RPMX_MTI_FCFECX_VL1_CCW_LO);
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val_hi = rpm_read(rpm, lmac_id,
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RPMX_MTI_FCFECX_CW_HI);
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val_lo = rpm_read(rpm, 0,
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RPMX_MTI_FCFECX_VL1_CCW_LO(lmac_id));
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val_hi = rpm_read(rpm, 0,
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RPMX_MTI_FCFECX_CW_HI(lmac_id));
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rsp->fec_corr_blks += (val_hi << 16 | val_lo);
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val_lo = rpm_read(rpm, lmac_id,
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RPMX_MTI_FCFECX_VL1_NCCW_LO);
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val_hi = rpm_read(rpm, lmac_id,
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RPMX_MTI_FCFECX_CW_HI);
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val_lo = rpm_read(rpm, 0,
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RPMX_MTI_FCFECX_VL1_NCCW_LO(lmac_id));
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val_hi = rpm_read(rpm, 0,
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RPMX_MTI_FCFECX_CW_HI(lmac_id));
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rsp->fec_uncorr_blks += (val_hi << 16 | val_lo);
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}
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} else {
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@ -91,11 +91,11 @@
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#define RPMX_MTI_RSFEC_STAT_FAST_DATA_HI_CDC 0x40000
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#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2 0x40050
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#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3 0x40058
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#define RPMX_MTI_FCFECX_VL0_CCW_LO 0x38618
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#define RPMX_MTI_FCFECX_VL0_NCCW_LO 0x38620
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#define RPMX_MTI_FCFECX_VL1_CCW_LO 0x38628
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#define RPMX_MTI_FCFECX_VL1_NCCW_LO 0x38630
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#define RPMX_MTI_FCFECX_CW_HI 0x38638
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#define RPMX_MTI_FCFECX_VL0_CCW_LO(a) (0x38618 + ((a) * 0x40))
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#define RPMX_MTI_FCFECX_VL0_NCCW_LO(a) (0x38620 + ((a) * 0x40))
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#define RPMX_MTI_FCFECX_VL1_CCW_LO(a) (0x38628 + ((a) * 0x40))
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#define RPMX_MTI_FCFECX_VL1_NCCW_LO(a) (0x38630 + ((a) * 0x40))
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#define RPMX_MTI_FCFECX_CW_HI(a) (0x38638 + ((a) * 0x40))
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/* CN10KB CSR Declaration */
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#define RPM2_CMRX_SW_INT 0x1b0
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