mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-12-29 09:16:33 +00:00
Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue
Tony Nguyen says: ==================== Intel Wired LAN Driver Updates 2023-02-09 (i40e) Jan removes i40e_status from the driver; replacing them with standard kernel error codes. Kees Cook replaces 0-length array with flexible array. * '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue: net/i40e: Replace 0-length array with flexible array i40e: use ERR_PTR error print in i40e messages i40e: use int for i40e_status i40e: Remove string printing for i40e_status i40e: Remove unused i40e status codes ==================== Link: https://lore.kernel.org/r/20230209172536.3595838-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
commit
75da437a2f
@ -177,7 +177,7 @@ enum i40e_interrupt_policy {
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struct i40e_lump_tracking {
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u16 num_entries;
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u16 list[0];
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u16 list[];
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#define I40E_PILE_VALID_BIT 0x8000
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#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
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};
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@ -1288,9 +1288,9 @@ void i40e_ptp_stop(struct i40e_pf *pf);
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int i40e_ptp_alloc_pins(struct i40e_pf *pf);
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int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
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int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
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i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
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i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
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i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
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int i40e_get_partition_bw_setting(struct i40e_pf *pf);
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int i40e_set_partition_bw_setting(struct i40e_pf *pf);
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int i40e_commit_partition_bw_setting(struct i40e_pf *pf);
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void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
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void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
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@ -47,9 +47,9 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
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* i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
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* @hw: pointer to the hardware structure
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**/
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static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
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static int i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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int ret_code;
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ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
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i40e_mem_atq_ring,
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@ -74,9 +74,9 @@ static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
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* i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
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* @hw: pointer to the hardware structure
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**/
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static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
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static int i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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int ret_code;
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ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
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i40e_mem_arq_ring,
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@ -115,11 +115,11 @@ static void i40e_free_adminq_arq(struct i40e_hw *hw)
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* i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
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* @hw: pointer to the hardware structure
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**/
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static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
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static int i40e_alloc_arq_bufs(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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struct i40e_aq_desc *desc;
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struct i40e_dma_mem *bi;
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int ret_code;
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int i;
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/* We'll be allocating the buffer info memory first, then we can
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@ -182,10 +182,10 @@ static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
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* i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
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* @hw: pointer to the hardware structure
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**/
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static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
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static int i40e_alloc_asq_bufs(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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struct i40e_dma_mem *bi;
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int ret_code;
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int i;
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/* No mapped memory needed yet, just the buffer info structures */
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@ -266,9 +266,9 @@ static void i40e_free_asq_bufs(struct i40e_hw *hw)
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*
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* Configure base address and length registers for the transmit queue
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**/
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static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
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static int i40e_config_asq_regs(struct i40e_hw *hw)
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{
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i40e_status ret_code = 0;
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int ret_code = 0;
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u32 reg = 0;
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/* Clear Head and Tail */
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@ -295,9 +295,9 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
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*
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* Configure base address and length registers for the receive (event queue)
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**/
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static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
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static int i40e_config_arq_regs(struct i40e_hw *hw)
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{
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i40e_status ret_code = 0;
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int ret_code = 0;
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u32 reg = 0;
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/* Clear Head and Tail */
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@ -334,9 +334,9 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
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* Do *NOT* hold the lock when calling this as the memory allocation routines
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* called are not going to be atomic context safe
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**/
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static i40e_status i40e_init_asq(struct i40e_hw *hw)
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static int i40e_init_asq(struct i40e_hw *hw)
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{
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i40e_status ret_code = 0;
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int ret_code = 0;
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if (hw->aq.asq.count > 0) {
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/* queue already initialized */
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@ -393,9 +393,9 @@ static i40e_status i40e_init_asq(struct i40e_hw *hw)
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* Do *NOT* hold the lock when calling this as the memory allocation routines
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* called are not going to be atomic context safe
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**/
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static i40e_status i40e_init_arq(struct i40e_hw *hw)
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static int i40e_init_arq(struct i40e_hw *hw)
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{
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i40e_status ret_code = 0;
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int ret_code = 0;
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if (hw->aq.arq.count > 0) {
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/* queue already initialized */
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@ -445,9 +445,9 @@ static i40e_status i40e_init_arq(struct i40e_hw *hw)
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*
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* The main shutdown routine for the Admin Send Queue
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**/
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static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
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static int i40e_shutdown_asq(struct i40e_hw *hw)
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{
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i40e_status ret_code = 0;
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int ret_code = 0;
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mutex_lock(&hw->aq.asq_mutex);
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@ -479,9 +479,9 @@ static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
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*
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* The main shutdown routine for the Admin Receive Queue
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**/
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static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
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static int i40e_shutdown_arq(struct i40e_hw *hw)
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{
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i40e_status ret_code = 0;
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int ret_code = 0;
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mutex_lock(&hw->aq.arq_mutex);
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@ -582,12 +582,12 @@ static void i40e_set_hw_flags(struct i40e_hw *hw)
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* - hw->aq.arq_buf_size
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* - hw->aq.asq_buf_size
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**/
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i40e_status i40e_init_adminq(struct i40e_hw *hw)
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int i40e_init_adminq(struct i40e_hw *hw)
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{
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u16 cfg_ptr, oem_hi, oem_lo;
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u16 eetrack_lo, eetrack_hi;
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i40e_status ret_code;
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int retry = 0;
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int ret_code;
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/* verify input for valid configuration */
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if ((hw->aq.num_arq_entries == 0) ||
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@ -780,7 +780,7 @@ static bool i40e_asq_done(struct i40e_hw *hw)
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* This is the main send command driver routine for the Admin Queue send
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* queue. It runs the queue, cleans the queue, etc
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**/
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static i40e_status
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static int
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i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
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struct i40e_aq_desc *desc,
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void *buff, /* can be NULL */
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@ -788,12 +788,12 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
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struct i40e_asq_cmd_details *cmd_details,
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bool is_atomic_context)
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{
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i40e_status status = 0;
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struct i40e_dma_mem *dma_buff = NULL;
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struct i40e_asq_cmd_details *details;
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struct i40e_aq_desc *desc_on_ring;
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bool cmd_completed = false;
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u16 retval = 0;
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int status = 0;
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u32 val = 0;
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if (hw->aq.asq.count == 0) {
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@ -984,7 +984,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,
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* Acquires the lock and calls the main send command execution
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* routine.
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**/
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i40e_status
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int
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i40e_asq_send_command_atomic(struct i40e_hw *hw,
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struct i40e_aq_desc *desc,
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void *buff, /* can be NULL */
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@ -992,7 +992,7 @@ i40e_asq_send_command_atomic(struct i40e_hw *hw,
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struct i40e_asq_cmd_details *cmd_details,
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bool is_atomic_context)
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{
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i40e_status status;
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int status;
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mutex_lock(&hw->aq.asq_mutex);
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status = i40e_asq_send_command_atomic_exec(hw, desc, buff, buff_size,
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@ -1003,7 +1003,7 @@ i40e_asq_send_command_atomic(struct i40e_hw *hw,
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return status;
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}
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i40e_status
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int
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i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,
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void *buff, /* can be NULL */ u16 buff_size,
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struct i40e_asq_cmd_details *cmd_details)
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@ -1026,7 +1026,7 @@ i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,
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* routine. Returns the last Admin Queue status in aq_status
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* to avoid race conditions in access to hw->aq.asq_last_status.
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**/
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i40e_status
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int
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i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,
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struct i40e_aq_desc *desc,
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void *buff, /* can be NULL */
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@ -1035,7 +1035,7 @@ i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,
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bool is_atomic_context,
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enum i40e_admin_queue_err *aq_status)
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{
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i40e_status status;
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int status;
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mutex_lock(&hw->aq.asq_mutex);
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status = i40e_asq_send_command_atomic_exec(hw, desc, buff,
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@ -1048,7 +1048,7 @@ i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,
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return status;
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}
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i40e_status
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int
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i40e_asq_send_command_v2(struct i40e_hw *hw, struct i40e_aq_desc *desc,
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void *buff, /* can be NULL */ u16 buff_size,
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struct i40e_asq_cmd_details *cmd_details,
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@ -1084,14 +1084,14 @@ void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
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* the contents through e. It can also return how many events are
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* left to process through 'pending'
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**/
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i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
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struct i40e_arq_event_info *e,
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u16 *pending)
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int i40e_clean_arq_element(struct i40e_hw *hw,
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struct i40e_arq_event_info *e,
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u16 *pending)
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{
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i40e_status ret_code = 0;
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u16 ntc = hw->aq.arq.next_to_clean;
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struct i40e_aq_desc *desc;
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struct i40e_dma_mem *bi;
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int ret_code = 0;
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u16 desc_idx;
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u16 datalen;
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u16 flags;
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@ -20,16 +20,16 @@ enum i40e_memory_type {
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};
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/* prototype for functions used for dynamic memory allocation */
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i40e_status i40e_allocate_dma_mem(struct i40e_hw *hw,
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struct i40e_dma_mem *mem,
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enum i40e_memory_type type,
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u64 size, u32 alignment);
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i40e_status i40e_free_dma_mem(struct i40e_hw *hw,
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struct i40e_dma_mem *mem);
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i40e_status i40e_allocate_virt_mem(struct i40e_hw *hw,
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struct i40e_virt_mem *mem,
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u32 size);
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i40e_status i40e_free_virt_mem(struct i40e_hw *hw,
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struct i40e_virt_mem *mem);
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int i40e_allocate_dma_mem(struct i40e_hw *hw,
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struct i40e_dma_mem *mem,
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enum i40e_memory_type type,
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u64 size, u32 alignment);
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int i40e_free_dma_mem(struct i40e_hw *hw,
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struct i40e_dma_mem *mem);
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int i40e_allocate_virt_mem(struct i40e_hw *hw,
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struct i40e_virt_mem *mem,
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u32 size);
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int i40e_free_virt_mem(struct i40e_hw *hw,
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struct i40e_virt_mem *mem);
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#endif /* _I40E_ALLOC_H_ */
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|
@ -541,7 +541,7 @@ static int i40e_client_virtchnl_send(struct i40e_info *ldev,
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{
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struct i40e_pf *pf = ldev->pf;
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struct i40e_hw *hw = &pf->hw;
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i40e_status err;
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int err;
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|
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err = i40e_aq_send_msg_to_vf(hw, vf_id, VIRTCHNL_OP_RDMA,
|
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0, msg, len, NULL);
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@ -674,7 +674,7 @@ static int i40e_client_update_vsi_ctxt(struct i40e_info *ldev,
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struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
|
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struct i40e_vsi_context ctxt;
|
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bool update = true;
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i40e_status err;
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int err;
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|
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/* TODO: for now do not allow setting VF's VSI setting */
|
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if (is_vf)
|
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@ -686,8 +686,8 @@ static int i40e_client_update_vsi_ctxt(struct i40e_info *ldev,
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ctxt.flags = I40E_AQ_VSI_TYPE_PF;
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if (err) {
|
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dev_info(&pf->pdev->dev,
|
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"couldn't get PF vsi config, err %s aq_err %s\n",
|
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i40e_stat_str(&pf->hw, err),
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"couldn't get PF vsi config, err %pe aq_err %s\n",
|
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ERR_PTR(err),
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i40e_aq_str(&pf->hw,
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pf->hw.aq.asq_last_status));
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return -ENOENT;
|
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@ -714,8 +714,8 @@ static int i40e_client_update_vsi_ctxt(struct i40e_info *ldev,
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err = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
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if (err) {
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dev_info(&pf->pdev->dev,
|
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"update VSI ctxt for PE failed, err %s aq_err %s\n",
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i40e_stat_str(&pf->hw, err),
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"update VSI ctxt for PE failed, err %pe aq_err %s\n",
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ERR_PTR(err),
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i40e_aq_str(&pf->hw,
|
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pf->hw.aq.asq_last_status));
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}
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -12,7 +12,7 @@
|
||||
*
|
||||
* Get the DCBX status from the Firmware
|
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**/
|
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i40e_status i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status)
|
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int i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status)
|
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{
|
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u32 reg;
|
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|
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@ -497,15 +497,15 @@ static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,
|
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*
|
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* Parse DCB configuration from the LLDPDU
|
||||
**/
|
||||
i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
|
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struct i40e_dcbx_config *dcbcfg)
|
||||
int i40e_lldp_to_dcb_config(u8 *lldpmib,
|
||||
struct i40e_dcbx_config *dcbcfg)
|
||||
{
|
||||
i40e_status ret = 0;
|
||||
struct i40e_lldp_org_tlv *tlv;
|
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u16 type;
|
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u16 length;
|
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u16 typelength;
|
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u16 offset = 0;
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||||
int ret = 0;
|
||||
u16 length;
|
||||
u16 type;
|
||||
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if (!lldpmib || !dcbcfg)
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return I40E_ERR_PARAM;
|
||||
@ -551,12 +551,12 @@ i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
|
||||
*
|
||||
* Query DCB configuration from the Firmware
|
||||
**/
|
||||
i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
|
||||
u8 bridgetype,
|
||||
struct i40e_dcbx_config *dcbcfg)
|
||||
int i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
|
||||
u8 bridgetype,
|
||||
struct i40e_dcbx_config *dcbcfg)
|
||||
{
|
||||
i40e_status ret = 0;
|
||||
struct i40e_virt_mem mem;
|
||||
int ret = 0;
|
||||
u8 *lldpmib;
|
||||
|
||||
/* Allocate the LLDPDU */
|
||||
@ -767,9 +767,9 @@ static void i40e_cee_to_dcb_config(
|
||||
*
|
||||
* Get IEEE mode DCB configuration from the Firmware
|
||||
**/
|
||||
static i40e_status i40e_get_ieee_dcb_config(struct i40e_hw *hw)
|
||||
static int i40e_get_ieee_dcb_config(struct i40e_hw *hw)
|
||||
{
|
||||
i40e_status ret = 0;
|
||||
int ret = 0;
|
||||
|
||||
/* IEEE mode */
|
||||
hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
|
||||
@ -797,11 +797,11 @@ static i40e_status i40e_get_ieee_dcb_config(struct i40e_hw *hw)
|
||||
*
|
||||
* Get DCB configuration from the Firmware
|
||||
**/
|
||||
i40e_status i40e_get_dcb_config(struct i40e_hw *hw)
|
||||
int i40e_get_dcb_config(struct i40e_hw *hw)
|
||||
{
|
||||
i40e_status ret = 0;
|
||||
struct i40e_aqc_get_cee_dcb_cfg_resp cee_cfg;
|
||||
struct i40e_aqc_get_cee_dcb_cfg_v1_resp cee_v1_cfg;
|
||||
struct i40e_aqc_get_cee_dcb_cfg_resp cee_cfg;
|
||||
int ret = 0;
|
||||
|
||||
/* If Firmware version < v4.33 on X710/XL710, IEEE only */
|
||||
if ((hw->mac.type == I40E_MAC_XL710) &&
|
||||
@ -867,11 +867,11 @@ i40e_status i40e_get_dcb_config(struct i40e_hw *hw)
|
||||
*
|
||||
* Update DCB configuration from the Firmware
|
||||
**/
|
||||
i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change)
|
||||
int i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change)
|
||||
{
|
||||
i40e_status ret = 0;
|
||||
struct i40e_lldp_variables lldp_cfg;
|
||||
u8 adminstatus = 0;
|
||||
int ret = 0;
|
||||
|
||||
if (!hw->func_caps.dcb)
|
||||
return I40E_NOT_SUPPORTED;
|
||||
@ -940,13 +940,13 @@ i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change)
|
||||
* Get status of FW Link Layer Discovery Protocol (LLDP) Agent.
|
||||
* Status of agent is reported via @lldp_status parameter.
|
||||
**/
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_get_fw_lldp_status(struct i40e_hw *hw,
|
||||
enum i40e_get_fw_lldp_status_resp *lldp_status)
|
||||
{
|
||||
struct i40e_virt_mem mem;
|
||||
i40e_status ret;
|
||||
u8 *lldpmib;
|
||||
int ret;
|
||||
|
||||
if (!lldp_status)
|
||||
return I40E_ERR_PARAM;
|
||||
@ -1238,13 +1238,13 @@ static void i40e_add_dcb_tlv(struct i40e_lldp_org_tlv *tlv,
|
||||
*
|
||||
* Set DCB configuration to the Firmware
|
||||
**/
|
||||
i40e_status i40e_set_dcb_config(struct i40e_hw *hw)
|
||||
int i40e_set_dcb_config(struct i40e_hw *hw)
|
||||
{
|
||||
struct i40e_dcbx_config *dcbcfg;
|
||||
struct i40e_virt_mem mem;
|
||||
u8 mib_type, *lldpmib;
|
||||
i40e_status ret;
|
||||
u16 miblen;
|
||||
int ret;
|
||||
|
||||
/* update the hw local config */
|
||||
dcbcfg = &hw->local_dcbx_config;
|
||||
@ -1274,8 +1274,8 @@ i40e_status i40e_set_dcb_config(struct i40e_hw *hw)
|
||||
*
|
||||
* send DCB configuration to FW
|
||||
**/
|
||||
i40e_status i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
|
||||
struct i40e_dcbx_config *dcbcfg)
|
||||
int i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
|
||||
struct i40e_dcbx_config *dcbcfg)
|
||||
{
|
||||
u16 length, offset = 0, tlvid, typelength;
|
||||
struct i40e_lldp_org_tlv *tlv;
|
||||
@ -1888,13 +1888,13 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,
|
||||
*
|
||||
* Reads the LLDP configuration data from NVM using passed addresses
|
||||
**/
|
||||
static i40e_status _i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
struct i40e_lldp_variables *lldp_cfg,
|
||||
u8 module, u32 word_offset)
|
||||
static int _i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
struct i40e_lldp_variables *lldp_cfg,
|
||||
u8 module, u32 word_offset)
|
||||
{
|
||||
u32 address, offset = (2 * word_offset);
|
||||
i40e_status ret;
|
||||
__le16 raw_mem;
|
||||
int ret;
|
||||
u16 mem;
|
||||
|
||||
ret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
|
||||
@ -1950,10 +1950,10 @@ static i40e_status _i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
*
|
||||
* Reads the LLDP configuration data from NVM
|
||||
**/
|
||||
i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
struct i40e_lldp_variables *lldp_cfg)
|
||||
int i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
struct i40e_lldp_variables *lldp_cfg)
|
||||
{
|
||||
i40e_status ret = 0;
|
||||
int ret = 0;
|
||||
u32 mem;
|
||||
|
||||
if (!lldp_cfg)
|
||||
|
@ -264,20 +264,20 @@ void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,
|
||||
void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,
|
||||
struct i40e_rx_pb_config *old_pb_cfg,
|
||||
struct i40e_rx_pb_config *new_pb_cfg);
|
||||
i40e_status i40e_get_dcbx_status(struct i40e_hw *hw,
|
||||
u16 *status);
|
||||
i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
|
||||
u8 bridgetype,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
i40e_status i40e_get_dcb_config(struct i40e_hw *hw);
|
||||
i40e_status i40e_init_dcb(struct i40e_hw *hw,
|
||||
bool enable_mib_change);
|
||||
enum i40e_status_code
|
||||
int i40e_get_dcbx_status(struct i40e_hw *hw,
|
||||
u16 *status);
|
||||
int i40e_lldp_to_dcb_config(u8 *lldpmib,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
int i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
|
||||
u8 bridgetype,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
int i40e_get_dcb_config(struct i40e_hw *hw);
|
||||
int i40e_init_dcb(struct i40e_hw *hw,
|
||||
bool enable_mib_change);
|
||||
int
|
||||
i40e_get_fw_lldp_status(struct i40e_hw *hw,
|
||||
enum i40e_get_fw_lldp_status_resp *lldp_status);
|
||||
i40e_status i40e_set_dcb_config(struct i40e_hw *hw);
|
||||
i40e_status i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
int i40e_set_dcb_config(struct i40e_hw *hw);
|
||||
int i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
#endif /* _I40E_DCB_H_ */
|
||||
|
@ -135,8 +135,8 @@ static int i40e_dcbnl_ieee_setets(struct net_device *netdev,
|
||||
ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg);
|
||||
if (ret) {
|
||||
dev_info(&pf->pdev->dev,
|
||||
"Failed setting DCB ETS configuration err %s aq_err %s\n",
|
||||
i40e_stat_str(&pf->hw, ret),
|
||||
"Failed setting DCB ETS configuration err %pe aq_err %s\n",
|
||||
ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -174,8 +174,8 @@ static int i40e_dcbnl_ieee_setpfc(struct net_device *netdev,
|
||||
ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg);
|
||||
if (ret) {
|
||||
dev_info(&pf->pdev->dev,
|
||||
"Failed setting DCB PFC configuration err %s aq_err %s\n",
|
||||
i40e_stat_str(&pf->hw, ret),
|
||||
"Failed setting DCB PFC configuration err %pe aq_err %s\n",
|
||||
ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -225,8 +225,8 @@ static int i40e_dcbnl_ieee_setapp(struct net_device *netdev,
|
||||
ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg);
|
||||
if (ret) {
|
||||
dev_info(&pf->pdev->dev,
|
||||
"Failed setting DCB configuration err %s aq_err %s\n",
|
||||
i40e_stat_str(&pf->hw, ret),
|
||||
"Failed setting DCB configuration err %pe aq_err %s\n",
|
||||
ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -290,8 +290,8 @@ static int i40e_dcbnl_ieee_delapp(struct net_device *netdev,
|
||||
ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg);
|
||||
if (ret) {
|
||||
dev_info(&pf->pdev->dev,
|
||||
"Failed setting DCB configuration err %s aq_err %s\n",
|
||||
i40e_stat_str(&pf->hw, ret),
|
||||
"Failed setting DCB configuration err %pe aq_err %s\n",
|
||||
ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
@ -36,7 +36,7 @@ static int i40e_ddp_does_profile_exist(struct i40e_hw *hw,
|
||||
{
|
||||
struct i40e_ddp_profile_list *profile_list;
|
||||
u8 buff[I40E_PROFILE_LIST_SIZE];
|
||||
i40e_status status;
|
||||
int status;
|
||||
int i;
|
||||
|
||||
status = i40e_aq_get_ddp_list(hw, buff, I40E_PROFILE_LIST_SIZE, 0,
|
||||
@ -91,7 +91,7 @@ static int i40e_ddp_does_profile_overlap(struct i40e_hw *hw,
|
||||
{
|
||||
struct i40e_ddp_profile_list *profile_list;
|
||||
u8 buff[I40E_PROFILE_LIST_SIZE];
|
||||
i40e_status status;
|
||||
int status;
|
||||
int i;
|
||||
|
||||
status = i40e_aq_get_ddp_list(hw, buff, I40E_PROFILE_LIST_SIZE, 0,
|
||||
@ -117,14 +117,14 @@ static int i40e_ddp_does_profile_overlap(struct i40e_hw *hw,
|
||||
*
|
||||
* Register a profile to the list of loaded profiles.
|
||||
*/
|
||||
static enum i40e_status_code
|
||||
static int
|
||||
i40e_add_pinfo(struct i40e_hw *hw, struct i40e_profile_segment *profile,
|
||||
u8 *profile_info_sec, u32 track_id)
|
||||
{
|
||||
struct i40e_profile_section_header *sec;
|
||||
struct i40e_profile_info *pinfo;
|
||||
i40e_status status;
|
||||
u32 offset = 0, info = 0;
|
||||
int status;
|
||||
|
||||
sec = (struct i40e_profile_section_header *)profile_info_sec;
|
||||
sec->tbl_size = 1;
|
||||
@ -157,14 +157,14 @@ i40e_add_pinfo(struct i40e_hw *hw, struct i40e_profile_segment *profile,
|
||||
*
|
||||
* Removes DDP profile from the NIC.
|
||||
**/
|
||||
static enum i40e_status_code
|
||||
static int
|
||||
i40e_del_pinfo(struct i40e_hw *hw, struct i40e_profile_segment *profile,
|
||||
u8 *profile_info_sec, u32 track_id)
|
||||
{
|
||||
struct i40e_profile_section_header *sec;
|
||||
struct i40e_profile_info *pinfo;
|
||||
i40e_status status;
|
||||
u32 offset = 0, info = 0;
|
||||
int status;
|
||||
|
||||
sec = (struct i40e_profile_section_header *)profile_info_sec;
|
||||
sec->tbl_size = 1;
|
||||
@ -270,12 +270,12 @@ int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
|
||||
struct i40e_profile_segment *profile_hdr;
|
||||
struct i40e_profile_info pinfo;
|
||||
struct i40e_package_header *pkg_hdr;
|
||||
i40e_status status;
|
||||
struct i40e_netdev_priv *np = netdev_priv(netdev);
|
||||
struct i40e_vsi *vsi = np->vsi;
|
||||
struct i40e_pf *pf = vsi->back;
|
||||
u32 track_id;
|
||||
int istatus;
|
||||
int status;
|
||||
|
||||
pkg_hdr = (struct i40e_package_header *)data;
|
||||
if (!i40e_ddp_is_pkg_hdr_valid(netdev, pkg_hdr, size))
|
||||
|
@ -918,9 +918,9 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
|
||||
dev_info(&pf->pdev->dev, "deleting relay %d\n", veb_seid);
|
||||
i40e_veb_release(pf->veb[i]);
|
||||
} else if (strncmp(cmd_buf, "add pvid", 8) == 0) {
|
||||
i40e_status ret;
|
||||
u16 vid;
|
||||
unsigned int v;
|
||||
int ret;
|
||||
u16 vid;
|
||||
|
||||
cnt = sscanf(&cmd_buf[8], "%i %u", &vsi_seid, &v);
|
||||
if (cnt != 2) {
|
||||
@ -1284,7 +1284,7 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
|
||||
}
|
||||
} else if (strncmp(cmd_buf, "send aq_cmd", 11) == 0) {
|
||||
struct i40e_aq_desc *desc;
|
||||
i40e_status ret;
|
||||
int ret;
|
||||
|
||||
desc = kzalloc(sizeof(struct i40e_aq_desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
@ -1330,9 +1330,9 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
|
||||
desc = NULL;
|
||||
} else if (strncmp(cmd_buf, "send indirect aq_cmd", 20) == 0) {
|
||||
struct i40e_aq_desc *desc;
|
||||
i40e_status ret;
|
||||
u16 buffer_len;
|
||||
u8 *buff;
|
||||
int ret;
|
||||
|
||||
desc = kzalloc(sizeof(struct i40e_aq_desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
|
@ -10,8 +10,8 @@
|
||||
* @reg: reg to be tested
|
||||
* @mask: bits to be touched
|
||||
**/
|
||||
static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
|
||||
u32 reg, u32 mask)
|
||||
static int i40e_diag_reg_pattern_test(struct i40e_hw *hw,
|
||||
u32 reg, u32 mask)
|
||||
{
|
||||
static const u32 patterns[] = {
|
||||
0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
|
||||
@ -74,9 +74,9 @@ struct i40e_diag_reg_test_info i40e_reg_list[] = {
|
||||
*
|
||||
* Perform registers diagnostic test
|
||||
**/
|
||||
i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
|
||||
int i40e_diag_reg_test(struct i40e_hw *hw)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
u32 reg, mask;
|
||||
u32 i, j;
|
||||
|
||||
@ -114,9 +114,9 @@ i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
|
||||
*
|
||||
* Perform EEPROM diagnostic test
|
||||
**/
|
||||
i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)
|
||||
int i40e_diag_eeprom_test(struct i40e_hw *hw)
|
||||
{
|
||||
i40e_status ret_code;
|
||||
int ret_code;
|
||||
u16 reg_val;
|
||||
|
||||
/* read NVM control word and if NVM valid, validate EEPROM checksum*/
|
||||
|
@ -22,7 +22,7 @@ struct i40e_diag_reg_test_info {
|
||||
|
||||
extern struct i40e_diag_reg_test_info i40e_reg_list[];
|
||||
|
||||
i40e_status i40e_diag_reg_test(struct i40e_hw *hw);
|
||||
i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw);
|
||||
int i40e_diag_reg_test(struct i40e_hw *hw);
|
||||
int i40e_diag_eeprom_test(struct i40e_hw *hw);
|
||||
|
||||
#endif /* _I40E_DIAG_H_ */
|
||||
|
@ -1226,8 +1226,8 @@ static int i40e_set_link_ksettings(struct net_device *netdev,
|
||||
struct i40e_vsi *vsi = np->vsi;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
bool autoneg_changed = false;
|
||||
i40e_status status = 0;
|
||||
int timeout = 50;
|
||||
int status = 0;
|
||||
int err = 0;
|
||||
__u32 speed;
|
||||
u8 autoneg;
|
||||
@ -1455,8 +1455,8 @@ static int i40e_set_link_ksettings(struct net_device *netdev,
|
||||
status = i40e_aq_set_phy_config(hw, &config, NULL);
|
||||
if (status) {
|
||||
netdev_info(netdev,
|
||||
"Set phy config failed, err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
"Set phy config failed, err %pe aq_err %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
err = -EAGAIN;
|
||||
goto done;
|
||||
@ -1465,8 +1465,8 @@ static int i40e_set_link_ksettings(struct net_device *netdev,
|
||||
status = i40e_update_link_info(hw);
|
||||
if (status)
|
||||
netdev_dbg(netdev,
|
||||
"Updating link info failed with err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
"Updating link info failed with err %pe aq_err %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
|
||||
} else {
|
||||
@ -1485,7 +1485,7 @@ static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
|
||||
struct i40e_aq_get_phy_abilities_resp abilities;
|
||||
struct i40e_pf *pf = np->vsi->back;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
i40e_status status = 0;
|
||||
int status = 0;
|
||||
u32 flags = 0;
|
||||
int err = 0;
|
||||
|
||||
@ -1517,8 +1517,8 @@ static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
|
||||
status = i40e_aq_set_phy_config(hw, &config, NULL);
|
||||
if (status) {
|
||||
netdev_info(netdev,
|
||||
"Set phy config failed, err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
"Set phy config failed, err %pe aq_err %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
err = -EAGAIN;
|
||||
goto done;
|
||||
@ -1531,8 +1531,8 @@ static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
|
||||
* (e.g. no physical connection etc.)
|
||||
*/
|
||||
netdev_dbg(netdev,
|
||||
"Updating link info failed with err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
"Updating link info failed with err %pe aq_err %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
}
|
||||
|
||||
@ -1547,7 +1547,7 @@ static int i40e_get_fec_param(struct net_device *netdev,
|
||||
struct i40e_aq_get_phy_abilities_resp abilities;
|
||||
struct i40e_pf *pf = np->vsi->back;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
i40e_status status = 0;
|
||||
int status = 0;
|
||||
int err = 0;
|
||||
u8 fec_cfg;
|
||||
|
||||
@ -1634,12 +1634,12 @@ static int i40e_nway_reset(struct net_device *netdev)
|
||||
struct i40e_pf *pf = np->vsi->back;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
bool link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
|
||||
i40e_status ret = 0;
|
||||
int ret = 0;
|
||||
|
||||
ret = i40e_aq_set_link_restart_an(hw, link_up, NULL);
|
||||
if (ret) {
|
||||
netdev_info(netdev, "link restart failed, err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, ret),
|
||||
netdev_info(netdev, "link restart failed, err %pe aq_err %s\n",
|
||||
ERR_PTR(ret),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
return -EIO;
|
||||
}
|
||||
@ -1699,9 +1699,9 @@ static int i40e_set_pauseparam(struct net_device *netdev,
|
||||
struct i40e_link_status *hw_link_info = &hw->phy.link_info;
|
||||
struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
|
||||
bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
|
||||
i40e_status status;
|
||||
u8 aq_failures;
|
||||
int err = 0;
|
||||
int status;
|
||||
u32 is_an;
|
||||
|
||||
/* Changing the port's flow control is not supported if this isn't the
|
||||
@ -1755,20 +1755,20 @@ static int i40e_set_pauseparam(struct net_device *netdev,
|
||||
status = i40e_set_fc(hw, &aq_failures, link_up);
|
||||
|
||||
if (aq_failures & I40E_SET_FC_AQ_FAIL_GET) {
|
||||
netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %pe aq_err %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
err = -EAGAIN;
|
||||
}
|
||||
if (aq_failures & I40E_SET_FC_AQ_FAIL_SET) {
|
||||
netdev_info(netdev, "Set fc failed on the set_phy_config call with err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
netdev_info(netdev, "Set fc failed on the set_phy_config call with err %pe aq_err %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
err = -EAGAIN;
|
||||
}
|
||||
if (aq_failures & I40E_SET_FC_AQ_FAIL_UPDATE) {
|
||||
netdev_info(netdev, "Set fc failed on the get_link_info call with err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
netdev_info(netdev, "Set fc failed on the get_link_info call with err %pe aq_err %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
err = -EAGAIN;
|
||||
}
|
||||
@ -2583,8 +2583,8 @@ static u64 i40e_link_test(struct net_device *netdev, u64 *data)
|
||||
{
|
||||
struct i40e_netdev_priv *np = netdev_priv(netdev);
|
||||
struct i40e_pf *pf = np->vsi->back;
|
||||
i40e_status status;
|
||||
bool link_up = false;
|
||||
int status;
|
||||
|
||||
netif_info(pf, hw, netdev, "link test\n");
|
||||
status = i40e_get_link_status(&pf->hw, &link_up);
|
||||
@ -2807,11 +2807,11 @@ static int i40e_set_phys_id(struct net_device *netdev,
|
||||
enum ethtool_phys_id_state state)
|
||||
{
|
||||
struct i40e_netdev_priv *np = netdev_priv(netdev);
|
||||
i40e_status ret = 0;
|
||||
struct i40e_pf *pf = np->vsi->back;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
int blink_freq = 2;
|
||||
u16 temp_status;
|
||||
int ret = 0;
|
||||
|
||||
switch (state) {
|
||||
case ETHTOOL_ID_ACTIVE:
|
||||
@ -5247,7 +5247,7 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
|
||||
struct i40e_vsi *vsi = np->vsi;
|
||||
struct i40e_pf *pf = vsi->back;
|
||||
u32 reset_needed = 0;
|
||||
i40e_status status;
|
||||
int status;
|
||||
u32 i, j;
|
||||
|
||||
orig_flags = READ_ONCE(pf->flags);
|
||||
@ -5362,8 +5362,8 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
|
||||
0, NULL);
|
||||
if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
|
||||
dev_info(&pf->pdev->dev,
|
||||
"couldn't set switch config bits, err %s aq_err %s\n",
|
||||
i40e_stat_str(&pf->hw, ret),
|
||||
"couldn't set switch config bits, err %pe aq_err %s\n",
|
||||
ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw,
|
||||
pf->hw.aq.asq_last_status));
|
||||
/* not a fatal problem, just keep going */
|
||||
@ -5435,9 +5435,8 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
|
||||
return -EBUSY;
|
||||
default:
|
||||
dev_warn(&pf->pdev->dev,
|
||||
"Starting FW LLDP agent failed: error: %s, %s\n",
|
||||
i40e_stat_str(&pf->hw,
|
||||
status),
|
||||
"Starting FW LLDP agent failed: error: %pe, %s\n",
|
||||
ERR_PTR(status),
|
||||
i40e_aq_str(&pf->hw,
|
||||
adq_err));
|
||||
return -EINVAL;
|
||||
@ -5477,8 +5476,8 @@ static int i40e_get_module_info(struct net_device *netdev,
|
||||
u32 sff8472_comp = 0;
|
||||
u32 sff8472_swap = 0;
|
||||
u32 sff8636_rev = 0;
|
||||
i40e_status status;
|
||||
u32 type = 0;
|
||||
int status;
|
||||
|
||||
/* Check if firmware supports reading module EEPROM. */
|
||||
if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
|
||||
@ -5582,8 +5581,8 @@ static int i40e_get_module_eeprom(struct net_device *netdev,
|
||||
struct i40e_pf *pf = vsi->back;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
bool is_sfp = false;
|
||||
i40e_status status;
|
||||
u32 value = 0;
|
||||
int status;
|
||||
int i;
|
||||
|
||||
if (!ee || !ee->len || !data)
|
||||
@ -5624,10 +5623,10 @@ static int i40e_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
|
||||
{
|
||||
struct i40e_netdev_priv *np = netdev_priv(netdev);
|
||||
struct i40e_aq_get_phy_abilities_resp phy_cfg;
|
||||
enum i40e_status_code status = 0;
|
||||
struct i40e_vsi *vsi = np->vsi;
|
||||
struct i40e_pf *pf = vsi->back;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
int status = 0;
|
||||
|
||||
/* Get initial PHY capabilities */
|
||||
status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_cfg, NULL);
|
||||
@ -5689,11 +5688,11 @@ static int i40e_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
|
||||
{
|
||||
struct i40e_netdev_priv *np = netdev_priv(netdev);
|
||||
struct i40e_aq_get_phy_abilities_resp abilities;
|
||||
enum i40e_status_code status = I40E_SUCCESS;
|
||||
struct i40e_aq_set_phy_config config;
|
||||
struct i40e_vsi *vsi = np->vsi;
|
||||
struct i40e_pf *pf = vsi->back;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
int status = I40E_SUCCESS;
|
||||
__le16 eee_capability;
|
||||
|
||||
/* Deny parameters we don't support */
|
||||
|
@ -17,17 +17,17 @@
|
||||
* @type: what type of segment descriptor we're manipulating
|
||||
* @direct_mode_sz: size to alloc in direct mode
|
||||
**/
|
||||
i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 sd_index,
|
||||
enum i40e_sd_entry_type type,
|
||||
u64 direct_mode_sz)
|
||||
int i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 sd_index,
|
||||
enum i40e_sd_entry_type type,
|
||||
u64 direct_mode_sz)
|
||||
{
|
||||
enum i40e_memory_type mem_type __attribute__((unused));
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
bool dma_mem_alloc_done = false;
|
||||
int ret_code = I40E_SUCCESS;
|
||||
struct i40e_dma_mem mem;
|
||||
i40e_status ret_code = I40E_SUCCESS;
|
||||
u64 alloc_len;
|
||||
|
||||
if (NULL == hmc_info->sd_table.sd_entry) {
|
||||
@ -106,19 +106,19 @@ i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
* aligned on 4K boundary and zeroed memory.
|
||||
* 2. It should be 4K in size.
|
||||
**/
|
||||
i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 pd_index,
|
||||
struct i40e_dma_mem *rsrc_pg)
|
||||
int i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 pd_index,
|
||||
struct i40e_dma_mem *rsrc_pg)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
struct i40e_hmc_pd_table *pd_table;
|
||||
struct i40e_hmc_pd_entry *pd_entry;
|
||||
struct i40e_dma_mem mem;
|
||||
struct i40e_dma_mem *page = &mem;
|
||||
u32 sd_idx, rel_pd_idx;
|
||||
u64 *pd_addr;
|
||||
int ret_code = 0;
|
||||
u64 page_desc;
|
||||
u64 *pd_addr;
|
||||
|
||||
if (pd_index / I40E_HMC_PD_CNT_IN_SD >= hmc_info->sd_table.sd_cnt) {
|
||||
ret_code = I40E_ERR_INVALID_PAGE_DESC_INDEX;
|
||||
@ -185,15 +185,15 @@ i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
* 1. Caller can deallocate the memory used by backing storage after this
|
||||
* function returns.
|
||||
**/
|
||||
i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
int i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
struct i40e_hmc_pd_entry *pd_entry;
|
||||
struct i40e_hmc_pd_table *pd_table;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
u32 sd_idx, rel_pd_idx;
|
||||
int ret_code = 0;
|
||||
u64 *pd_addr;
|
||||
|
||||
/* calculate index */
|
||||
@ -241,11 +241,11 @@ i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @idx: the page index
|
||||
**/
|
||||
i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
int i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
int ret_code = 0;
|
||||
|
||||
/* get the entry and decrease its ref counter */
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[idx];
|
||||
@ -269,9 +269,9 @@ i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
* @idx: the page index
|
||||
* @is_pf: used to distinguish between VF and PF
|
||||
**/
|
||||
i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf)
|
||||
int i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf)
|
||||
{
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
|
||||
@ -290,11 +290,11 @@ i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @idx: segment descriptor index to find the relevant page descriptor
|
||||
**/
|
||||
i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
int i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
int ret_code = 0;
|
||||
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[idx];
|
||||
|
||||
@ -318,9 +318,9 @@ i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
* @idx: segment descriptor index to find the relevant page descriptor
|
||||
* @is_pf: used to distinguish between VF and PF
|
||||
**/
|
||||
i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf)
|
||||
int i40e_remove_pd_page_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf)
|
||||
{
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
|
||||
|
@ -187,28 +187,28 @@ struct i40e_hmc_info {
|
||||
/* add one more to the limit to correct our range */ \
|
||||
*(pd_limit) += 1; \
|
||||
}
|
||||
i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 sd_index,
|
||||
enum i40e_sd_entry_type type,
|
||||
u64 direct_mode_sz);
|
||||
|
||||
i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 pd_index,
|
||||
struct i40e_dma_mem *rsrc_pg);
|
||||
i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
int i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 sd_index,
|
||||
enum i40e_sd_entry_type type,
|
||||
u64 direct_mode_sz);
|
||||
int i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 pd_index,
|
||||
struct i40e_dma_mem *rsrc_pg);
|
||||
int i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
int i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
int i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
int i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
int i40e_remove_pd_page_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
|
||||
#endif /* _I40E_HMC_H_ */
|
||||
|
@ -74,12 +74,12 @@ static u64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,
|
||||
* Assumptions:
|
||||
* - HMC Resource Profile has been selected before calling this function.
|
||||
**/
|
||||
i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
|
||||
u32 rxq_num, u32 fcoe_cntx_num,
|
||||
u32 fcoe_filt_num)
|
||||
int i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
|
||||
u32 rxq_num, u32 fcoe_cntx_num,
|
||||
u32 fcoe_filt_num)
|
||||
{
|
||||
struct i40e_hmc_obj_info *obj, *full_obj;
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
u64 l2fpm_size;
|
||||
u32 size_exp;
|
||||
|
||||
@ -229,11 +229,11 @@ i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
|
||||
* 1. caller can deallocate the memory used by pd after this function
|
||||
* returns.
|
||||
**/
|
||||
static i40e_status i40e_remove_pd_page(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
static int i40e_remove_pd_page(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
|
||||
if (!i40e_prep_remove_pd_page(hmc_info, idx))
|
||||
ret_code = i40e_remove_pd_page_new(hw, hmc_info, idx, true);
|
||||
@ -256,11 +256,11 @@ static i40e_status i40e_remove_pd_page(struct i40e_hw *hw,
|
||||
* 1. caller can deallocate the memory used by backing storage after this
|
||||
* function returns.
|
||||
**/
|
||||
static i40e_status i40e_remove_sd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
static int i40e_remove_sd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
|
||||
if (!i40e_prep_remove_sd_bp(hmc_info, idx))
|
||||
ret_code = i40e_remove_sd_bp_new(hw, hmc_info, idx, true);
|
||||
@ -276,15 +276,15 @@ static i40e_status i40e_remove_sd_bp(struct i40e_hw *hw,
|
||||
* This will allocate memory for PDs and backing pages and populate
|
||||
* the sd and pd entries.
|
||||
**/
|
||||
static i40e_status i40e_create_lan_hmc_object(struct i40e_hw *hw,
|
||||
struct i40e_hmc_lan_create_obj_info *info)
|
||||
static int i40e_create_lan_hmc_object(struct i40e_hw *hw,
|
||||
struct i40e_hmc_lan_create_obj_info *info)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
u32 pd_idx1 = 0, pd_lmt1 = 0;
|
||||
u32 pd_idx = 0, pd_lmt = 0;
|
||||
bool pd_error = false;
|
||||
u32 sd_idx, sd_lmt;
|
||||
int ret_code = 0;
|
||||
u64 sd_size;
|
||||
u32 i, j;
|
||||
|
||||
@ -435,13 +435,13 @@ static i40e_status i40e_create_lan_hmc_object(struct i40e_hw *hw,
|
||||
* - This function will be called after i40e_init_lan_hmc() and before
|
||||
* any LAN/FCoE HMC objects can be created.
|
||||
**/
|
||||
i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
|
||||
enum i40e_hmc_model model)
|
||||
int i40e_configure_lan_hmc(struct i40e_hw *hw,
|
||||
enum i40e_hmc_model model)
|
||||
{
|
||||
struct i40e_hmc_lan_create_obj_info info;
|
||||
i40e_status ret_code = 0;
|
||||
u8 hmc_fn_id = hw->hmc.hmc_fn_id;
|
||||
struct i40e_hmc_obj_info *obj;
|
||||
int ret_code = 0;
|
||||
|
||||
/* Initialize part of the create object info struct */
|
||||
info.hmc_info = &hw->hmc;
|
||||
@ -520,13 +520,13 @@ i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
|
||||
* caller should deallocate memory allocated previously for
|
||||
* book-keeping information about PDs and backing storage.
|
||||
**/
|
||||
static i40e_status i40e_delete_lan_hmc_object(struct i40e_hw *hw,
|
||||
struct i40e_hmc_lan_delete_obj_info *info)
|
||||
static int i40e_delete_lan_hmc_object(struct i40e_hw *hw,
|
||||
struct i40e_hmc_lan_delete_obj_info *info)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
struct i40e_hmc_pd_table *pd_table;
|
||||
u32 pd_idx, pd_lmt, rel_pd_idx;
|
||||
u32 sd_idx, sd_lmt;
|
||||
int ret_code = 0;
|
||||
u32 i, j;
|
||||
|
||||
if (NULL == info) {
|
||||
@ -632,10 +632,10 @@ static i40e_status i40e_delete_lan_hmc_object(struct i40e_hw *hw,
|
||||
* This must be called by drivers as they are shutting down and being
|
||||
* removed from the OS.
|
||||
**/
|
||||
i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw)
|
||||
int i40e_shutdown_lan_hmc(struct i40e_hw *hw)
|
||||
{
|
||||
struct i40e_hmc_lan_delete_obj_info info;
|
||||
i40e_status ret_code;
|
||||
int ret_code;
|
||||
|
||||
info.hmc_info = &hw->hmc;
|
||||
info.rsrc_type = I40E_HMC_LAN_FULL;
|
||||
@ -915,9 +915,9 @@ static void i40e_write_qword(u8 *hmc_bits,
|
||||
* @context_bytes: pointer to the context bit array (DMA memory)
|
||||
* @hmc_type: the type of HMC resource
|
||||
**/
|
||||
static i40e_status i40e_clear_hmc_context(struct i40e_hw *hw,
|
||||
u8 *context_bytes,
|
||||
enum i40e_hmc_lan_rsrc_type hmc_type)
|
||||
static int i40e_clear_hmc_context(struct i40e_hw *hw,
|
||||
u8 *context_bytes,
|
||||
enum i40e_hmc_lan_rsrc_type hmc_type)
|
||||
{
|
||||
/* clean the bit array */
|
||||
memset(context_bytes, 0, (u32)hw->hmc.hmc_obj[hmc_type].size);
|
||||
@ -931,9 +931,9 @@ static i40e_status i40e_clear_hmc_context(struct i40e_hw *hw,
|
||||
* @ce_info: a description of the struct to be filled
|
||||
* @dest: the struct to be filled
|
||||
**/
|
||||
static i40e_status i40e_set_hmc_context(u8 *context_bytes,
|
||||
struct i40e_context_ele *ce_info,
|
||||
u8 *dest)
|
||||
static int i40e_set_hmc_context(u8 *context_bytes,
|
||||
struct i40e_context_ele *ce_info,
|
||||
u8 *dest)
|
||||
{
|
||||
int f;
|
||||
|
||||
@ -973,18 +973,18 @@ static i40e_status i40e_set_hmc_context(u8 *context_bytes,
|
||||
* base pointer. This function is used for LAN Queue contexts.
|
||||
**/
|
||||
static
|
||||
i40e_status i40e_hmc_get_object_va(struct i40e_hw *hw, u8 **object_base,
|
||||
enum i40e_hmc_lan_rsrc_type rsrc_type,
|
||||
u32 obj_idx)
|
||||
int i40e_hmc_get_object_va(struct i40e_hw *hw, u8 **object_base,
|
||||
enum i40e_hmc_lan_rsrc_type rsrc_type,
|
||||
u32 obj_idx)
|
||||
{
|
||||
struct i40e_hmc_info *hmc_info = &hw->hmc;
|
||||
u32 obj_offset_in_sd, obj_offset_in_pd;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
struct i40e_hmc_pd_entry *pd_entry;
|
||||
u32 pd_idx, pd_lmt, rel_pd_idx;
|
||||
i40e_status ret_code = 0;
|
||||
u64 obj_offset_in_fpm;
|
||||
u32 sd_idx, sd_lmt;
|
||||
int ret_code = 0;
|
||||
|
||||
if (NULL == hmc_info) {
|
||||
ret_code = I40E_ERR_BAD_PTR;
|
||||
@ -1042,11 +1042,11 @@ i40e_status i40e_hmc_get_object_va(struct i40e_hw *hw, u8 **object_base,
|
||||
* @hw: the hardware struct
|
||||
* @queue: the queue we care about
|
||||
**/
|
||||
i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue)
|
||||
int i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue)
|
||||
{
|
||||
i40e_status err;
|
||||
u8 *context_bytes;
|
||||
int err;
|
||||
|
||||
err = i40e_hmc_get_object_va(hw, &context_bytes,
|
||||
I40E_HMC_LAN_TX, queue);
|
||||
@ -1062,12 +1062,12 @@ i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
* @queue: the queue we care about
|
||||
* @s: the struct to be filled
|
||||
**/
|
||||
i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s)
|
||||
int i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s)
|
||||
{
|
||||
i40e_status err;
|
||||
u8 *context_bytes;
|
||||
int err;
|
||||
|
||||
err = i40e_hmc_get_object_va(hw, &context_bytes,
|
||||
I40E_HMC_LAN_TX, queue);
|
||||
@ -1083,11 +1083,11 @@ i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
* @hw: the hardware struct
|
||||
* @queue: the queue we care about
|
||||
**/
|
||||
i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue)
|
||||
int i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue)
|
||||
{
|
||||
i40e_status err;
|
||||
u8 *context_bytes;
|
||||
int err;
|
||||
|
||||
err = i40e_hmc_get_object_va(hw, &context_bytes,
|
||||
I40E_HMC_LAN_RX, queue);
|
||||
@ -1103,12 +1103,12 @@ i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
* @queue: the queue we care about
|
||||
* @s: the struct to be filled
|
||||
**/
|
||||
i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s)
|
||||
int i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s)
|
||||
{
|
||||
i40e_status err;
|
||||
u8 *context_bytes;
|
||||
int err;
|
||||
|
||||
err = i40e_hmc_get_object_va(hw, &context_bytes,
|
||||
I40E_HMC_LAN_RX, queue);
|
||||
|
@ -137,22 +137,22 @@ struct i40e_hmc_lan_delete_obj_info {
|
||||
u32 count;
|
||||
};
|
||||
|
||||
i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
|
||||
u32 rxq_num, u32 fcoe_cntx_num,
|
||||
u32 fcoe_filt_num);
|
||||
i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
|
||||
enum i40e_hmc_model model);
|
||||
i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);
|
||||
int i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
|
||||
u32 rxq_num, u32 fcoe_cntx_num,
|
||||
u32 fcoe_filt_num);
|
||||
int i40e_configure_lan_hmc(struct i40e_hw *hw,
|
||||
enum i40e_hmc_model model);
|
||||
int i40e_shutdown_lan_hmc(struct i40e_hw *hw);
|
||||
|
||||
i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s);
|
||||
i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s);
|
||||
int i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
int i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s);
|
||||
int i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
int i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s);
|
||||
|
||||
#endif /* _I40E_LAN_HMC_H_ */
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -13,10 +13,10 @@
|
||||
* in this file) as an equivalent of the FLASH part mapped into the SR.
|
||||
* We are accessing FLASH always thru the Shadow RAM.
|
||||
**/
|
||||
i40e_status i40e_init_nvm(struct i40e_hw *hw)
|
||||
int i40e_init_nvm(struct i40e_hw *hw)
|
||||
{
|
||||
struct i40e_nvm_info *nvm = &hw->nvm;
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
u32 fla, gens;
|
||||
u8 sr_size;
|
||||
|
||||
@ -52,12 +52,12 @@ i40e_status i40e_init_nvm(struct i40e_hw *hw)
|
||||
* This function will request NVM ownership for reading
|
||||
* via the proper Admin Command.
|
||||
**/
|
||||
i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
|
||||
enum i40e_aq_resource_access_type access)
|
||||
int i40e_acquire_nvm(struct i40e_hw *hw,
|
||||
enum i40e_aq_resource_access_type access)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
u64 gtime, timeout;
|
||||
u64 time_left = 0;
|
||||
int ret_code = 0;
|
||||
|
||||
if (hw->nvm.blank_nvm_mode)
|
||||
goto i40e_i40e_acquire_nvm_exit;
|
||||
@ -111,7 +111,7 @@ i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
|
||||
**/
|
||||
void i40e_release_nvm(struct i40e_hw *hw)
|
||||
{
|
||||
i40e_status ret_code = I40E_SUCCESS;
|
||||
int ret_code = I40E_SUCCESS;
|
||||
u32 total_delay = 0;
|
||||
|
||||
if (hw->nvm.blank_nvm_mode)
|
||||
@ -138,9 +138,9 @@ void i40e_release_nvm(struct i40e_hw *hw)
|
||||
*
|
||||
* Polls the SRCTL Shadow RAM register done bit.
|
||||
**/
|
||||
static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
|
||||
static int i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
|
||||
{
|
||||
i40e_status ret_code = I40E_ERR_TIMEOUT;
|
||||
int ret_code = I40E_ERR_TIMEOUT;
|
||||
u32 srctl, wait_cnt;
|
||||
|
||||
/* Poll the I40E_GLNVM_SRCTL until the done bit is set */
|
||||
@ -165,10 +165,10 @@ static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
|
||||
*
|
||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
|
||||
**/
|
||||
static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data)
|
||||
static int i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data)
|
||||
{
|
||||
i40e_status ret_code = I40E_ERR_TIMEOUT;
|
||||
int ret_code = I40E_ERR_TIMEOUT;
|
||||
u32 sr_reg;
|
||||
|
||||
if (offset >= hw->nvm.sr_size) {
|
||||
@ -216,13 +216,13 @@ static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
|
||||
*
|
||||
* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
|
||||
**/
|
||||
static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw,
|
||||
u8 module_pointer, u32 offset,
|
||||
u16 words, void *data,
|
||||
bool last_command)
|
||||
static int i40e_read_nvm_aq(struct i40e_hw *hw,
|
||||
u8 module_pointer, u32 offset,
|
||||
u16 words, void *data,
|
||||
bool last_command)
|
||||
{
|
||||
i40e_status ret_code = I40E_ERR_NVM;
|
||||
struct i40e_asq_cmd_details cmd_details;
|
||||
int ret_code = I40E_ERR_NVM;
|
||||
|
||||
memset(&cmd_details, 0, sizeof(cmd_details));
|
||||
cmd_details.wb_desc = &hw->nvm_wb_desc;
|
||||
@ -264,10 +264,10 @@ static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw,
|
||||
*
|
||||
* Reads one 16 bit word from the Shadow RAM using the AdminQ
|
||||
**/
|
||||
static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data)
|
||||
static int i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data)
|
||||
{
|
||||
i40e_status ret_code = I40E_ERR_TIMEOUT;
|
||||
int ret_code = I40E_ERR_TIMEOUT;
|
||||
|
||||
ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
|
||||
*data = le16_to_cpu(*(__le16 *)data);
|
||||
@ -286,8 +286,8 @@ static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
|
||||
* Do not use this function except in cases where the nvm lock is already
|
||||
* taken via i40e_acquire_nvm().
|
||||
**/
|
||||
static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw,
|
||||
u16 offset, u16 *data)
|
||||
static int __i40e_read_nvm_word(struct i40e_hw *hw,
|
||||
u16 offset, u16 *data)
|
||||
{
|
||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
|
||||
return i40e_read_nvm_word_aq(hw, offset, data);
|
||||
@ -303,10 +303,10 @@ static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw,
|
||||
*
|
||||
* Reads one 16 bit word from the Shadow RAM.
|
||||
**/
|
||||
i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data)
|
||||
int i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
|
||||
if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
|
||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
|
||||
@ -330,17 +330,17 @@ i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
* @words_data_size: Words to read from NVM
|
||||
* @data_ptr: Pointer to memory location where resulting buffer will be stored
|
||||
**/
|
||||
enum i40e_status_code i40e_read_nvm_module_data(struct i40e_hw *hw,
|
||||
u8 module_ptr,
|
||||
u16 module_offset,
|
||||
u16 data_offset,
|
||||
u16 words_data_size,
|
||||
u16 *data_ptr)
|
||||
int i40e_read_nvm_module_data(struct i40e_hw *hw,
|
||||
u8 module_ptr,
|
||||
u16 module_offset,
|
||||
u16 data_offset,
|
||||
u16 words_data_size,
|
||||
u16 *data_ptr)
|
||||
{
|
||||
i40e_status status;
|
||||
u16 specific_ptr = 0;
|
||||
u16 ptr_value = 0;
|
||||
u32 offset = 0;
|
||||
int status;
|
||||
|
||||
if (module_ptr != 0) {
|
||||
status = i40e_read_nvm_word(hw, module_ptr, &ptr_value);
|
||||
@ -406,10 +406,10 @@ enum i40e_status_code i40e_read_nvm_module_data(struct i40e_hw *hw,
|
||||
* method. The buffer read is preceded by the NVM ownership take
|
||||
* and followed by the release.
|
||||
**/
|
||||
static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
static int i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
u16 index, word;
|
||||
|
||||
/* Loop thru the selected region */
|
||||
@ -437,13 +437,13 @@ static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
|
||||
* method. The buffer read is preceded by the NVM ownership take
|
||||
* and followed by the release.
|
||||
**/
|
||||
static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
static int i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
{
|
||||
i40e_status ret_code;
|
||||
u16 read_size;
|
||||
bool last_cmd = false;
|
||||
u16 words_read = 0;
|
||||
u16 read_size;
|
||||
int ret_code;
|
||||
u16 i = 0;
|
||||
|
||||
do {
|
||||
@ -493,9 +493,9 @@ static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
|
||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
|
||||
* method.
|
||||
**/
|
||||
static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
|
||||
u16 offset, u16 *words,
|
||||
u16 *data)
|
||||
static int __i40e_read_nvm_buffer(struct i40e_hw *hw,
|
||||
u16 offset, u16 *words,
|
||||
u16 *data)
|
||||
{
|
||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
|
||||
return i40e_read_nvm_buffer_aq(hw, offset, words, data);
|
||||
@ -514,10 +514,10 @@ static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
|
||||
* method. The buffer read is preceded by the NVM ownership take
|
||||
* and followed by the release.
|
||||
**/
|
||||
i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
int i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
int ret_code = 0;
|
||||
|
||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
|
||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
|
||||
@ -544,12 +544,12 @@ i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
*
|
||||
* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
|
||||
**/
|
||||
static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 words, void *data,
|
||||
bool last_command)
|
||||
static int i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 words, void *data,
|
||||
bool last_command)
|
||||
{
|
||||
i40e_status ret_code = I40E_ERR_NVM;
|
||||
struct i40e_asq_cmd_details cmd_details;
|
||||
int ret_code = I40E_ERR_NVM;
|
||||
|
||||
memset(&cmd_details, 0, sizeof(cmd_details));
|
||||
cmd_details.wb_desc = &hw->nvm_wb_desc;
|
||||
@ -594,14 +594,14 @@ static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
|
||||
* is customer specific and unknown. Therefore, this function skips all maximum
|
||||
* possible size of VPD (1kB).
|
||||
**/
|
||||
static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum)
|
||||
static int i40e_calc_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum)
|
||||
{
|
||||
i40e_status ret_code;
|
||||
struct i40e_virt_mem vmem;
|
||||
u16 pcie_alt_module = 0;
|
||||
u16 checksum_local = 0;
|
||||
u16 vpd_module = 0;
|
||||
int ret_code;
|
||||
u16 *data;
|
||||
u16 i = 0;
|
||||
|
||||
@ -675,11 +675,11 @@ static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
|
||||
* on ARQ completion event reception by caller.
|
||||
* This function will commit SR to NVM.
|
||||
**/
|
||||
i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
|
||||
int i40e_update_nvm_checksum(struct i40e_hw *hw)
|
||||
{
|
||||
i40e_status ret_code;
|
||||
u16 checksum;
|
||||
__le16 le_sum;
|
||||
int ret_code;
|
||||
u16 checksum;
|
||||
|
||||
ret_code = i40e_calc_nvm_checksum(hw, &checksum);
|
||||
if (!ret_code) {
|
||||
@ -699,12 +699,12 @@ i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
|
||||
* Performs checksum calculation and validates the NVM SW checksum. If the
|
||||
* caller does not need checksum, the value can be NULL.
|
||||
**/
|
||||
i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum)
|
||||
int i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum)
|
||||
{
|
||||
i40e_status ret_code = 0;
|
||||
u16 checksum_sr = 0;
|
||||
u16 checksum_local = 0;
|
||||
u16 checksum_sr = 0;
|
||||
int ret_code = 0;
|
||||
|
||||
/* We must acquire the NVM lock in order to correctly synchronize the
|
||||
* NVM accesses across multiple PFs. Without doing so it is possible
|
||||
@ -733,36 +733,36 @@ i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
static int i40e_nvmupd_state_init(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static int i40e_nvmupd_state_reading(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static int i40e_nvmupd_state_writing(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *perrno);
|
||||
static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *perrno);
|
||||
static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static int i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *perrno);
|
||||
static int i40e_nvmupd_nvm_write(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static int i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static int i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static int i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno);
|
||||
static inline u8 i40e_nvmupd_get_module(u32 val)
|
||||
{
|
||||
return (u8)(val & I40E_NVM_MOD_PNT_MASK);
|
||||
@ -807,12 +807,12 @@ static const char * const i40e_nvm_update_state_str[] = {
|
||||
*
|
||||
* Dispatches command depending on what update state is current
|
||||
**/
|
||||
i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
int i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
i40e_status status;
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
int status;
|
||||
|
||||
/* assume success */
|
||||
*perrno = 0;
|
||||
@ -923,12 +923,12 @@ i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
* Process legitimate commands of the Init state and conditionally set next
|
||||
* state. Reject all other commands.
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_state_init(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
i40e_status status = 0;
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
int status = 0;
|
||||
|
||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
|
||||
|
||||
@ -1062,12 +1062,12 @@ static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
|
||||
* NVM ownership is already held. Process legitimate commands and set any
|
||||
* change in state; reject all other commands.
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_state_reading(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
i40e_status status = 0;
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
int status = 0;
|
||||
|
||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
|
||||
|
||||
@ -1104,13 +1104,13 @@ static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
|
||||
* NVM ownership is already held. Process legitimate commands and set any
|
||||
* change in state; reject all other commands
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_state_writing(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
i40e_status status = 0;
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
bool retry_attempt = false;
|
||||
int status = 0;
|
||||
|
||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
|
||||
|
||||
@ -1187,8 +1187,8 @@ static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
|
||||
*/
|
||||
if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
|
||||
!retry_attempt) {
|
||||
i40e_status old_status = status;
|
||||
u32 old_asq_status = hw->aq.asq_last_status;
|
||||
int old_status = status;
|
||||
u32 gtime;
|
||||
|
||||
gtime = rd32(hw, I40E_GLVFGEN_TIMER);
|
||||
@ -1370,17 +1370,17 @@ static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
|
||||
*
|
||||
* cmd structure contains identifiers and data buffer
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
struct i40e_asq_cmd_details cmd_details;
|
||||
i40e_status status;
|
||||
struct i40e_aq_desc *aq_desc;
|
||||
u32 buff_size = 0;
|
||||
u8 *buff = NULL;
|
||||
u32 aq_desc_len;
|
||||
u32 aq_data_len;
|
||||
int status;
|
||||
|
||||
i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
|
||||
if (cmd->offset == 0xffff)
|
||||
@ -1429,8 +1429,8 @@ static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
|
||||
buff_size, &cmd_details);
|
||||
if (status) {
|
||||
i40e_debug(hw, I40E_DEBUG_NVM,
|
||||
"i40e_nvmupd_exec_aq err %s aq_err %s\n",
|
||||
i40e_stat_str(hw, status),
|
||||
"%s err %pe aq_err %s\n",
|
||||
__func__, ERR_PTR(status),
|
||||
i40e_aq_str(hw, hw->aq.asq_last_status));
|
||||
*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
|
||||
return status;
|
||||
@ -1454,9 +1454,9 @@ static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
|
||||
*
|
||||
* cmd structure contains identifiers and data buffer
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
u32 aq_total_len;
|
||||
u32 aq_desc_len;
|
||||
@ -1523,9 +1523,9 @@ static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
|
||||
*
|
||||
* cmd structure contains identifiers and data buffer
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
u32 aq_total_len;
|
||||
u32 aq_desc_len;
|
||||
@ -1557,13 +1557,13 @@ static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
|
||||
*
|
||||
* cmd structure contains identifiers and data buffer
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
struct i40e_asq_cmd_details cmd_details;
|
||||
i40e_status status;
|
||||
u8 module, transaction;
|
||||
int status;
|
||||
bool last;
|
||||
|
||||
transaction = i40e_nvmupd_get_transaction(cmd->config);
|
||||
@ -1596,13 +1596,13 @@ static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
||||
*
|
||||
* module, offset, data_size and data are in cmd structure
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *perrno)
|
||||
static int i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *perrno)
|
||||
{
|
||||
i40e_status status = 0;
|
||||
struct i40e_asq_cmd_details cmd_details;
|
||||
u8 module, transaction;
|
||||
int status = 0;
|
||||
bool last;
|
||||
|
||||
transaction = i40e_nvmupd_get_transaction(cmd->config);
|
||||
@ -1636,14 +1636,14 @@ static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
||||
*
|
||||
* module, offset, data_size and data are in cmd structure
|
||||
**/
|
||||
static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
static int i40e_nvmupd_nvm_write(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *perrno)
|
||||
{
|
||||
i40e_status status = 0;
|
||||
struct i40e_asq_cmd_details cmd_details;
|
||||
u8 module, transaction;
|
||||
u8 preservation_flags;
|
||||
int status = 0;
|
||||
bool last;
|
||||
|
||||
transaction = i40e_nvmupd_get_transaction(cmd->config);
|
||||
|
@ -56,5 +56,4 @@ do { \
|
||||
(h)->bus.func, ##__VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
typedef enum i40e_status_code i40e_status;
|
||||
#endif /* _I40E_OSDEP_H_ */
|
||||
|
@ -16,29 +16,29 @@
|
||||
*/
|
||||
|
||||
/* adminq functions */
|
||||
i40e_status i40e_init_adminq(struct i40e_hw *hw);
|
||||
int i40e_init_adminq(struct i40e_hw *hw);
|
||||
void i40e_shutdown_adminq(struct i40e_hw *hw);
|
||||
void i40e_adminq_init_ring_data(struct i40e_hw *hw);
|
||||
i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
|
||||
struct i40e_arq_event_info *e,
|
||||
u16 *events_pending);
|
||||
i40e_status
|
||||
int i40e_clean_arq_element(struct i40e_hw *hw,
|
||||
struct i40e_arq_event_info *e,
|
||||
u16 *events_pending);
|
||||
int
|
||||
i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,
|
||||
void *buff, /* can be NULL */ u16 buff_size,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status
|
||||
int
|
||||
i40e_asq_send_command_v2(struct i40e_hw *hw,
|
||||
struct i40e_aq_desc *desc,
|
||||
void *buff, /* can be NULL */
|
||||
u16 buff_size,
|
||||
struct i40e_asq_cmd_details *cmd_details,
|
||||
enum i40e_admin_queue_err *aq_status);
|
||||
i40e_status
|
||||
int
|
||||
i40e_asq_send_command_atomic(struct i40e_hw *hw, struct i40e_aq_desc *desc,
|
||||
void *buff, /* can be NULL */ u16 buff_size,
|
||||
struct i40e_asq_cmd_details *cmd_details,
|
||||
bool is_atomic_context);
|
||||
i40e_status
|
||||
int
|
||||
i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,
|
||||
struct i40e_aq_desc *desc,
|
||||
void *buff, /* can be NULL */
|
||||
@ -53,327 +53,332 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
|
||||
|
||||
void i40e_idle_aq(struct i40e_hw *hw);
|
||||
bool i40e_check_asq_alive(struct i40e_hw *hw);
|
||||
i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
|
||||
int i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
|
||||
const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);
|
||||
const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err);
|
||||
|
||||
i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
|
||||
bool pf_lut, u8 *lut, u16 lut_size);
|
||||
i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,
|
||||
bool pf_lut, u8 *lut, u16 lut_size);
|
||||
i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_get_set_rss_key_data *key);
|
||||
i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_get_set_rss_key_data *key);
|
||||
int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
|
||||
bool pf_lut, u8 *lut, u16 lut_size);
|
||||
int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,
|
||||
bool pf_lut, u8 *lut, u16 lut_size);
|
||||
int i40e_aq_get_rss_key(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_get_set_rss_key_data *key);
|
||||
int i40e_aq_set_rss_key(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_get_set_rss_key_data *key);
|
||||
|
||||
u32 i40e_led_get(struct i40e_hw *hw);
|
||||
void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);
|
||||
i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
|
||||
u16 led_addr, u32 mode);
|
||||
i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
|
||||
u16 *val);
|
||||
i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
|
||||
u32 time, u32 interval);
|
||||
int i40e_led_set_phy(struct i40e_hw *hw, bool on,
|
||||
u16 led_addr, u32 mode);
|
||||
int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
|
||||
u16 *val);
|
||||
int i40e_blink_phy_link_led(struct i40e_hw *hw,
|
||||
u32 time, u32 interval);
|
||||
|
||||
/* admin send queue commands */
|
||||
|
||||
i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
|
||||
u16 *fw_major_version, u16 *fw_minor_version,
|
||||
u32 *fw_build,
|
||||
u16 *api_major_version, u16 *api_minor_version,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u64 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
|
||||
int i40e_aq_get_firmware_version(struct i40e_hw *hw,
|
||||
u16 *fw_major_version, u16 *fw_minor_version,
|
||||
u32 *fw_build,
|
||||
u16 *api_major_version, u16 *api_minor_version,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_debug_write_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u64 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_debug_read_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u64 *reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
|
||||
int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_clear_default_vsi(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
|
||||
bool qualified_modules, bool report_init,
|
||||
struct i40e_aq_get_phy_abilities_resp *abilities,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_phy_config(struct i40e_hw *hw,
|
||||
struct i40e_aq_set_phy_config *config,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
|
||||
bool atomic_reset);
|
||||
int i40e_aq_set_mac_loopback(struct i40e_hw *hw,
|
||||
bool ena_lpbk,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_phy_int_mask(struct i40e_hw *hw, u16 mask,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_link_restart_an(struct i40e_hw *hw,
|
||||
bool enable_link,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
|
||||
bool qualified_modules, bool report_init,
|
||||
struct i40e_aq_get_phy_abilities_resp *abilities,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
|
||||
struct i40e_aq_set_phy_config *config,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
|
||||
bool atomic_reset);
|
||||
i40e_status i40e_aq_set_mac_loopback(struct i40e_hw *hw,
|
||||
bool ena_lpbk,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, u16 mask,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
|
||||
bool enable_link,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
|
||||
bool enable_lse, struct i40e_link_status *link,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
|
||||
u64 advt_reg,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
|
||||
int i40e_aq_get_link_info(struct i40e_hw *hw,
|
||||
bool enable_lse, struct i40e_link_status *link,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
|
||||
u64 advt_reg,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_send_driver_version(struct i40e_hw *hw,
|
||||
struct i40e_driver_version *dv,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
|
||||
u16 vsi_id, bool set_filter,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
|
||||
u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details,
|
||||
bool rx_only_promisc);
|
||||
i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
|
||||
u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
|
||||
u16 seid, bool enable,
|
||||
u16 vid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
|
||||
u16 seid, bool enable,
|
||||
u16 vid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
|
||||
u16 seid, bool enable, u16 vid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
|
||||
u16 seid, bool enable,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
|
||||
u16 downlink_seid, u8 enabled_tc,
|
||||
bool default_port, u16 *pveb_seid,
|
||||
bool enable_stats,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
|
||||
u16 veb_seid, u16 *switch_id, bool *floating,
|
||||
u16 *statistic_index, u16 *vebs_used,
|
||||
u16 *vebs_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
int i40e_aq_add_vsi(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
|
||||
u16 vsi_id, bool set_filter,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, u16 vsi_id, bool set,
|
||||
struct i40e_asq_cmd_details *cmd_details,
|
||||
bool rx_only_promisc);
|
||||
int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, u16 vsi_id, bool set,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
|
||||
u16 seid, bool enable,
|
||||
u16 vid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
|
||||
u16 seid, bool enable,
|
||||
u16 vid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
|
||||
u16 seid, bool enable, u16 vid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
|
||||
u16 seid, bool enable,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_get_vsi_params(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_update_vsi_params(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
|
||||
u16 downlink_seid, u8 enabled_tc,
|
||||
bool default_port, u16 *pveb_seid,
|
||||
bool enable_stats,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_get_veb_parameters(struct i40e_hw *hw,
|
||||
u16 veb_seid, u16 *switch_id, bool *floating,
|
||||
u16 *statistic_index, u16 *vebs_used,
|
||||
u16 *vebs_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_add_macvlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_aqc_add_macvlan_element_data *mv_list,
|
||||
u16 count, struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status
|
||||
int
|
||||
i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_add_macvlan_element_data *mv_list,
|
||||
u16 count, struct i40e_asq_cmd_details *cmd_details,
|
||||
enum i40e_admin_queue_err *aq_status);
|
||||
i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_aqc_remove_macvlan_element_data *mv_list,
|
||||
u16 count, struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status
|
||||
int i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_aqc_remove_macvlan_element_data *mv_list,
|
||||
u16 count, struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_remove_macvlan_element_data *mv_list,
|
||||
u16 count, struct i40e_asq_cmd_details *cmd_details,
|
||||
enum i40e_admin_queue_err *aq_status);
|
||||
i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
|
||||
u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
|
||||
struct i40e_asq_cmd_details *cmd_details,
|
||||
u16 *rule_id, u16 *rules_used, u16 *rules_free);
|
||||
i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
|
||||
u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
|
||||
struct i40e_asq_cmd_details *cmd_details,
|
||||
u16 *rules_used, u16 *rules_free);
|
||||
int i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
|
||||
u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
|
||||
struct i40e_asq_cmd_details *cmd_details,
|
||||
u16 *rule_id, u16 *rules_used, u16 *rules_free);
|
||||
int i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
|
||||
u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
|
||||
struct i40e_asq_cmd_details *cmd_details,
|
||||
u16 *rules_used, u16 *rules_free);
|
||||
|
||||
i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
|
||||
u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
|
||||
struct i40e_aqc_get_switch_config_resp *buf,
|
||||
u16 buf_size, u16 *start_seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
|
||||
u16 flags,
|
||||
u16 valid_flags, u8 mode,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
|
||||
enum i40e_aq_resources_ids resource,
|
||||
enum i40e_aq_resource_access_type access,
|
||||
u8 sdp_number, u64 *timeout,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
|
||||
enum i40e_aq_resources_ids resource,
|
||||
u8 sdp_number,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, void *data,
|
||||
bool last_command,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, bool last_command,
|
||||
int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
|
||||
u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_get_switch_config(struct i40e_hw *hw,
|
||||
struct i40e_aqc_get_switch_config_resp *buf,
|
||||
u16 buf_size, u16 *start_seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
|
||||
void *buff, u16 buff_size, u16 *data_size,
|
||||
enum i40e_admin_queue_opc list_type_opc,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, void *data,
|
||||
bool last_command, u8 preservation_flags,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
|
||||
u8 rearrange_nvm,
|
||||
int i40e_aq_set_switch_config(struct i40e_hw *hw,
|
||||
u16 flags,
|
||||
u16 valid_flags, u8 mode,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_request_resource(struct i40e_hw *hw,
|
||||
enum i40e_aq_resources_ids resource,
|
||||
enum i40e_aq_resource_access_type access,
|
||||
u8 sdp_number, u64 *timeout,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_release_resource(struct i40e_hw *hw,
|
||||
enum i40e_aq_resources_ids resource,
|
||||
u8 sdp_number,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, void *data,
|
||||
bool last_command,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, bool last_command,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_discover_capabilities(struct i40e_hw *hw,
|
||||
void *buff, u16 buff_size, u16 *data_size,
|
||||
enum i40e_admin_queue_opc list_type_opc,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
|
||||
u8 mib_type, void *buff, u16 buff_size,
|
||||
u16 *local_len, u16 *remote_len,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code
|
||||
int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, void *data,
|
||||
bool last_command, u8 preservation_flags,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_rearrange_nvm(struct i40e_hw *hw,
|
||||
u8 rearrange_nvm,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
|
||||
u8 mib_type, void *buff, u16 buff_size,
|
||||
u16 *local_len, u16 *remote_len,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_set_lldp_mib(struct i40e_hw *hw,
|
||||
u8 mib_type, void *buff, u16 buff_size,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
|
||||
bool enable_update,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code
|
||||
int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
|
||||
bool enable_update,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
|
||||
bool persist,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_set_dcb_parameters(struct i40e_hw *hw,
|
||||
bool dcb_enable,
|
||||
struct i40e_asq_cmd_details
|
||||
*cmd_details);
|
||||
i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
|
||||
int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
|
||||
bool persist,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_set_dcb_parameters(struct i40e_hw *hw,
|
||||
bool dcb_enable,
|
||||
struct i40e_asq_cmd_details
|
||||
*cmd_details);
|
||||
int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
|
||||
void *buff, u16 buff_size,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
|
||||
void *buff, u16 buff_size,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
|
||||
u16 udp_port, u8 protocol_index,
|
||||
u8 *filter_index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
|
||||
u16 flags, u8 *mac_addr,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
|
||||
int i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
|
||||
u16 udp_port, u8 protocol_index,
|
||||
u8 *filter_index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_mac_address_write(struct i40e_hw *hw,
|
||||
u16 flags, u8 *mac_addr,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
|
||||
u16 seid, u16 credit, u8 max_credit,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
|
||||
u16 seid, u16 credit, u8 max_bw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
|
||||
int i40e_aq_dcb_updated(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
|
||||
enum i40e_admin_queue_opc opcode,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
|
||||
int i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
|
||||
u16 seid, u16 credit, u8 max_bw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
|
||||
enum i40e_admin_queue_opc opcode,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_port_ets_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code
|
||||
int i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_query_port_ets_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_port_ets_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_resume_port_tx(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int
|
||||
i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_cloud_filters_element_bb *filters,
|
||||
u8 filter_count);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 vsi,
|
||||
struct i40e_aqc_cloud_filters_element_data *filters,
|
||||
u8 filter_count);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 vsi,
|
||||
struct i40e_aqc_cloud_filters_element_data *filters,
|
||||
u8 filter_count);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_cloud_filters_element_bb *filters,
|
||||
u8 filter_count);
|
||||
i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
struct i40e_lldp_variables *lldp_cfg);
|
||||
enum i40e_status_code
|
||||
int i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
struct i40e_lldp_variables *lldp_cfg);
|
||||
int
|
||||
i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
/* i40e_common */
|
||||
i40e_status i40e_init_shared_code(struct i40e_hw *hw);
|
||||
i40e_status i40e_pf_reset(struct i40e_hw *hw);
|
||||
int i40e_init_shared_code(struct i40e_hw *hw);
|
||||
int i40e_pf_reset(struct i40e_hw *hw);
|
||||
void i40e_clear_hw(struct i40e_hw *hw);
|
||||
void i40e_clear_pxe_mode(struct i40e_hw *hw);
|
||||
i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up);
|
||||
i40e_status i40e_update_link_info(struct i40e_hw *hw);
|
||||
i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
|
||||
i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
|
||||
u32 *max_bw, u32 *min_bw, bool *min_valid,
|
||||
bool *max_valid);
|
||||
i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
|
||||
struct i40e_aqc_configure_partition_bw_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
|
||||
i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
|
||||
u32 pba_num_size);
|
||||
i40e_status i40e_validate_mac_addr(u8 *mac_addr);
|
||||
int i40e_get_link_status(struct i40e_hw *hw, bool *link_up);
|
||||
int i40e_update_link_info(struct i40e_hw *hw);
|
||||
int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
|
||||
int i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
|
||||
u32 *max_bw, u32 *min_bw, bool *min_valid,
|
||||
bool *max_valid);
|
||||
int
|
||||
i40e_aq_configure_partition_bw(struct i40e_hw *hw,
|
||||
struct i40e_aqc_configure_partition_bw_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
|
||||
int i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
|
||||
u32 pba_num_size);
|
||||
int i40e_validate_mac_addr(u8 *mac_addr);
|
||||
void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable);
|
||||
/* prototype for functions used for NVM access */
|
||||
i40e_status i40e_init_nvm(struct i40e_hw *hw);
|
||||
i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
|
||||
enum i40e_aq_resource_access_type access);
|
||||
int i40e_init_nvm(struct i40e_hw *hw);
|
||||
int i40e_acquire_nvm(struct i40e_hw *hw,
|
||||
enum i40e_aq_resource_access_type access);
|
||||
void i40e_release_nvm(struct i40e_hw *hw);
|
||||
i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data);
|
||||
enum i40e_status_code i40e_read_nvm_module_data(struct i40e_hw *hw,
|
||||
u8 module_ptr,
|
||||
u16 module_offset,
|
||||
u16 data_offset,
|
||||
u16 words_data_size,
|
||||
u16 *data_ptr);
|
||||
i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data);
|
||||
i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw);
|
||||
i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum);
|
||||
i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *);
|
||||
int i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data);
|
||||
int i40e_read_nvm_module_data(struct i40e_hw *hw,
|
||||
u8 module_ptr,
|
||||
u16 module_offset,
|
||||
u16 data_offset,
|
||||
u16 words_data_size,
|
||||
u16 *data_ptr);
|
||||
int i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data);
|
||||
int i40e_update_nvm_checksum(struct i40e_hw *hw);
|
||||
int i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum);
|
||||
int i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode,
|
||||
struct i40e_aq_desc *desc);
|
||||
void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw);
|
||||
void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status);
|
||||
|
||||
i40e_status i40e_set_mac_type(struct i40e_hw *hw);
|
||||
int i40e_set_mac_type(struct i40e_hw *hw);
|
||||
|
||||
extern struct i40e_rx_ptype_decoded i40e_ptype_lookup[];
|
||||
|
||||
@ -422,41 +427,41 @@ i40e_virtchnl_link_speed(enum i40e_aq_link_speed link_speed)
|
||||
/* i40e_common for VF drivers*/
|
||||
void i40e_vf_parse_hw_config(struct i40e_hw *hw,
|
||||
struct virtchnl_vf_resource *msg);
|
||||
i40e_status i40e_vf_reset(struct i40e_hw *hw);
|
||||
i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
|
||||
enum virtchnl_ops v_opcode,
|
||||
i40e_status v_retval,
|
||||
u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_set_filter_control(struct i40e_hw *hw,
|
||||
struct i40e_filter_control_settings *settings);
|
||||
i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
|
||||
u8 *mac_addr, u16 ethtype, u16 flags,
|
||||
u16 vsi_seid, u16 queue, bool is_add,
|
||||
struct i40e_control_filter_stats *stats,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
|
||||
u8 table_id, u32 start_index, u16 buff_size,
|
||||
void *buff, u16 *ret_buff_size,
|
||||
u8 *ret_next_table, u32 *ret_next_index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_vf_reset(struct i40e_hw *hw);
|
||||
int i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
|
||||
enum virtchnl_ops v_opcode,
|
||||
int v_retval,
|
||||
u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_set_filter_control(struct i40e_hw *hw,
|
||||
struct i40e_filter_control_settings *settings);
|
||||
int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
|
||||
u8 *mac_addr, u16 ethtype, u16 flags,
|
||||
u16 vsi_seid, u16 queue, bool is_add,
|
||||
struct i40e_control_filter_stats *stats,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
|
||||
u8 table_id, u32 start_index, u16 buff_size,
|
||||
void *buff, u16 *ret_buff_size,
|
||||
u8 *ret_next_table, u32 *ret_next_index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
|
||||
u16 vsi_seid);
|
||||
i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 *reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 *reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
|
||||
i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
|
||||
u8 phy_select, u8 dev_addr, bool page_change,
|
||||
bool set_mdio, u8 mdio_num,
|
||||
u32 reg_addr, u32 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
|
||||
u8 phy_select, u8 dev_addr, bool page_change,
|
||||
bool set_mdio, u8 mdio_num,
|
||||
@ -469,43 +474,43 @@ i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
|
||||
#define i40e_aq_get_phy_register(hw, ps, da, pc, ra, rv, cd) \
|
||||
i40e_aq_get_phy_register_ext(hw, ps, da, pc, false, 0, ra, rv, cd)
|
||||
|
||||
i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
|
||||
u16 reg, u8 phy_addr, u16 *value);
|
||||
i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
|
||||
u16 reg, u8 phy_addr, u16 value);
|
||||
i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
|
||||
u8 page, u16 reg, u8 phy_addr, u16 *value);
|
||||
i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
|
||||
u8 page, u16 reg, u8 phy_addr, u16 value);
|
||||
i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
|
||||
u8 phy_addr, u16 *value);
|
||||
i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
|
||||
u8 phy_addr, u16 value);
|
||||
int i40e_read_phy_register_clause22(struct i40e_hw *hw,
|
||||
u16 reg, u8 phy_addr, u16 *value);
|
||||
int i40e_write_phy_register_clause22(struct i40e_hw *hw,
|
||||
u16 reg, u8 phy_addr, u16 value);
|
||||
int i40e_read_phy_register_clause45(struct i40e_hw *hw,
|
||||
u8 page, u16 reg, u8 phy_addr, u16 *value);
|
||||
int i40e_write_phy_register_clause45(struct i40e_hw *hw,
|
||||
u8 page, u16 reg, u8 phy_addr, u16 value);
|
||||
int i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
|
||||
u8 phy_addr, u16 *value);
|
||||
int i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
|
||||
u8 phy_addr, u16 value);
|
||||
u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);
|
||||
i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
|
||||
u32 time, u32 interval);
|
||||
i40e_status i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
|
||||
u16 buff_size, u32 track_id,
|
||||
u32 *error_offset, u32 *error_info,
|
||||
struct i40e_asq_cmd_details *
|
||||
cmd_details);
|
||||
i40e_status i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
|
||||
u16 buff_size, u8 flags,
|
||||
struct i40e_asq_cmd_details *
|
||||
cmd_details);
|
||||
int i40e_blink_phy_link_led(struct i40e_hw *hw,
|
||||
u32 time, u32 interval);
|
||||
int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
|
||||
u16 buff_size, u32 track_id,
|
||||
u32 *error_offset, u32 *error_info,
|
||||
struct i40e_asq_cmd_details *
|
||||
cmd_details);
|
||||
int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
|
||||
u16 buff_size, u8 flags,
|
||||
struct i40e_asq_cmd_details *
|
||||
cmd_details);
|
||||
struct i40e_generic_seg_header *
|
||||
i40e_find_segment_in_package(u32 segment_type,
|
||||
struct i40e_package_header *pkg_header);
|
||||
struct i40e_profile_section_header *
|
||||
i40e_find_section_in_profile(u32 section_type,
|
||||
struct i40e_profile_segment *profile);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *i40e_seg,
|
||||
u32 track_id);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *i40e_seg,
|
||||
u32 track_id);
|
||||
enum i40e_status_code
|
||||
int
|
||||
i40e_add_pinfo_to_list(struct i40e_hw *hw,
|
||||
struct i40e_profile_segment *profile,
|
||||
u8 *profile_info_sec, u32 track_id);
|
||||
|
@ -9,65 +9,30 @@ enum i40e_status_code {
|
||||
I40E_SUCCESS = 0,
|
||||
I40E_ERR_NVM = -1,
|
||||
I40E_ERR_NVM_CHECKSUM = -2,
|
||||
I40E_ERR_PHY = -3,
|
||||
I40E_ERR_CONFIG = -4,
|
||||
I40E_ERR_PARAM = -5,
|
||||
I40E_ERR_MAC_TYPE = -6,
|
||||
I40E_ERR_UNKNOWN_PHY = -7,
|
||||
I40E_ERR_LINK_SETUP = -8,
|
||||
I40E_ERR_ADAPTER_STOPPED = -9,
|
||||
I40E_ERR_INVALID_MAC_ADDR = -10,
|
||||
I40E_ERR_DEVICE_NOT_SUPPORTED = -11,
|
||||
I40E_ERR_PRIMARY_REQUESTS_PENDING = -12,
|
||||
I40E_ERR_INVALID_LINK_SETTINGS = -13,
|
||||
I40E_ERR_AUTONEG_NOT_COMPLETE = -14,
|
||||
I40E_ERR_RESET_FAILED = -15,
|
||||
I40E_ERR_SWFW_SYNC = -16,
|
||||
I40E_ERR_NO_AVAILABLE_VSI = -17,
|
||||
I40E_ERR_NO_MEMORY = -18,
|
||||
I40E_ERR_BAD_PTR = -19,
|
||||
I40E_ERR_RING_FULL = -20,
|
||||
I40E_ERR_INVALID_PD_ID = -21,
|
||||
I40E_ERR_INVALID_QP_ID = -22,
|
||||
I40E_ERR_INVALID_CQ_ID = -23,
|
||||
I40E_ERR_INVALID_CEQ_ID = -24,
|
||||
I40E_ERR_INVALID_AEQ_ID = -25,
|
||||
I40E_ERR_INVALID_SIZE = -26,
|
||||
I40E_ERR_INVALID_ARP_INDEX = -27,
|
||||
I40E_ERR_INVALID_FPM_FUNC_ID = -28,
|
||||
I40E_ERR_QP_INVALID_MSG_SIZE = -29,
|
||||
I40E_ERR_QP_TOOMANY_WRS_POSTED = -30,
|
||||
I40E_ERR_INVALID_FRAG_COUNT = -31,
|
||||
I40E_ERR_QUEUE_EMPTY = -32,
|
||||
I40E_ERR_INVALID_ALIGNMENT = -33,
|
||||
I40E_ERR_FLUSHED_QUEUE = -34,
|
||||
I40E_ERR_INVALID_PUSH_PAGE_INDEX = -35,
|
||||
I40E_ERR_INVALID_IMM_DATA_SIZE = -36,
|
||||
I40E_ERR_TIMEOUT = -37,
|
||||
I40E_ERR_OPCODE_MISMATCH = -38,
|
||||
I40E_ERR_CQP_COMPL_ERROR = -39,
|
||||
I40E_ERR_INVALID_VF_ID = -40,
|
||||
I40E_ERR_INVALID_HMCFN_ID = -41,
|
||||
I40E_ERR_BACKING_PAGE_ERROR = -42,
|
||||
I40E_ERR_NO_PBLCHUNKS_AVAILABLE = -43,
|
||||
I40E_ERR_INVALID_PBLE_INDEX = -44,
|
||||
I40E_ERR_INVALID_SD_INDEX = -45,
|
||||
I40E_ERR_INVALID_PAGE_DESC_INDEX = -46,
|
||||
I40E_ERR_INVALID_SD_TYPE = -47,
|
||||
I40E_ERR_MEMCPY_FAILED = -48,
|
||||
I40E_ERR_INVALID_HMC_OBJ_INDEX = -49,
|
||||
I40E_ERR_INVALID_HMC_OBJ_COUNT = -50,
|
||||
I40E_ERR_INVALID_SRQ_ARM_LIMIT = -51,
|
||||
I40E_ERR_SRQ_ENABLED = -52,
|
||||
I40E_ERR_ADMIN_QUEUE_ERROR = -53,
|
||||
I40E_ERR_ADMIN_QUEUE_TIMEOUT = -54,
|
||||
I40E_ERR_BUF_TOO_SHORT = -55,
|
||||
I40E_ERR_ADMIN_QUEUE_FULL = -56,
|
||||
I40E_ERR_ADMIN_QUEUE_NO_WORK = -57,
|
||||
I40E_ERR_BAD_IWARP_CQE = -58,
|
||||
I40E_ERR_NVM_BLANK_MODE = -59,
|
||||
I40E_ERR_NOT_IMPLEMENTED = -60,
|
||||
I40E_ERR_PE_DOORBELL_NOT_ENABLED = -61,
|
||||
I40E_ERR_DIAG_TEST_FAILED = -62,
|
||||
I40E_ERR_NOT_READY = -63,
|
||||
I40E_NOT_SUPPORTED = -64,
|
||||
|
@ -17,7 +17,7 @@
|
||||
**/
|
||||
static void i40e_vc_vf_broadcast(struct i40e_pf *pf,
|
||||
enum virtchnl_ops v_opcode,
|
||||
i40e_status v_retval, u8 *msg,
|
||||
int v_retval, u8 *msg,
|
||||
u16 msglen)
|
||||
{
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
@ -1247,13 +1247,13 @@ static void i40e_get_vlan_list_sync(struct i40e_vsi *vsi, u16 *num_vlans,
|
||||
* @vl: List of VLANs - apply filter for given VLANs
|
||||
* @num_vlans: Number of elements in @vl
|
||||
**/
|
||||
static i40e_status
|
||||
static int
|
||||
i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
|
||||
bool unicast_enable, s16 *vl, u16 num_vlans)
|
||||
{
|
||||
i40e_status aq_ret, aq_tmp = 0;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
int aq_ret, aq_tmp = 0;
|
||||
int i;
|
||||
|
||||
/* No VLAN to set promisc on, set on VSI */
|
||||
@ -1265,9 +1265,9 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
|
||||
int aq_err = pf->hw.aq.asq_last_status;
|
||||
|
||||
dev_err(&pf->pdev->dev,
|
||||
"VF %d failed to set multicast promiscuous mode err %s aq_err %s\n",
|
||||
"VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n",
|
||||
vf->vf_id,
|
||||
i40e_stat_str(&pf->hw, aq_ret),
|
||||
ERR_PTR(aq_ret),
|
||||
i40e_aq_str(&pf->hw, aq_err));
|
||||
|
||||
return aq_ret;
|
||||
@ -1281,9 +1281,9 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
|
||||
int aq_err = pf->hw.aq.asq_last_status;
|
||||
|
||||
dev_err(&pf->pdev->dev,
|
||||
"VF %d failed to set unicast promiscuous mode err %s aq_err %s\n",
|
||||
"VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n",
|
||||
vf->vf_id,
|
||||
i40e_stat_str(&pf->hw, aq_ret),
|
||||
ERR_PTR(aq_ret),
|
||||
i40e_aq_str(&pf->hw, aq_err));
|
||||
}
|
||||
|
||||
@ -1298,9 +1298,9 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
|
||||
int aq_err = pf->hw.aq.asq_last_status;
|
||||
|
||||
dev_err(&pf->pdev->dev,
|
||||
"VF %d failed to set multicast promiscuous mode err %s aq_err %s\n",
|
||||
"VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n",
|
||||
vf->vf_id,
|
||||
i40e_stat_str(&pf->hw, aq_ret),
|
||||
ERR_PTR(aq_ret),
|
||||
i40e_aq_str(&pf->hw, aq_err));
|
||||
|
||||
if (!aq_tmp)
|
||||
@ -1314,9 +1314,9 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
|
||||
int aq_err = pf->hw.aq.asq_last_status;
|
||||
|
||||
dev_err(&pf->pdev->dev,
|
||||
"VF %d failed to set unicast promiscuous mode err %s aq_err %s\n",
|
||||
"VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n",
|
||||
vf->vf_id,
|
||||
i40e_stat_str(&pf->hw, aq_ret),
|
||||
ERR_PTR(aq_ret),
|
||||
i40e_aq_str(&pf->hw, aq_err));
|
||||
|
||||
if (!aq_tmp)
|
||||
@ -1340,13 +1340,13 @@ i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
|
||||
* Called from the VF to configure the promiscuous mode of
|
||||
* VF vsis and from the VF reset path to reset promiscuous mode.
|
||||
**/
|
||||
static i40e_status i40e_config_vf_promiscuous_mode(struct i40e_vf *vf,
|
||||
u16 vsi_id,
|
||||
bool allmulti,
|
||||
bool alluni)
|
||||
static int i40e_config_vf_promiscuous_mode(struct i40e_vf *vf,
|
||||
u16 vsi_id,
|
||||
bool allmulti,
|
||||
bool alluni)
|
||||
{
|
||||
i40e_status aq_ret = I40E_SUCCESS;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
int aq_ret = I40E_SUCCESS;
|
||||
struct i40e_vsi *vsi;
|
||||
u16 num_vlans;
|
||||
s16 *vl;
|
||||
@ -1956,7 +1956,7 @@ static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode,
|
||||
struct i40e_pf *pf;
|
||||
struct i40e_hw *hw;
|
||||
int abs_vf_id;
|
||||
i40e_status aq_ret;
|
||||
int aq_ret;
|
||||
|
||||
/* validate the request */
|
||||
if (!vf || vf->vf_id >= vf->pf->num_alloc_vfs)
|
||||
@ -1988,7 +1988,7 @@ static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode,
|
||||
**/
|
||||
static int i40e_vc_send_resp_to_vf(struct i40e_vf *vf,
|
||||
enum virtchnl_ops opcode,
|
||||
i40e_status retval)
|
||||
int retval)
|
||||
{
|
||||
return i40e_vc_send_msg_to_vf(vf, opcode, retval, NULL, 0);
|
||||
}
|
||||
@ -2092,9 +2092,9 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
|
||||
{
|
||||
struct virtchnl_vf_resource *vfres = NULL;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
i40e_status aq_ret = 0;
|
||||
struct i40e_vsi *vsi;
|
||||
int num_vsis = 1;
|
||||
int aq_ret = 0;
|
||||
size_t len = 0;
|
||||
int ret;
|
||||
|
||||
@ -2222,9 +2222,9 @@ static int i40e_vc_config_promiscuous_mode_msg(struct i40e_vf *vf, u8 *msg)
|
||||
struct virtchnl_promisc_info *info =
|
||||
(struct virtchnl_promisc_info *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
i40e_status aq_ret = 0;
|
||||
bool allmulti = false;
|
||||
bool alluni = false;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
aq_ret = I40E_ERR_PARAM;
|
||||
@ -2309,10 +2309,10 @@ static int i40e_vc_config_queues_msg(struct i40e_vf *vf, u8 *msg)
|
||||
struct virtchnl_queue_pair_info *qpi;
|
||||
u16 vsi_id, vsi_queue_id = 0;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
i40e_status aq_ret = 0;
|
||||
int i, j = 0, idx = 0;
|
||||
struct i40e_vsi *vsi;
|
||||
u16 num_qps_all = 0;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
aq_ret = I40E_ERR_PARAM;
|
||||
@ -2459,8 +2459,8 @@ static int i40e_vc_config_irq_map_msg(struct i40e_vf *vf, u8 *msg)
|
||||
struct virtchnl_irq_map_info *irqmap_info =
|
||||
(struct virtchnl_irq_map_info *)msg;
|
||||
struct virtchnl_vector_map *map;
|
||||
int aq_ret = 0;
|
||||
u16 vsi_id;
|
||||
i40e_status aq_ret = 0;
|
||||
int i;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
@ -2575,7 +2575,7 @@ static int i40e_vc_enable_queues_msg(struct i40e_vf *vf, u8 *msg)
|
||||
struct virtchnl_queue_select *vqs =
|
||||
(struct virtchnl_queue_select *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
int i;
|
||||
|
||||
if (!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states)) {
|
||||
@ -2633,7 +2633,7 @@ static int i40e_vc_disable_queues_msg(struct i40e_vf *vf, u8 *msg)
|
||||
struct virtchnl_queue_select *vqs =
|
||||
(struct virtchnl_queue_select *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
aq_ret = I40E_ERR_PARAM;
|
||||
@ -2784,7 +2784,7 @@ static int i40e_vc_get_stats_msg(struct i40e_vf *vf, u8 *msg)
|
||||
(struct virtchnl_queue_select *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_eth_stats stats;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
struct i40e_vsi *vsi;
|
||||
|
||||
memset(&stats, 0, sizeof(struct i40e_eth_stats));
|
||||
@ -2927,7 +2927,7 @@ static int i40e_vc_add_mac_addr_msg(struct i40e_vf *vf, u8 *msg)
|
||||
(struct virtchnl_ether_addr_list *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
i40e_status ret = 0;
|
||||
int ret = 0;
|
||||
int i;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
|
||||
@ -2999,7 +2999,7 @@ static int i40e_vc_del_mac_addr_msg(struct i40e_vf *vf, u8 *msg)
|
||||
bool was_unimac_deleted = false;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
i40e_status ret = 0;
|
||||
int ret = 0;
|
||||
int i;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
|
||||
@ -3072,7 +3072,7 @@ static int i40e_vc_add_vlan_msg(struct i40e_vf *vf, u8 *msg)
|
||||
(struct virtchnl_vlan_filter_list *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
int i;
|
||||
|
||||
if ((vf->num_vlan >= I40E_VC_MAX_VLAN_PER_VF) &&
|
||||
@ -3143,7 +3143,7 @@ static int i40e_vc_remove_vlan_msg(struct i40e_vf *vf, u8 *msg)
|
||||
(struct virtchnl_vlan_filter_list *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
int i;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
|
||||
@ -3199,7 +3199,7 @@ static int i40e_vc_rdma_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
|
||||
{
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
int abs_vf_id = vf->vf_id + pf->hw.func_caps.vf_base_id;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states) ||
|
||||
!test_bit(I40E_VF_STATE_RDMAENA, &vf->vf_states)) {
|
||||
@ -3228,7 +3228,7 @@ static int i40e_vc_rdma_qvmap_msg(struct i40e_vf *vf, u8 *msg, bool config)
|
||||
{
|
||||
struct virtchnl_rdma_qvlist_info *qvlist_info =
|
||||
(struct virtchnl_rdma_qvlist_info *)msg;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states) ||
|
||||
!test_bit(I40E_VF_STATE_RDMAENA, &vf->vf_states)) {
|
||||
@ -3264,7 +3264,7 @@ static int i40e_vc_config_rss_key(struct i40e_vf *vf, u8 *msg)
|
||||
(struct virtchnl_rss_key *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
|
||||
!i40e_vc_isvalid_vsi_id(vf, vrk->vsi_id) ||
|
||||
@ -3294,7 +3294,7 @@ static int i40e_vc_config_rss_lut(struct i40e_vf *vf, u8 *msg)
|
||||
(struct virtchnl_rss_lut *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
u16 i;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
|
||||
@ -3329,7 +3329,7 @@ static int i40e_vc_get_rss_hena(struct i40e_vf *vf, u8 *msg)
|
||||
{
|
||||
struct virtchnl_rss_hena *vrh = NULL;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
int len = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
@ -3366,7 +3366,7 @@ static int i40e_vc_set_rss_hena(struct i40e_vf *vf, u8 *msg)
|
||||
(struct virtchnl_rss_hena *)msg;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
aq_ret = I40E_ERR_PARAM;
|
||||
@ -3390,8 +3390,8 @@ static int i40e_vc_set_rss_hena(struct i40e_vf *vf, u8 *msg)
|
||||
**/
|
||||
static int i40e_vc_enable_vlan_stripping(struct i40e_vf *vf, u8 *msg)
|
||||
{
|
||||
i40e_status aq_ret = 0;
|
||||
struct i40e_vsi *vsi;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
aq_ret = I40E_ERR_PARAM;
|
||||
@ -3416,8 +3416,8 @@ static int i40e_vc_enable_vlan_stripping(struct i40e_vf *vf, u8 *msg)
|
||||
**/
|
||||
static int i40e_vc_disable_vlan_stripping(struct i40e_vf *vf, u8 *msg)
|
||||
{
|
||||
i40e_status aq_ret = 0;
|
||||
struct i40e_vsi *vsi;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
aq_ret = I40E_ERR_PARAM;
|
||||
@ -3616,8 +3616,8 @@ static void i40e_del_all_cloud_filters(struct i40e_vf *vf)
|
||||
ret = i40e_add_del_cloud_filter(vsi, cfilter, false);
|
||||
if (ret)
|
||||
dev_err(&pf->pdev->dev,
|
||||
"VF %d: Failed to delete cloud filter, err %s aq_err %s\n",
|
||||
vf->vf_id, i40e_stat_str(&pf->hw, ret),
|
||||
"VF %d: Failed to delete cloud filter, err %pe aq_err %s\n",
|
||||
vf->vf_id, ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw,
|
||||
pf->hw.aq.asq_last_status));
|
||||
|
||||
@ -3643,7 +3643,7 @@ static int i40e_vc_del_cloud_filter(struct i40e_vf *vf, u8 *msg)
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
struct hlist_node *node;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
int i, ret;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
@ -3719,8 +3719,8 @@ static int i40e_vc_del_cloud_filter(struct i40e_vf *vf, u8 *msg)
|
||||
ret = i40e_add_del_cloud_filter(vsi, &cfilter, false);
|
||||
if (ret) {
|
||||
dev_err(&pf->pdev->dev,
|
||||
"VF %d: Failed to delete cloud filter, err %s aq_err %s\n",
|
||||
vf->vf_id, i40e_stat_str(&pf->hw, ret),
|
||||
"VF %d: Failed to delete cloud filter, err %pe aq_err %s\n",
|
||||
vf->vf_id, ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
|
||||
goto err;
|
||||
}
|
||||
@ -3774,7 +3774,7 @@ static int i40e_vc_add_cloud_filter(struct i40e_vf *vf, u8 *msg)
|
||||
struct i40e_cloud_filter *cfilter = NULL;
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_vsi *vsi = NULL;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
int i, ret;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
@ -3853,8 +3853,8 @@ static int i40e_vc_add_cloud_filter(struct i40e_vf *vf, u8 *msg)
|
||||
ret = i40e_add_del_cloud_filter(vsi, cfilter, true);
|
||||
if (ret) {
|
||||
dev_err(&pf->pdev->dev,
|
||||
"VF %d: Failed to add cloud filter, err %s aq_err %s\n",
|
||||
vf->vf_id, i40e_stat_str(&pf->hw, ret),
|
||||
"VF %d: Failed to add cloud filter, err %pe aq_err %s\n",
|
||||
vf->vf_id, ERR_PTR(ret),
|
||||
i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
|
||||
goto err_free;
|
||||
}
|
||||
@ -3883,7 +3883,7 @@ static int i40e_vc_add_qch_msg(struct i40e_vf *vf, u8 *msg)
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
struct i40e_link_status *ls = &pf->hw.phy.link_info;
|
||||
int i, adq_request_qps = 0;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
u64 speed = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
@ -3995,7 +3995,7 @@ static int i40e_vc_add_qch_msg(struct i40e_vf *vf, u8 *msg)
|
||||
static int i40e_vc_del_qch_msg(struct i40e_vf *vf, u8 *msg)
|
||||
{
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
i40e_status aq_ret = 0;
|
||||
int aq_ret = 0;
|
||||
|
||||
if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
|
||||
aq_ret = I40E_ERR_PARAM;
|
||||
|
Loading…
Reference in New Issue
Block a user