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soundwire: amd: refactor existing code for acp 6.3 platform
Refactor existing code by adding acp pci revision id coditional checks for ACP 6.3 platform. Rename the macros and structure names with ACP63 tag. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Link: https://lore.kernel.org/r/20240924081846.1834612-3-Vijendar.Mukunda@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Vijendar Mukunda
Vinod Koul
parent
ced20ea315
commit
7b54323dde
@ -433,12 +433,18 @@ static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_pa
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u32 frame_fmt_reg, dpn_frame_fmt;
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dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num);
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switch (amd_manager->instance) {
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case ACP_SDW0:
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frame_fmt_reg = sdw0_manager_dp_reg[p_params->num].frame_fmt_reg;
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break;
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case ACP_SDW1:
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frame_fmt_reg = sdw1_manager_dp_reg[p_params->num].frame_fmt_reg;
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switch (amd_manager->acp_rev) {
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case ACP63_PCI_REV_ID:
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switch (amd_manager->instance) {
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case ACP_SDW0:
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frame_fmt_reg = acp63_sdw0_dp_reg[p_params->num].frame_fmt_reg;
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break;
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case ACP_SDW1:
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frame_fmt_reg = acp63_sdw1_dp_reg[p_params->num].frame_fmt_reg;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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@ -465,20 +471,28 @@ static int amd_sdw_transport_params(struct sdw_bus *bus,
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u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg;
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u32 offset_reg, lane_ctrl_ch_en_reg;
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switch (amd_manager->instance) {
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case ACP_SDW0:
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frame_fmt_reg = sdw0_manager_dp_reg[params->port_num].frame_fmt_reg;
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sample_int_reg = sdw0_manager_dp_reg[params->port_num].sample_int_reg;
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hctrl_dp0_reg = sdw0_manager_dp_reg[params->port_num].hctrl_dp0_reg;
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offset_reg = sdw0_manager_dp_reg[params->port_num].offset_reg;
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lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
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break;
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case ACP_SDW1:
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frame_fmt_reg = sdw1_manager_dp_reg[params->port_num].frame_fmt_reg;
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sample_int_reg = sdw1_manager_dp_reg[params->port_num].sample_int_reg;
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hctrl_dp0_reg = sdw1_manager_dp_reg[params->port_num].hctrl_dp0_reg;
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offset_reg = sdw1_manager_dp_reg[params->port_num].offset_reg;
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lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
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switch (amd_manager->acp_rev) {
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case ACP63_PCI_REV_ID:
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switch (amd_manager->instance) {
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case ACP_SDW0:
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frame_fmt_reg = acp63_sdw0_dp_reg[params->port_num].frame_fmt_reg;
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sample_int_reg = acp63_sdw0_dp_reg[params->port_num].sample_int_reg;
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hctrl_dp0_reg = acp63_sdw0_dp_reg[params->port_num].hctrl_dp0_reg;
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offset_reg = acp63_sdw0_dp_reg[params->port_num].offset_reg;
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lane_ctrl_ch_en_reg =
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acp63_sdw0_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
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break;
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case ACP_SDW1:
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frame_fmt_reg = acp63_sdw1_dp_reg[params->port_num].frame_fmt_reg;
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sample_int_reg = acp63_sdw1_dp_reg[params->port_num].sample_int_reg;
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hctrl_dp0_reg = acp63_sdw1_dp_reg[params->port_num].hctrl_dp0_reg;
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offset_reg = acp63_sdw1_dp_reg[params->port_num].offset_reg;
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lane_ctrl_ch_en_reg =
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acp63_sdw1_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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@ -520,12 +534,20 @@ static int amd_sdw_port_enable(struct sdw_bus *bus,
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u32 dpn_ch_enable;
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u32 lane_ctrl_ch_en_reg;
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switch (amd_manager->instance) {
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case ACP_SDW0:
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lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
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break;
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case ACP_SDW1:
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lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
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switch (amd_manager->acp_rev) {
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case ACP63_PCI_REV_ID:
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switch (amd_manager->instance) {
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case ACP_SDW0:
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lane_ctrl_ch_en_reg =
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acp63_sdw0_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
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break;
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case ACP_SDW1:
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lane_ctrl_ch_en_reg =
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acp63_sdw1_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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@ -927,15 +949,21 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
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* information.
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*/
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amd_manager->bus.controller_id = 0;
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switch (amd_manager->instance) {
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case ACP_SDW0:
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amd_manager->num_dout_ports = AMD_SDW0_MAX_TX_PORTS;
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amd_manager->num_din_ports = AMD_SDW0_MAX_RX_PORTS;
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break;
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case ACP_SDW1:
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amd_manager->num_dout_ports = AMD_SDW1_MAX_TX_PORTS;
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amd_manager->num_din_ports = AMD_SDW1_MAX_RX_PORTS;
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dev_dbg(dev, "acp_rev:0x%x\n", amd_manager->acp_rev);
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switch (amd_manager->acp_rev) {
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case ACP63_PCI_REV_ID:
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switch (amd_manager->instance) {
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case ACP_SDW0:
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amd_manager->num_dout_ports = AMD_ACP63_SDW0_MAX_TX_PORTS;
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amd_manager->num_din_ports = AMD_ACP63_SDW0_MAX_RX_PORTS;
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break;
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case ACP_SDW1:
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amd_manager->num_dout_ports = AMD_ACP63_SDW1_MAX_TX_PORTS;
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amd_manager->num_din_ports = AMD_ACP63_SDW1_MAX_RX_PORTS;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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@ -155,12 +155,12 @@
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#define AMD_SDW_IRQ_MASK_8TO11 0x000c7777
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#define AMD_SDW_IRQ_ERROR_MASK 0xff
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#define AMD_SDW_MAX_FREQ_NUM 1
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#define AMD_SDW0_MAX_TX_PORTS 3
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#define AMD_SDW0_MAX_RX_PORTS 3
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#define AMD_SDW1_MAX_TX_PORTS 1
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#define AMD_SDW1_MAX_RX_PORTS 1
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#define AMD_SDW0_MAX_DAI 6
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#define AMD_SDW1_MAX_DAI 2
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#define AMD_ACP63_SDW0_MAX_TX_PORTS 3
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#define AMD_ACP63_SDW0_MAX_RX_PORTS 3
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#define AMD_ACP63_SDW1_MAX_TX_PORTS 1
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#define AMD_ACP63_SDW1_MAX_RX_PORTS 1
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#define AMD_ACP63_SDW0_MAX_DAI 6
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#define AMD_ACP63_SDW1_MAX_DAI 2
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#define AMD_SDW_SLAVE_0_ATTACHED 5
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#define AMD_SDW_SSP_COUNTER_VAL 3
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@ -222,7 +222,7 @@ struct sdw_manager_dp_reg {
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* in SoundWire DMA driver.
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*/
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static struct sdw_manager_dp_reg sdw0_manager_dp_reg[AMD_SDW0_MAX_DAI] = {
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static struct sdw_manager_dp_reg acp63_sdw0_dp_reg[AMD_ACP63_SDW0_MAX_DAI] = {
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{ACP_SW_AUDIO0_TX_FRAME_FORMAT, ACP_SW_AUDIO0_TX_SAMPLEINTERVAL, ACP_SW_AUDIO0_TX_HCTRL_DP0,
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ACP_SW_AUDIO0_TX_OFFSET_DP0, ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0},
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{ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,
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@ -237,7 +237,7 @@ static struct sdw_manager_dp_reg sdw0_manager_dp_reg[AMD_SDW0_MAX_DAI] = {
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ACP_SW_AUDIO2_RX_OFFSET, ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0},
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};
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static struct sdw_manager_dp_reg sdw1_manager_dp_reg[AMD_SDW1_MAX_DAI] = {
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static struct sdw_manager_dp_reg acp63_sdw1_dp_reg[AMD_ACP63_SDW1_MAX_DAI] = {
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{ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,
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ACP_SW_AUDIO1_TX_OFFSET, ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0},
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{ACP_SW_AUDIO1_RX_FRAME_FORMAT, ACP_SW_AUDIO1_RX_SAMPLEINTERVAL, ACP_SW_AUDIO1_RX_HCTRL,
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@ -27,6 +27,7 @@
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#define ACP_SDW0 0
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#define ACP_SDW1 1
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#define AMD_SDW_MAX_MANAGER_COUNT 2
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#define ACP63_PCI_REV_ID 0x63
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struct acp_sdw_pdata {
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u16 instance;
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