mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-01-09 14:43:16 +00:00
perf tools changes for v5.18: 1st batch
New features:
perf ftrace:
- Add -n/--use-nsec option to the 'latency' subcommand.
Default: usecs:
$ sudo perf ftrace latency -T dput -a sleep 1
# DURATION | COUNT | GRAPH |
0 - 1 us | 2098375 | ############################# |
1 - 2 us | 61 | |
2 - 4 us | 33 | |
4 - 8 us | 13 | |
8 - 16 us | 124 | |
16 - 32 us | 123 | |
32 - 64 us | 1 | |
64 - 128 us | 0 | |
128 - 256 us | 1 | |
256 - 512 us | 0 | |
Better granularity with nsec:
$ sudo perf ftrace latency -T dput -a -n sleep 1
# DURATION | COUNT | GRAPH |
0 - 1 us | 0 | |
1 - 2 ns | 0 | |
2 - 4 ns | 0 | |
4 - 8 ns | 0 | |
8 - 16 ns | 0 | |
16 - 32 ns | 0 | |
32 - 64 ns | 0 | |
64 - 128 ns | 1163434 | ############## |
128 - 256 ns | 914102 | ############# |
256 - 512 ns | 884 | |
512 - 1024 ns | 613 | |
1 - 2 us | 31 | |
2 - 4 us | 17 | |
4 - 8 us | 7 | |
8 - 16 us | 123 | |
16 - 32 us | 83 | |
perf lock:
- Add -c/--combine-locks option to merge lock instances in the same class into
a single entry.
# perf lock report -c
Name acquired contended avg wait(ns) total wait(ns) max wait(ns) min wait(ns)
rcu_read_lock 251225 0 0 0 0 0
hrtimer_bases.lock 39450 0 0 0 0 0
&sb->s_type->i_l... 10301 1 662 662 662 662
ptlock_ptr(page) 10173 2 701 1402 760 642
&(ei->i_block_re... 8732 0 0 0 0 0
&xa->xa_lock 8088 0 0 0 0 0
&base->lock 6705 0 0 0 0 0
&p->pi_lock 5549 0 0 0 0 0
&dentry->d_lockr... 5010 4 1274 5097 1844 789
&ep->lock 3958 0 0 0 0 0
- Add -F/--field option to customize the list of fields to output:
$ perf lock report -F contended,wait_max -k avg_wait
Name contended max wait(ns) avg wait(ns)
slock-AF_INET6 1 23543 23543
&lruvec->lru_lock 5 18317 11254
slock-AF_INET6 1 10379 10379
rcu_node_1 1 2104 2104
&dentry->d_lockr... 1 1844 1844
&dentry->d_lockr... 1 1672 1672
&newf->file_lock 15 2279 1025
&dentry->d_lockr... 1 792 792
- Add --synth=no option for record, as there is no need to symbolize,
lock names comes from the tracepoints.
perf record:
- Threaded recording, opt-in, via the new --threads command line option.
- Improve AMD IBS (Instruction-Based Sampling) error handling messages.
perf script:
- Add 'brstackinsnlen' field (use it with -F) for branch stacks.
- Output branch sample type in 'perf script'.
perf report:
- Add "addr_from" and "addr_to" sort dimensions.
- Print branch stack entry type in 'perf report --dump-raw-trace'
- Fix symbolization for chrooted workloads.
Hardware tracing:
Intel PT:
- Add CFE (Control Flow Event) and EVD (Event Data) packets support.
- Add MODE.Exec IFLAG bit support.
Explanation about these features from the "Intel® 64 and IA-32 architectures
software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C,
3D, and 4" PDF at:
https://cdrdv2.intel.com/v1/dl/getContent/671200
At page 3951:
<quote>
32.2.4
Event Trace is a capability that exposes details about the asynchronous
events, when they are generated, and when their corresponding software
event handler completes execution. These include:
o Interrupts, including NMI and SMI, including the interrupt vector when
defined.
o Faults, exceptions including the fault vector.
— Page faults additionally include the page fault address, when in context.
o Event handler returns, including IRET and RSM.
o VM exits and VM entries.¹
— VM exits include the values written to the “exit reason” and “exit qualification” VMCS fields.
INIT and SIPI events.
o TSX aborts, including the abort status returned for the RTM instructions.
o Shutdown.
Additionally, it provides indication of the status of the Interrupt Flag
(IF), to indicate when interrupts are masked.
</quote>
ARM CoreSight:
- Use advertised caps/min_interval as default sample_period on ARM spe.
- Update deduction of TRCCONFIGR register for branch broadcast on ARM's CoreSight ETM.
Vendor Events (JSON):
Intel:
- Update events and metrics for:
Alderlake, Broadwell, Broadwell DE, BroadwellX, CascadelakeX, Elkhartlake,
Bonnell, Goldmont, GoldmontPlus, Westmere EP-DP, Haswell, HaswellX,
Icelake, IcelakeX, Ivybridge, Ivytown, Jaketown, Knights Landing,
Nehalem EP, Sandybridge, Silvermont, Skylake, Skylake Server, SkylakeX,
Tigerlake, TremontX, Westmere EP-SP, Westmere EX.
ARM:
- Add support for HiSilicon CPA PMU aliasing.
perf stat:
- Fix forked applications enablement of counters.
- The 'slots' should only be printed on a different order than the one specified
on the command line when 'topdown' events are present, fix it.
Miscellaneous:
- Sync msr-index, cpufeatures header files with the kernel sources.
- Stop using some deprecated libbpf APIs in 'perf trace'.
- Fix some spelling mistakes.
- Refactor the maps pointers usage to pave the way for using refcount debugging.
- Only offer the --tui option on perf top, report and annotate when perf was
built with libslang.
- Don't mention --to-ctf in 'perf data --help' when not linking with the required
library, libbabeltrace.
- Use ARRAY_SIZE() instead of ad hoc equivalent, spotted by array_size.cocci.
- Enhance the matching of sub-commands abbreviations:
'perf c2c rec' -> 'perf c2c record'
'perf c2c recport -> error
- Set build-id using build-id header on new mmap records.
- Fix generation of 'perf --version' string.
perf test:
- Add test for the arm_spe event.
- Add test to check unwinding using fame-pointer (fp) mode on arm64.
- Make metric testing more robust in 'perf test'.
- Add error message for unsupported branch stack cases.
libperf:
- Add API for allocating new thread map array.
- Fix typo in perf_evlist__open() failure error messages in libperf tests.
perf c2c:
- Replace bitmap_weight() with bitmap_empty() where appropriate.
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQR2GiIUctdOfX2qHhGyPKLppCJ+JwUCYj8viwAKCRCyPKLppCJ+
J8K3AQDpN45P4/TWJxVWhZlvYzJtWDSboXHZJfmBiEd4Xu2zbwD7BFW02f1ATHPr
dGBFXxRQQufBIqfE+OQXG59Awp1m8wE=
=1l8S
-----END PGP SIGNATURE-----
Merge tag 'perf-tools-for-v5.18-2022-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull perf tools updates from Arnaldo Carvalho de Melo:
"New features:
perf ftrace:
- Add -n/--use-nsec option to the 'latency' subcommand.
Default: usecs:
$ sudo perf ftrace latency -T dput -a sleep 1
# DURATION | COUNT | GRAPH |
0 - 1 us | 2098375 | ############################# |
1 - 2 us | 61 | |
2 - 4 us | 33 | |
4 - 8 us | 13 | |
8 - 16 us | 124 | |
16 - 32 us | 123 | |
32 - 64 us | 1 | |
64 - 128 us | 0 | |
128 - 256 us | 1 | |
256 - 512 us | 0 | |
Better granularity with nsec:
$ sudo perf ftrace latency -T dput -a -n sleep 1
# DURATION | COUNT | GRAPH |
0 - 1 us | 0 | |
1 - 2 ns | 0 | |
2 - 4 ns | 0 | |
4 - 8 ns | 0 | |
8 - 16 ns | 0 | |
16 - 32 ns | 0 | |
32 - 64 ns | 0 | |
64 - 128 ns | 1163434 | ############## |
128 - 256 ns | 914102 | ############# |
256 - 512 ns | 884 | |
512 - 1024 ns | 613 | |
1 - 2 us | 31 | |
2 - 4 us | 17 | |
4 - 8 us | 7 | |
8 - 16 us | 123 | |
16 - 32 us | 83 | |
perf lock:
- Add -c/--combine-locks option to merge lock instances in the same
class into a single entry.
# perf lock report -c
Name acquired contended avg wait(ns) total wait(ns) max wait(ns) min wait(ns)
rcu_read_lock 251225 0 0 0 0 0
hrtimer_bases.lock 39450 0 0 0 0 0
&sb->s_type->i_l... 10301 1 662 662 662 662
ptlock_ptr(page) 10173 2 701 1402 760 642
&(ei->i_block_re... 8732 0 0 0 0 0
&xa->xa_lock 8088 0 0 0 0 0
&base->lock 6705 0 0 0 0 0
&p->pi_lock 5549 0 0 0 0 0
&dentry->d_lockr... 5010 4 1274 5097 1844 789
&ep->lock 3958 0 0 0 0 0
- Add -F/--field option to customize the list of fields to output:
$ perf lock report -F contended,wait_max -k avg_wait
Name contended max wait(ns) avg wait(ns)
slock-AF_INET6 1 23543 23543
&lruvec->lru_lock 5 18317 11254
slock-AF_INET6 1 10379 10379
rcu_node_1 1 2104 2104
&dentry->d_lockr... 1 1844 1844
&dentry->d_lockr... 1 1672 1672
&newf->file_lock 15 2279 1025
&dentry->d_lockr... 1 792 792
- Add --synth=no option for record, as there is no need to symbolize,
lock names comes from the tracepoints.
perf record:
- Threaded recording, opt-in, via the new --threads command line
option.
- Improve AMD IBS (Instruction-Based Sampling) error handling
messages.
perf script:
- Add 'brstackinsnlen' field (use it with -F) for branch stacks.
- Output branch sample type in 'perf script'.
perf report:
- Add "addr_from" and "addr_to" sort dimensions.
- Print branch stack entry type in 'perf report --dump-raw-trace'
- Fix symbolization for chrooted workloads.
Hardware tracing:
Intel PT:
- Add CFE (Control Flow Event) and EVD (Event Data) packets support.
- Add MODE.Exec IFLAG bit support.
Explanation about these features from the "Intel® 64 and IA-32
architectures software developer’s manual combined volumes: 1, 2A,
2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4" PDF at:
https://cdrdv2.intel.com/v1/dl/getContent/671200
At page 3951:
"32.2.4
Event Trace is a capability that exposes details about the
asynchronous events, when they are generated, and when their
corresponding software event handler completes execution. These
include:
o Interrupts, including NMI and SMI, including the interrupt
vector when defined.
o Faults, exceptions including the fault vector.
- Page faults additionally include the page fault address,
when in context.
o Event handler returns, including IRET and RSM.
o VM exits and VM entries.¹
- VM exits include the values written to the “exit reason”
and “exit qualification” VMCS fields. INIT and SIPI events.
o TSX aborts, including the abort status returned for the RTM
instructions.
o Shutdown.
Additionally, it provides indication of the status of the
Interrupt Flag (IF), to indicate when interrupts are masked"
ARM CoreSight:
- Use advertised caps/min_interval as default sample_period on ARM
spe.
- Update deduction of TRCCONFIGR register for branch broadcast on
ARM's CoreSight ETM.
Vendor Events (JSON):
Intel:
- Update events and metrics for: Alderlake, Broadwell, Broadwell DE,
BroadwellX, CascadelakeX, Elkhartlake, Bonnell, Goldmont,
GoldmontPlus, Westmere EP-DP, Haswell, HaswellX, Icelake, IcelakeX,
Ivybridge, Ivytown, Jaketown, Knights Landing, Nehalem EP,
Sandybridge, Silvermont, Skylake, Skylake Server, SkylakeX,
Tigerlake, TremontX, Westmere EP-SP, and Westmere EX.
ARM:
- Add support for HiSilicon CPA PMU aliasing.
perf stat:
- Fix forked applications enablement of counters.
- The 'slots' should only be printed on a different order than the
one specified on the command line when 'topdown' events are
present, fix it.
Miscellaneous:
- Sync msr-index, cpufeatures header files with the kernel sources.
- Stop using some deprecated libbpf APIs in 'perf trace'.
- Fix some spelling mistakes.
- Refactor the maps pointers usage to pave the way for using refcount
debugging.
- Only offer the --tui option on perf top, report and annotate when
perf was built with libslang.
- Don't mention --to-ctf in 'perf data --help' when not linking with
the required library, libbabeltrace.
- Use ARRAY_SIZE() instead of ad hoc equivalent, spotted by
array_size.cocci.
- Enhance the matching of sub-commands abbreviations:
'perf c2c rec' -> 'perf c2c record'
'perf c2c recport -> error
- Set build-id using build-id header on new mmap records.
- Fix generation of 'perf --version' string.
perf test:
- Add test for the arm_spe event.
- Add test to check unwinding using fame-pointer (fp) mode on arm64.
- Make metric testing more robust in 'perf test'.
- Add error message for unsupported branch stack cases.
libperf:
- Add API for allocating new thread map array.
- Fix typo in perf_evlist__open() failure error messages in libperf
tests.
perf c2c:
- Replace bitmap_weight() with bitmap_empty() where appropriate"
* tag 'perf-tools-for-v5.18-2022-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (143 commits)
perf evsel: Improve AMD IBS (Instruction-Based Sampling) error handling messages
perf python: Add perf_env stubs that will be needed in evsel__open_strerror()
perf tools: Enhance the matching of sub-commands abbreviations
libperf tests: Fix typo in perf_evlist__open() failure error messages
tools arm64: Import cputype.h
perf lock: Add -F/--field option to control output
perf lock: Extend struct lock_key to have print function
perf lock: Add --synth=no option for record
tools headers cpufeatures: Sync with the kernel sources
tools headers cpufeatures: Sync with the kernel sources
perf stat: Fix forked applications enablement of counters
tools arch x86: Sync the msr-index.h copy with the kernel sources
perf evsel: Make evsel__env() always return a valid env
perf build-id: Fix spelling mistake "Cant" -> "Can't"
perf header: Fix spelling mistake "could't" -> "couldn't"
perf script: Add 'brstackinsnlen' for branch stacks
perf parse-events: Move slots only with topdown
perf ftrace latency: Update documentation
perf ftrace latency: Add -n/--use-nsec option
perf tools: Fix version kernel tag
...
This commit is contained in:
Linus Torvalds
commit
7b58b82b86
258
tools/arch/arm64/include/asm/cputype.h
Normal file
258
tools/arch/arm64/include/asm/cputype.h
Normal file
@ -0,0 +1,258 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2012 ARM Ltd.
|
||||
*/
|
||||
#ifndef __ASM_CPUTYPE_H
|
||||
#define __ASM_CPUTYPE_H
|
||||
|
||||
#define INVALID_HWID ULONG_MAX
|
||||
|
||||
#define MPIDR_UP_BITMASK (0x1 << 30)
|
||||
#define MPIDR_MT_BITMASK (0x1 << 24)
|
||||
#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
|
||||
|
||||
#define MPIDR_LEVEL_BITS_SHIFT 3
|
||||
#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
|
||||
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
|
||||
|
||||
#define MPIDR_LEVEL_SHIFT(level) \
|
||||
(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
|
||||
|
||||
#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
|
||||
((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
|
||||
|
||||
#define MIDR_REVISION_MASK 0xf
|
||||
#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
|
||||
#define MIDR_PARTNUM_SHIFT 4
|
||||
#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
|
||||
#define MIDR_PARTNUM(midr) \
|
||||
(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
|
||||
#define MIDR_ARCHITECTURE_SHIFT 16
|
||||
#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
|
||||
#define MIDR_ARCHITECTURE(midr) \
|
||||
(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
|
||||
#define MIDR_VARIANT_SHIFT 20
|
||||
#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
|
||||
#define MIDR_VARIANT(midr) \
|
||||
(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
|
||||
#define MIDR_IMPLEMENTOR_SHIFT 24
|
||||
#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
|
||||
#define MIDR_IMPLEMENTOR(midr) \
|
||||
(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
|
||||
|
||||
#define MIDR_CPU_MODEL(imp, partnum) \
|
||||
(((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
|
||||
(0xf << MIDR_ARCHITECTURE_SHIFT) | \
|
||||
((partnum) << MIDR_PARTNUM_SHIFT))
|
||||
|
||||
#define MIDR_CPU_VAR_REV(var, rev) \
|
||||
(((var) << MIDR_VARIANT_SHIFT) | (rev))
|
||||
|
||||
#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
|
||||
MIDR_ARCHITECTURE_MASK)
|
||||
|
||||
#define ARM_CPU_IMP_ARM 0x41
|
||||
#define ARM_CPU_IMP_APM 0x50
|
||||
#define ARM_CPU_IMP_CAVIUM 0x43
|
||||
#define ARM_CPU_IMP_BRCM 0x42
|
||||
#define ARM_CPU_IMP_QCOM 0x51
|
||||
#define ARM_CPU_IMP_NVIDIA 0x4E
|
||||
#define ARM_CPU_IMP_FUJITSU 0x46
|
||||
#define ARM_CPU_IMP_HISI 0x48
|
||||
#define ARM_CPU_IMP_APPLE 0x61
|
||||
|
||||
#define ARM_CPU_PART_AEM_V8 0xD0F
|
||||
#define ARM_CPU_PART_FOUNDATION 0xD00
|
||||
#define ARM_CPU_PART_CORTEX_A57 0xD07
|
||||
#define ARM_CPU_PART_CORTEX_A72 0xD08
|
||||
#define ARM_CPU_PART_CORTEX_A53 0xD03
|
||||
#define ARM_CPU_PART_CORTEX_A73 0xD09
|
||||
#define ARM_CPU_PART_CORTEX_A75 0xD0A
|
||||
#define ARM_CPU_PART_CORTEX_A35 0xD04
|
||||
#define ARM_CPU_PART_CORTEX_A55 0xD05
|
||||
#define ARM_CPU_PART_CORTEX_A76 0xD0B
|
||||
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
|
||||
#define ARM_CPU_PART_CORTEX_A77 0xD0D
|
||||
#define ARM_CPU_PART_NEOVERSE_V1 0xD40
|
||||
#define ARM_CPU_PART_CORTEX_A78 0xD41
|
||||
#define ARM_CPU_PART_CORTEX_X1 0xD44
|
||||
#define ARM_CPU_PART_CORTEX_A510 0xD46
|
||||
#define ARM_CPU_PART_CORTEX_A710 0xD47
|
||||
#define ARM_CPU_PART_CORTEX_X2 0xD48
|
||||
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
|
||||
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
|
||||
|
||||
#define APM_CPU_PART_POTENZA 0x000
|
||||
|
||||
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
|
||||
#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
|
||||
#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
|
||||
#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
|
||||
/* OcteonTx2 series */
|
||||
#define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1
|
||||
#define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2
|
||||
#define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3
|
||||
#define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4
|
||||
#define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5
|
||||
#define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6
|
||||
|
||||
#define BRCM_CPU_PART_BRAHMA_B53 0x100
|
||||
#define BRCM_CPU_PART_VULCAN 0x516
|
||||
|
||||
#define QCOM_CPU_PART_FALKOR_V1 0x800
|
||||
#define QCOM_CPU_PART_FALKOR 0xC00
|
||||
#define QCOM_CPU_PART_KRYO 0x200
|
||||
#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
|
||||
#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
|
||||
#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
|
||||
#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
|
||||
#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
|
||||
|
||||
#define NVIDIA_CPU_PART_DENVER 0x003
|
||||
#define NVIDIA_CPU_PART_CARMEL 0x004
|
||||
|
||||
#define FUJITSU_CPU_PART_A64FX 0x001
|
||||
|
||||
#define HISI_CPU_PART_TSV110 0xD01
|
||||
|
||||
#define APPLE_CPU_PART_M1_ICESTORM 0x022
|
||||
#define APPLE_CPU_PART_M1_FIRESTORM 0x023
|
||||
|
||||
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
|
||||
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
|
||||
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
|
||||
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
|
||||
#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
|
||||
#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
|
||||
#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
|
||||
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
|
||||
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
|
||||
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
|
||||
#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
|
||||
#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
|
||||
#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
|
||||
#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
|
||||
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
|
||||
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
|
||||
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
|
||||
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
|
||||
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
|
||||
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
|
||||
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
|
||||
#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
|
||||
#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
|
||||
#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
|
||||
#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
|
||||
#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
|
||||
#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
|
||||
#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
|
||||
#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
|
||||
#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
|
||||
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
|
||||
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
|
||||
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
|
||||
#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
|
||||
#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
|
||||
#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
|
||||
#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
|
||||
#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
|
||||
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
|
||||
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
|
||||
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
|
||||
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
|
||||
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
|
||||
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
|
||||
|
||||
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
|
||||
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
|
||||
#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
|
||||
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include "sysreg.h"
|
||||
|
||||
#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
|
||||
|
||||
/*
|
||||
* Represent a range of MIDR values for a given CPU model and a
|
||||
* range of variant/revision values.
|
||||
*
|
||||
* @model - CPU model as defined by MIDR_CPU_MODEL
|
||||
* @rv_min - Minimum value for the revision/variant as defined by
|
||||
* MIDR_CPU_VAR_REV
|
||||
* @rv_max - Maximum value for the variant/revision for the range.
|
||||
*/
|
||||
struct midr_range {
|
||||
u32 model;
|
||||
u32 rv_min;
|
||||
u32 rv_max;
|
||||
};
|
||||
|
||||
#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
|
||||
{ \
|
||||
.model = m, \
|
||||
.rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
|
||||
.rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
|
||||
}
|
||||
|
||||
#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
|
||||
#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
|
||||
#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
|
||||
|
||||
static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
|
||||
u32 rv_max)
|
||||
{
|
||||
u32 _model = midr & MIDR_CPU_MODEL_MASK;
|
||||
u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
|
||||
|
||||
return _model == model && rv >= rv_min && rv <= rv_max;
|
||||
}
|
||||
|
||||
static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
|
||||
{
|
||||
return midr_is_cpu_model_range(midr, range->model,
|
||||
range->rv_min, range->rv_max);
|
||||
}
|
||||
|
||||
static inline bool
|
||||
is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
|
||||
{
|
||||
while (ranges->model)
|
||||
if (is_midr_in_range(midr, ranges++))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* The CPU ID never changes at run time, so we might as well tell the
|
||||
* compiler that it's constant. Use this function to read the CPU ID
|
||||
* rather than directly reading processor_id or read_cpuid() directly.
|
||||
*/
|
||||
static inline u32 __attribute_const__ read_cpuid_id(void)
|
||||
{
|
||||
return read_cpuid(MIDR_EL1);
|
||||
}
|
||||
|
||||
static inline u64 __attribute_const__ read_cpuid_mpidr(void)
|
||||
{
|
||||
return read_cpuid(MPIDR_EL1);
|
||||
}
|
||||
|
||||
static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
|
||||
{
|
||||
return MIDR_IMPLEMENTOR(read_cpuid_id());
|
||||
}
|
||||
|
||||
static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
|
||||
{
|
||||
return MIDR_PARTNUM(read_cpuid_id());
|
||||
}
|
||||
|
||||
static inline u32 __attribute_const__ read_cpuid_cachetype(void)
|
||||
{
|
||||
return read_cpuid(CTR_EL0);
|
||||
}
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
@ -299,9 +299,6 @@
|
||||
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
|
||||
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
|
||||
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
|
||||
#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
|
||||
#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
|
||||
#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
|
||||
|
||||
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
|
||||
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
|
||||
@ -330,6 +327,7 @@
|
||||
#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
|
||||
#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
|
||||
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
|
||||
#define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */
|
||||
|
||||
/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
|
||||
#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
|
||||
@ -390,7 +388,10 @@
|
||||
#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
|
||||
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
|
||||
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
|
||||
#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
|
||||
#define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
|
||||
#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
|
||||
#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
|
||||
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
|
||||
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
|
||||
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
|
||||
|
||||
@ -56,8 +56,11 @@
|
||||
# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
|
||||
#endif
|
||||
|
||||
/* Force disable because it's broken beyond repair */
|
||||
#define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
|
||||
#ifdef CONFIG_INTEL_IOMMU_SVM
|
||||
# define DISABLE_ENQCMD 0
|
||||
#else
|
||||
# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_X86_SGX
|
||||
# define DISABLE_SGX 0
|
||||
|
||||
@ -705,12 +705,14 @@
|
||||
|
||||
#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
|
||||
#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
|
||||
#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
|
||||
|
||||
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
|
||||
|
||||
#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
|
||||
#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
|
||||
#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
|
||||
#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
|
||||
|
||||
/* Thermal Thresholds Support */
|
||||
#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
|
||||
@ -959,4 +961,8 @@
|
||||
#define MSR_VM_IGNNE 0xc0010115
|
||||
#define MSR_VM_HSAVE_PA 0xc0010117
|
||||
|
||||
/* Hardware Feedback Interface */
|
||||
#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
|
||||
#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
|
||||
|
||||
#endif /* _ASM_X86_MSR_INDEX_H */
|
||||
|
||||
@ -102,10 +102,6 @@
|
||||
# define __init
|
||||
#endif
|
||||
|
||||
#ifndef noinline
|
||||
# define noinline
|
||||
#endif
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
* ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
|
||||
* directly use below macros as config bits.
|
||||
*/
|
||||
#define ETM_OPT_BRANCH_BROADCAST 8
|
||||
#define ETM_OPT_CYCACC 12
|
||||
#define ETM_OPT_CTXTID 14
|
||||
#define ETM_OPT_CTXTID2 15
|
||||
@ -25,6 +26,7 @@
|
||||
#define ETM_OPT_RETSTK 29
|
||||
|
||||
/* ETMv4 CONFIGR programming bits for the ETM OPTs */
|
||||
#define ETM4_CFG_BIT_BB 3
|
||||
#define ETM4_CFG_BIT_CYCACC 4
|
||||
#define ETM4_CFG_BIT_CTXTID 6
|
||||
#define ETM4_CFG_BIT_VMID 7
|
||||
|
||||
@ -88,6 +88,23 @@ int fdarray__add(struct fdarray *fda, int fd, short revents, enum fdarray_flags
|
||||
return pos;
|
||||
}
|
||||
|
||||
int fdarray__dup_entry_from(struct fdarray *fda, int pos, struct fdarray *from)
|
||||
{
|
||||
struct pollfd *entry;
|
||||
int npos;
|
||||
|
||||
if (pos >= from->nr)
|
||||
return -EINVAL;
|
||||
|
||||
entry = &from->entries[pos];
|
||||
|
||||
npos = fdarray__add(fda, entry->fd, entry->events, from->priv[pos].flags);
|
||||
if (npos >= 0)
|
||||
fda->priv[npos] = from->priv[pos];
|
||||
|
||||
return npos;
|
||||
}
|
||||
|
||||
int fdarray__filter(struct fdarray *fda, short revents,
|
||||
void (*entry_destructor)(struct fdarray *fda, int fd, void *arg),
|
||||
void *arg)
|
||||
|
||||
@ -42,6 +42,7 @@ struct fdarray *fdarray__new(int nr_alloc, int nr_autogrow);
|
||||
void fdarray__delete(struct fdarray *fda);
|
||||
|
||||
int fdarray__add(struct fdarray *fda, int fd, short revents, enum fdarray_flags flags);
|
||||
int fdarray__dup_entry_from(struct fdarray *fda, int pos, struct fdarray *from);
|
||||
int fdarray__poll(struct fdarray *fda, int timeout);
|
||||
int fdarray__filter(struct fdarray *fda, short revents,
|
||||
void (*entry_destructor)(struct fdarray *fda, int fd, void *arg),
|
||||
|
||||
@ -62,11 +62,12 @@ SYNOPSIS
|
||||
struct perf_thread_map;
|
||||
|
||||
struct perf_thread_map *perf_thread_map__new_dummy(void);
|
||||
struct perf_thread_map *perf_thread_map__new_array(int nr_threads, pid_t *array);
|
||||
|
||||
void perf_thread_map__set_pid(struct perf_thread_map *map, int thread, pid_t pid);
|
||||
char *perf_thread_map__comm(struct perf_thread_map *map, int thread);
|
||||
void perf_thread_map__set_pid(struct perf_thread_map *map, int idx, pid_t pid);
|
||||
char *perf_thread_map__comm(struct perf_thread_map *map, int idx);
|
||||
int perf_thread_map__nr(struct perf_thread_map *threads);
|
||||
pid_t perf_thread_map__pid(struct perf_thread_map *map, int thread);
|
||||
pid_t perf_thread_map__pid(struct perf_thread_map *map, int idx);
|
||||
|
||||
struct perf_thread_map *perf_thread_map__get(struct perf_thread_map *map);
|
||||
void perf_thread_map__put(struct perf_thread_map *map);
|
||||
|
||||
@ -8,11 +8,12 @@
|
||||
struct perf_thread_map;
|
||||
|
||||
LIBPERF_API struct perf_thread_map *perf_thread_map__new_dummy(void);
|
||||
LIBPERF_API struct perf_thread_map *perf_thread_map__new_array(int nr_threads, pid_t *array);
|
||||
|
||||
LIBPERF_API void perf_thread_map__set_pid(struct perf_thread_map *map, int thread, pid_t pid);
|
||||
LIBPERF_API char *perf_thread_map__comm(struct perf_thread_map *map, int thread);
|
||||
LIBPERF_API void perf_thread_map__set_pid(struct perf_thread_map *map, int idx, pid_t pid);
|
||||
LIBPERF_API char *perf_thread_map__comm(struct perf_thread_map *map, int idx);
|
||||
LIBPERF_API int perf_thread_map__nr(struct perf_thread_map *threads);
|
||||
LIBPERF_API pid_t perf_thread_map__pid(struct perf_thread_map *map, int thread);
|
||||
LIBPERF_API pid_t perf_thread_map__pid(struct perf_thread_map *map, int idx);
|
||||
|
||||
LIBPERF_API struct perf_thread_map *perf_thread_map__get(struct perf_thread_map *map);
|
||||
LIBPERF_API void perf_thread_map__put(struct perf_thread_map *map);
|
||||
|
||||
@ -12,6 +12,7 @@ LIBPERF_0.0.1 {
|
||||
perf_cpu_map__empty;
|
||||
perf_cpu_map__max;
|
||||
perf_cpu_map__has;
|
||||
perf_thread_map__new_array;
|
||||
perf_thread_map__new_dummy;
|
||||
perf_thread_map__set_pid;
|
||||
perf_thread_map__comm;
|
||||
|
||||
@ -69,7 +69,7 @@ static int test_stat_cpu(void)
|
||||
perf_evlist__set_maps(evlist, cpus, NULL);
|
||||
|
||||
err = perf_evlist__open(evlist);
|
||||
__T("failed to open evsel", err == 0);
|
||||
__T("failed to open evlist", err == 0);
|
||||
|
||||
perf_evlist__for_each_evsel(evlist, evsel) {
|
||||
cpus = perf_evsel__cpus(evsel);
|
||||
@ -130,7 +130,7 @@ static int test_stat_thread(void)
|
||||
perf_evlist__set_maps(evlist, NULL, threads);
|
||||
|
||||
err = perf_evlist__open(evlist);
|
||||
__T("failed to open evsel", err == 0);
|
||||
__T("failed to open evlist", err == 0);
|
||||
|
||||
perf_evlist__for_each_evsel(evlist, evsel) {
|
||||
perf_evsel__read(evsel, 0, 0, &counts);
|
||||
@ -187,7 +187,7 @@ static int test_stat_thread_enable(void)
|
||||
perf_evlist__set_maps(evlist, NULL, threads);
|
||||
|
||||
err = perf_evlist__open(evlist);
|
||||
__T("failed to open evsel", err == 0);
|
||||
__T("failed to open evlist", err == 0);
|
||||
|
||||
perf_evlist__for_each_evsel(evlist, evsel) {
|
||||
perf_evsel__read(evsel, 0, 0, &counts);
|
||||
@ -507,7 +507,7 @@ static int test_stat_multiplexing(void)
|
||||
perf_evlist__set_maps(evlist, NULL, threads);
|
||||
|
||||
err = perf_evlist__open(evlist);
|
||||
__T("failed to open evsel", err == 0);
|
||||
__T("failed to open evlist", err == 0);
|
||||
|
||||
perf_evlist__enable(evlist);
|
||||
|
||||
|
||||
@ -11,9 +11,43 @@ static int libperf_print(enum libperf_print_level level,
|
||||
return vfprintf(stderr, fmt, ap);
|
||||
}
|
||||
|
||||
static int test_threadmap_array(int nr, pid_t *array)
|
||||
{
|
||||
struct perf_thread_map *threads;
|
||||
int i;
|
||||
|
||||
threads = perf_thread_map__new_array(nr, array);
|
||||
__T("Failed to allocate new thread map", threads);
|
||||
|
||||
__T("Unexpected number of threads", perf_thread_map__nr(threads) == nr);
|
||||
|
||||
for (i = 0; i < nr; i++) {
|
||||
__T("Unexpected initial value of thread",
|
||||
perf_thread_map__pid(threads, i) == (array ? array[i] : -1));
|
||||
}
|
||||
|
||||
for (i = 1; i < nr; i++)
|
||||
perf_thread_map__set_pid(threads, i, i * 100);
|
||||
|
||||
__T("Unexpected value of thread 0",
|
||||
perf_thread_map__pid(threads, 0) == (array ? array[0] : -1));
|
||||
|
||||
for (i = 1; i < nr; i++) {
|
||||
__T("Unexpected thread value",
|
||||
perf_thread_map__pid(threads, i) == i * 100);
|
||||
}
|
||||
|
||||
perf_thread_map__put(threads);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define THREADS_NR 10
|
||||
int test_threadmap(int argc, char **argv)
|
||||
{
|
||||
struct perf_thread_map *threads;
|
||||
pid_t thr_array[THREADS_NR];
|
||||
int i;
|
||||
|
||||
__T_START;
|
||||
|
||||
@ -27,6 +61,13 @@ int test_threadmap(int argc, char **argv)
|
||||
perf_thread_map__put(threads);
|
||||
perf_thread_map__put(threads);
|
||||
|
||||
test_threadmap_array(THREADS_NR, NULL);
|
||||
|
||||
for (i = 0; i < THREADS_NR; i++)
|
||||
thr_array[i] = i + 100;
|
||||
|
||||
test_threadmap_array(THREADS_NR, thr_array);
|
||||
|
||||
__T_END;
|
||||
return tests_failed == 0 ? 0 : -1;
|
||||
}
|
||||
|
||||
@ -32,26 +32,36 @@ struct perf_thread_map *perf_thread_map__realloc(struct perf_thread_map *map, in
|
||||
|
||||
#define thread_map__alloc(__nr) perf_thread_map__realloc(NULL, __nr)
|
||||
|
||||
void perf_thread_map__set_pid(struct perf_thread_map *map, int thread, pid_t pid)
|
||||
void perf_thread_map__set_pid(struct perf_thread_map *map, int idx, pid_t pid)
|
||||
{
|
||||
map->map[thread].pid = pid;
|
||||
map->map[idx].pid = pid;
|
||||
}
|
||||
|
||||
char *perf_thread_map__comm(struct perf_thread_map *map, int thread)
|
||||
char *perf_thread_map__comm(struct perf_thread_map *map, int idx)
|
||||
{
|
||||
return map->map[thread].comm;
|
||||
return map->map[idx].comm;
|
||||
}
|
||||
|
||||
struct perf_thread_map *perf_thread_map__new_array(int nr_threads, pid_t *array)
|
||||
{
|
||||
struct perf_thread_map *threads = thread_map__alloc(nr_threads);
|
||||
int i;
|
||||
|
||||
if (!threads)
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < nr_threads; i++)
|
||||
perf_thread_map__set_pid(threads, i, array ? array[i] : -1);
|
||||
|
||||
threads->nr = nr_threads;
|
||||
refcount_set(&threads->refcnt, 1);
|
||||
|
||||
return threads;
|
||||
}
|
||||
|
||||
struct perf_thread_map *perf_thread_map__new_dummy(void)
|
||||
{
|
||||
struct perf_thread_map *threads = thread_map__alloc(1);
|
||||
|
||||
if (threads != NULL) {
|
||||
perf_thread_map__set_pid(threads, 0, -1);
|
||||
threads->nr = 1;
|
||||
refcount_set(&threads->refcnt, 1);
|
||||
}
|
||||
return threads;
|
||||
return perf_thread_map__new_array(1, NULL);
|
||||
}
|
||||
|
||||
static void perf_thread_map__delete(struct perf_thread_map *threads)
|
||||
@ -85,7 +95,7 @@ int perf_thread_map__nr(struct perf_thread_map *threads)
|
||||
return threads ? threads->nr : 1;
|
||||
}
|
||||
|
||||
pid_t perf_thread_map__pid(struct perf_thread_map *map, int thread)
|
||||
pid_t perf_thread_map__pid(struct perf_thread_map *map, int idx)
|
||||
{
|
||||
return map->map[thread].pid;
|
||||
return map->map[idx].pid;
|
||||
}
|
||||
|
||||
@ -7,6 +7,8 @@
|
||||
p synthesize power events (incl. PSB events for Intel PT)
|
||||
o synthesize other events recorded due to the use
|
||||
of aux-output (refer to perf record)
|
||||
I synthesize interrupt or similar (asynchronous) events
|
||||
(e.g. Intel PT Event Trace)
|
||||
e synthesize error events
|
||||
d create a debug log
|
||||
f synthesize first level cache events
|
||||
|
||||
@ -9,32 +9,24 @@ perf-ftrace - simple wrapper for kernel's ftrace functionality
|
||||
SYNOPSIS
|
||||
--------
|
||||
[verse]
|
||||
'perf ftrace' <command>
|
||||
'perf ftrace' {trace|latency} <command>
|
||||
|
||||
DESCRIPTION
|
||||
-----------
|
||||
The 'perf ftrace' command is a simple wrapper of kernel's ftrace
|
||||
functionality. It only supports single thread tracing currently and
|
||||
just reads trace_pipe in text and then write it to stdout.
|
||||
The 'perf ftrace' command provides a collection of subcommands which use
|
||||
kernel's ftrace infrastructure.
|
||||
|
||||
'perf ftrace trace' is a simple wrapper of the ftrace. It only supports
|
||||
single thread tracing currently and just reads trace_pipe in text and then
|
||||
write it to stdout.
|
||||
|
||||
'perf ftrace latency' calculates execution latency of a given function
|
||||
(optionally with BPF) and display it as a histogram.
|
||||
|
||||
The following options apply to perf ftrace.
|
||||
|
||||
OPTIONS
|
||||
-------
|
||||
|
||||
-t::
|
||||
--tracer=::
|
||||
Tracer to use when neither -G nor -F option is not
|
||||
specified: function_graph or function.
|
||||
|
||||
-v::
|
||||
--verbose::
|
||||
Increase the verbosity level.
|
||||
|
||||
-F::
|
||||
--funcs::
|
||||
List available functions to trace. It accepts a pattern to
|
||||
only list interested functions.
|
||||
COMMON OPTIONS
|
||||
--------------
|
||||
|
||||
-p::
|
||||
--pid=::
|
||||
@ -43,10 +35,6 @@ OPTIONS
|
||||
--tid=::
|
||||
Trace on existing thread id (comma separated list).
|
||||
|
||||
-D::
|
||||
--delay::
|
||||
Time (ms) to wait before starting tracing after program start.
|
||||
|
||||
-a::
|
||||
--all-cpus::
|
||||
Force system-wide collection. Scripts run without a <command>
|
||||
@ -61,6 +49,28 @@ OPTIONS
|
||||
Ranges of CPUs are specified with -: 0-2.
|
||||
Default is to trace on all online CPUs.
|
||||
|
||||
-v::
|
||||
--verbose::
|
||||
Increase the verbosity level.
|
||||
|
||||
|
||||
OPTIONS for 'perf ftrace trace'
|
||||
-------------------------------
|
||||
|
||||
-t::
|
||||
--tracer=::
|
||||
Tracer to use when neither -G nor -F option is not
|
||||
specified: function_graph or function.
|
||||
|
||||
-F::
|
||||
--funcs::
|
||||
List available functions to trace. It accepts a pattern to
|
||||
only list interested functions.
|
||||
|
||||
-D::
|
||||
--delay::
|
||||
Time (ms) to wait before starting tracing after program start.
|
||||
|
||||
-m::
|
||||
--buffer-size::
|
||||
Set the size of per-cpu tracing buffer, <size> is expected to
|
||||
@ -114,6 +124,25 @@ OPTIONS
|
||||
thresh=<n> - Setup trace duration threshold in microseconds.
|
||||
depth=<n> - Set max depth for function graph tracer to follow.
|
||||
|
||||
|
||||
OPTIONS for 'perf ftrace latency'
|
||||
---------------------------------
|
||||
|
||||
-T::
|
||||
--trace-funcs=::
|
||||
Set the function name to get the histogram. Unlike perf ftrace trace,
|
||||
it only allows single function to calculate the histogram.
|
||||
|
||||
-b::
|
||||
--use-bpf::
|
||||
Use BPF to measure function latency instead of using the ftrace (it
|
||||
uses function_graph tracer internally).
|
||||
|
||||
-n::
|
||||
--use-nsec::
|
||||
Use nano-second instead of micro-second as a base unit of the histogram.
|
||||
|
||||
|
||||
SEE ALSO
|
||||
--------
|
||||
linkperf:perf-record[1], linkperf:perf-trace[1]
|
||||
|
||||
@ -108,9 +108,10 @@ displayed as follows:
|
||||
|
||||
perf script --itrace=ibxwpe -F+flags
|
||||
|
||||
The flags are "bcrosyiABExgh" which stand for branch, call, return, conditional,
|
||||
The flags are "bcrosyiABExghDt" which stand for branch, call, return, conditional,
|
||||
system, asynchronous, interrupt, transaction abort, trace begin, trace end,
|
||||
in transaction, VM-entry, and VM-exit respectively.
|
||||
in transaction, VM-entry, VM-exit, interrupt disabled, and interrupt disable
|
||||
toggle respectively.
|
||||
|
||||
perf script also supports higher level ways to dump instruction traces:
|
||||
|
||||
@ -483,6 +484,30 @@ pwr_evt Enable power events. The power events provide information about
|
||||
which contains "1" if the feature is supported and
|
||||
"0" otherwise.
|
||||
|
||||
event Enable Event Trace. The events provide information about asynchronous
|
||||
events.
|
||||
|
||||
Support for this feature is indicated by:
|
||||
|
||||
/sys/bus/event_source/devices/intel_pt/caps/event_trace
|
||||
|
||||
which contains "1" if the feature is supported and
|
||||
"0" otherwise.
|
||||
|
||||
notnt Disable TNT packets. Without TNT packets, it is not possible to walk
|
||||
executable code to reconstruct control flow, however FUP, TIP, TIP.PGE
|
||||
and TIP.PGD packets still indicate asynchronous control flow, and (if
|
||||
return compression is disabled - see noretcomp) return statements.
|
||||
The advantage of eliminating TNT packets is reducing the size of the
|
||||
trace and corresponding tracing overhead.
|
||||
|
||||
Support for this feature is indicated by:
|
||||
|
||||
/sys/bus/event_source/devices/intel_pt/caps/tnt_disable
|
||||
|
||||
which contains "1" if the feature is supported and
|
||||
"0" otherwise.
|
||||
|
||||
|
||||
AUX area sampling option
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
@ -876,6 +901,8 @@ The letters are:
|
||||
p synthesize "power" events (incl. PSB events)
|
||||
c synthesize branches events (calls only)
|
||||
r synthesize branches events (returns only)
|
||||
o synthesize PEBS-via-PT events
|
||||
I synthesize Event Trace events
|
||||
e synthesize tracing error events
|
||||
d create a debug log
|
||||
g synthesize a call chain (use with i or x)
|
||||
@ -1371,6 +1398,79 @@ There were none.
|
||||
:17006 17006 [001] 11500.262869216: ffffffff8220116e error_entry+0xe ([guest.kernel.kallsyms]) pushq %rax
|
||||
|
||||
|
||||
Event Trace
|
||||
-----------
|
||||
|
||||
Event Trace records information about asynchronous events, for example interrupts,
|
||||
faults, VM exits and entries. The information is recorded in CFE and EVD packets,
|
||||
and also the Interrupt Flag is recorded on the MODE.Exec packet. The CFE packet
|
||||
contains a type field to identify one of the following:
|
||||
|
||||
1 INTR interrupt, fault, exception, NMI
|
||||
2 IRET interrupt return
|
||||
3 SMI system management interrupt
|
||||
4 RSM resume from system management mode
|
||||
5 SIPI startup interprocessor interrupt
|
||||
6 INIT INIT signal
|
||||
7 VMENTRY VM-Entry
|
||||
8 VMEXIT VM-Entry
|
||||
9 VMEXIT_INTR VM-Exit due to interrupt
|
||||
10 SHUTDOWN Shutdown
|
||||
|
||||
For more details, refer to the Intel 64 and IA-32 Architectures Software
|
||||
Developer Manuals (version 076 or later).
|
||||
|
||||
The capability to do Event Trace is indicated by the
|
||||
/sys/bus/event_source/devices/intel_pt/caps/event_trace file.
|
||||
|
||||
Event trace is selected for recording using the "event" config term. e.g.
|
||||
|
||||
perf record -e intel_pt/event/u uname
|
||||
|
||||
Event trace events are output using the --itrace I option. e.g.
|
||||
|
||||
perf script --itrace=Ie
|
||||
|
||||
perf script displays events containing CFE type, vector and event data,
|
||||
in the form:
|
||||
|
||||
evt: hw int (t) cfe: INTR IP: 1 vector: 3 PFA: 0x8877665544332211
|
||||
|
||||
The IP flag indicates if the event binds to an IP, which includes any case where
|
||||
flow control packet generation is enabled, as well as when CFE packet IP bit is
|
||||
set.
|
||||
|
||||
perf script displays events containing changes to the Interrupt Flag in the form:
|
||||
|
||||
iflag: t IFLAG: 1->0 via branch
|
||||
|
||||
where "via branch" indicates a branch (interrupt or return from interrupt) and
|
||||
"non branch" indicates an instruction such as CFI, STI or POPF).
|
||||
|
||||
In addition, the current state of the interrupt flag is indicated by the presence
|
||||
or absence of the "D" (interrupt disabled) perf script flag. If the interrupt
|
||||
flag is changed, then the "t" flag is also included i.e.
|
||||
|
||||
no flag, interrupts enabled IF=1
|
||||
t interrupts become disabled IF=1 -> IF=0
|
||||
D interrupts are disabled IF=0
|
||||
Dt interrupts become enabled IF=0 -> IF=1
|
||||
|
||||
The intel-pt-events.py script illustrates how to access Event Trace information
|
||||
using a Python script.
|
||||
|
||||
|
||||
TNT Disable
|
||||
-----------
|
||||
|
||||
TNT packets are disabled using the "notnt" config term. e.g.
|
||||
|
||||
perf record -e intel_pt/notnt/u uname
|
||||
|
||||
In that case the --itrace q option is forced because walking executable code
|
||||
to reconstruct the control flow is not possible.
|
||||
|
||||
|
||||
|
||||
SEE ALSO
|
||||
--------
|
||||
|
||||
@ -54,6 +54,16 @@ REPORT OPTIONS
|
||||
Sorting key. Possible values: acquired (default), contended,
|
||||
avg_wait, wait_total, wait_max, wait_min.
|
||||
|
||||
-F::
|
||||
--field=<value>::
|
||||
Output fields. By default it shows all the fields but users can
|
||||
customize that using this. Possible values: acquired, contended,
|
||||
avg_wait, wait_total, wait_max, wait_min.
|
||||
|
||||
-c::
|
||||
--combine-locks::
|
||||
Merge lock instances in the same class (based on name).
|
||||
|
||||
INFO OPTIONS
|
||||
------------
|
||||
|
||||
|
||||
@ -713,6 +713,40 @@ measurements:
|
||||
wait -n ${perf_pid}
|
||||
exit $?
|
||||
|
||||
--threads=<spec>::
|
||||
Write collected trace data into several data files using parallel threads.
|
||||
<spec> value can be user defined list of masks. Masks separated by colon
|
||||
define CPUs to be monitored by a thread and affinity mask of that thread
|
||||
is separated by slash:
|
||||
|
||||
<cpus mask 1>/<affinity mask 1>:<cpus mask 2>/<affinity mask 2>:...
|
||||
|
||||
CPUs or affinity masks must not overlap with other corresponding masks.
|
||||
Invalid CPUs are ignored, but masks containing only invalid CPUs are not
|
||||
allowed.
|
||||
|
||||
For example user specification like the following:
|
||||
|
||||
0,2-4/2-4:1,5-7/5-7
|
||||
|
||||
specifies parallel threads layout that consists of two threads,
|
||||
the first thread monitors CPUs 0 and 2-4 with the affinity mask 2-4,
|
||||
the second monitors CPUs 1 and 5-7 with the affinity mask 5-7.
|
||||
|
||||
<spec> value can also be a string meaning predefined parallel threads
|
||||
layout:
|
||||
|
||||
cpu - create new data streaming thread for every monitored cpu
|
||||
core - create new thread to monitor CPUs grouped by a core
|
||||
package - create new thread to monitor CPUs grouped by a package
|
||||
numa - create new threed to monitor CPUs grouped by a NUMA domain
|
||||
|
||||
Predefined layouts can be used on systems with large number of CPUs in
|
||||
order not to spawn multiple per-cpu streaming threads but still avoid LOST
|
||||
events in data directory files. Option specified with no or empty value
|
||||
defaults to CPU layout. Masks defined or provided by the option value are
|
||||
filtered through the mask provided by -C option.
|
||||
|
||||
include::intel-hybrid.txt[]
|
||||
|
||||
--debuginfod[=URLs]::
|
||||
|
||||
@ -129,8 +129,8 @@ OPTIONS
|
||||
Comma separated list of fields to print. Options are:
|
||||
comm, tid, pid, time, cpu, event, trace, ip, sym, dso, addr, symoff,
|
||||
srcline, period, iregs, uregs, brstack, brstacksym, flags, bpf-output,
|
||||
brstackinsn, brstackoff, callindent, insn, insnlen, synth, phys_addr,
|
||||
metric, misc, srccode, ipc, data_page_size, code_page_size, ins_lat.
|
||||
brstackinsn, brstackinsnlen, brstackoff, callindent, insn, insnlen, synth,
|
||||
phys_addr, metric, misc, srccode, ipc, data_page_size, code_page_size, ins_lat.
|
||||
Field list can be prepended with the type, trace, sw or hw,
|
||||
to indicate to which event type the field list applies.
|
||||
e.g., -F sw:comm,tid,time,ip,sym and -F trace:time,cpu,trace
|
||||
@ -195,16 +195,19 @@ OPTIONS
|
||||
At this point usage is displayed, and perf-script exits.
|
||||
|
||||
The flags field is synthesized and may have a value when Instruction
|
||||
Trace decoding. The flags are "bcrosyiABExgh" which stand for branch,
|
||||
Trace decoding. The flags are "bcrosyiABExghDt" which stand for branch,
|
||||
call, return, conditional, system, asynchronous, interrupt,
|
||||
transaction abort, trace begin, trace end, in transaction, VM-Entry, and VM-Exit
|
||||
respectively. Known combinations of flags are printed more nicely e.g.
|
||||
transaction abort, trace begin, trace end, in transaction, VM-Entry,
|
||||
VM-Exit, interrupt disabled and interrupt disable toggle respectively.
|
||||
Known combinations of flags are printed more nicely e.g.
|
||||
"call" for "bc", "return" for "br", "jcc" for "bo", "jmp" for "b",
|
||||
"int" for "bci", "iret" for "bri", "syscall" for "bcs", "sysret" for "brs",
|
||||
"async" for "by", "hw int" for "bcyi", "tx abrt" for "bA", "tr strt" for "bB",
|
||||
"tr end" for "bE", "vmentry" for "bcg", "vmexit" for "bch".
|
||||
However the "x" flag will be displayed separately in those
|
||||
cases e.g. "jcc (x)" for a condition branch within a transaction.
|
||||
However the "x", "D" and "t" flags will be displayed separately in those
|
||||
cases e.g. "jcc (xD)" for a condition branch within a transaction
|
||||
with interrupts disabled. Note, interrupts becoming disabled is "t",
|
||||
whereas interrupts becoming enabled is "Dt".
|
||||
|
||||
The callindent field is synthesized and may have a value when
|
||||
Instruction Trace decoding. For calls and returns, it will display the
|
||||
@ -238,6 +241,10 @@ OPTIONS
|
||||
is printed. This is the full execution path leading to the sample. This is only supported when the
|
||||
sample was recorded with perf record -b or -j any.
|
||||
|
||||
Use brstackinsnlen to print the brstackinsn lenght. For example, you
|
||||
can’t know the next sequential instruction after an unconditional branch unless
|
||||
you calculate that based on its length.
|
||||
|
||||
The brstackoff field will print an offset into a specific dso/binary.
|
||||
|
||||
With the metric option perf script can compute metrics for
|
||||
|
||||
@ -691,7 +691,7 @@ $(OUTPUT)common-cmds.h: $(wildcard Documentation/perf-*.txt)
|
||||
$(SCRIPTS) : % : %.sh
|
||||
$(QUIET_GEN)$(INSTALL) '$@.sh' '$(OUTPUT)$@'
|
||||
|
||||
$(OUTPUT)PERF-VERSION-FILE: ../../.git/HEAD
|
||||
$(OUTPUT)PERF-VERSION-FILE: ../../.git/HEAD ../../.git/ORIG_HEAD
|
||||
$(Q)$(SHELL_PATH) util/PERF-VERSION-GEN $(OUTPUT)
|
||||
$(Q)touch $(OUTPUT)PERF-VERSION-FILE
|
||||
|
||||
@ -1144,7 +1144,7 @@ endif
|
||||
# then force version regeneration:
|
||||
#
|
||||
ifeq ($(wildcard ../../.git/HEAD),)
|
||||
GIT-HEAD-PHONY = ../../.git/HEAD
|
||||
GIT-HEAD-PHONY = ../../.git/HEAD ../../.git/ORIG_HEAD
|
||||
else
|
||||
GIT-HEAD-PHONY =
|
||||
endif
|
||||
|
||||
@ -510,6 +510,9 @@ static u64 cs_etmv4_get_config(struct auxtrace_record *itr)
|
||||
if (config_opts & BIT(ETM_OPT_CTXTID2))
|
||||
config |= BIT(ETM4_CFG_BIT_VMID) |
|
||||
BIT(ETM4_CFG_BIT_VMID_OPT);
|
||||
if (config_opts & BIT(ETM_OPT_BRANCH_BROADCAST))
|
||||
config |= BIT(ETM4_CFG_BIT_BB);
|
||||
|
||||
return config;
|
||||
}
|
||||
|
||||
|
||||
@ -158,7 +158,7 @@ static int arm_spe_recording_options(struct auxtrace_record *itr,
|
||||
return -EINVAL;
|
||||
}
|
||||
evsel->core.attr.freq = 0;
|
||||
evsel->core.attr.sample_period = 1;
|
||||
evsel->core.attr.sample_period = arm_spe_pmu->default_config->sample_period;
|
||||
arm_spe_evsel = evsel;
|
||||
opts->full_auxtrace = true;
|
||||
}
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
* @new_ctx: expected new packet context
|
||||
* @ctx_unchanged: the packet context must not change
|
||||
*/
|
||||
struct test_data {
|
||||
static struct test_data {
|
||||
int len;
|
||||
u8 bytes[INTEL_PT_PKT_MAX_SZ];
|
||||
enum intel_pt_pkt_ctx ctx;
|
||||
@ -70,8 +70,11 @@ struct test_data {
|
||||
{8, {0x02, 0x43, 3, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0xC0A08060403}, 0, 0 },
|
||||
/* Mode Exec Packet */
|
||||
{2, {0x99, 0x00}, 0, {INTEL_PT_MODE_EXEC, 0, 16}, 0, 0 },
|
||||
{2, {0x99, 0x01}, 0, {INTEL_PT_MODE_EXEC, 0, 64}, 0, 0 },
|
||||
{2, {0x99, 0x02}, 0, {INTEL_PT_MODE_EXEC, 0, 32}, 0, 0 },
|
||||
{2, {0x99, 0x01}, 0, {INTEL_PT_MODE_EXEC, 1, 64}, 0, 0 },
|
||||
{2, {0x99, 0x02}, 0, {INTEL_PT_MODE_EXEC, 2, 32}, 0, 0 },
|
||||
{2, {0x99, 0x04}, 0, {INTEL_PT_MODE_EXEC, 4, 16}, 0, 0 },
|
||||
{2, {0x99, 0x05}, 0, {INTEL_PT_MODE_EXEC, 5, 64}, 0, 0 },
|
||||
{2, {0x99, 0x06}, 0, {INTEL_PT_MODE_EXEC, 6, 32}, 0, 0 },
|
||||
/* Mode TSX Packet */
|
||||
{2, {0x99, 0x20}, 0, {INTEL_PT_MODE_TSX, 0, 0}, 0, 0 },
|
||||
{2, {0x99, 0x21}, 0, {INTEL_PT_MODE_TSX, 0, 1}, 0, 0 },
|
||||
@ -166,6 +169,14 @@ struct test_data {
|
||||
{2, {0x02, 0xb3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 },
|
||||
{2, {0x02, 0x33}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 },
|
||||
{2, {0x02, 0xb3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 },
|
||||
/* Control Flow Event Packet */
|
||||
{4, {0x02, 0x13, 0x01, 0x03}, 0, {INTEL_PT_CFE, 1, 3}, 0, 0 },
|
||||
{4, {0x02, 0x13, 0x81, 0x03}, 0, {INTEL_PT_CFE_IP, 1, 3}, 0, 0 },
|
||||
{4, {0x02, 0x13, 0x1f, 0x00}, 0, {INTEL_PT_CFE, 0x1f, 0}, 0, 0 },
|
||||
{4, {0x02, 0x13, 0x9f, 0xff}, 0, {INTEL_PT_CFE_IP, 0x1f, 0xff}, 0, 0 },
|
||||
/* */
|
||||
{11, {0x02, 0x53, 0x09, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_EVD, 0x09, 0x7060504030201}, 0, 0 },
|
||||
{11, {0x02, 0x53, 0x3f, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_EVD, 0x3f, 0x8070605040302}, 0, 0 },
|
||||
/* Terminator */
|
||||
{0, {0}, 0, {0, 0, 0}, 0, 0 },
|
||||
};
|
||||
|
||||
@ -18,7 +18,7 @@ int perf_event__synthesize_extra_kmaps(struct perf_tool *tool,
|
||||
{
|
||||
int rc = 0;
|
||||
struct map *pos;
|
||||
struct maps *kmaps = &machine->kmaps;
|
||||
struct maps *kmaps = machine__kernel_maps(machine);
|
||||
union perf_event *event = zalloc(sizeof(event->mmap) +
|
||||
machine->id_hdr_size);
|
||||
|
||||
|
||||
@ -20,17 +20,27 @@ int arch_evlist__add_default_attrs(struct evlist *evlist)
|
||||
|
||||
struct evsel *arch_evlist__leader(struct list_head *list)
|
||||
{
|
||||
struct evsel *evsel, *first;
|
||||
struct evsel *evsel, *first, *slots = NULL;
|
||||
bool has_topdown = false;
|
||||
|
||||
first = list_first_entry(list, struct evsel, core.node);
|
||||
|
||||
if (!pmu_have_event("cpu", "slots"))
|
||||
return first;
|
||||
|
||||
/* If there is a slots event and a topdown event then the slots event comes first. */
|
||||
__evlist__for_each_entry(list, evsel) {
|
||||
if (evsel->pmu_name && !strcmp(evsel->pmu_name, "cpu") &&
|
||||
evsel->name && strcasestr(evsel->name, "slots"))
|
||||
return evsel;
|
||||
if (evsel->pmu_name && !strcmp(evsel->pmu_name, "cpu") && evsel->name) {
|
||||
if (strcasestr(evsel->name, "slots")) {
|
||||
slots = evsel;
|
||||
if (slots == first)
|
||||
return first;
|
||||
}
|
||||
if (!strncasecmp(evsel->name, "topdown", 7))
|
||||
has_topdown = true;
|
||||
if (slots && has_topdown)
|
||||
return slots;
|
||||
}
|
||||
}
|
||||
return first;
|
||||
}
|
||||
|
||||
@ -306,6 +306,7 @@ intel_pt_info_priv_size(struct auxtrace_record *itr, struct evlist *evlist)
|
||||
|
||||
ptr->priv_size = (INTEL_PT_AUXTRACE_PRIV_MAX * sizeof(u64)) +
|
||||
intel_pt_filter_bytes(filter);
|
||||
ptr->priv_size += sizeof(u64); /* Cap Event Trace */
|
||||
|
||||
return ptr->priv_size;
|
||||
}
|
||||
@ -335,6 +336,7 @@ static int intel_pt_info_fill(struct auxtrace_record *itr,
|
||||
unsigned long max_non_turbo_ratio;
|
||||
size_t filter_str_len;
|
||||
const char *filter;
|
||||
int event_trace;
|
||||
__u64 *info;
|
||||
int err;
|
||||
|
||||
@ -357,6 +359,9 @@ static int intel_pt_info_fill(struct auxtrace_record *itr,
|
||||
if (perf_pmu__scan_file(intel_pt_pmu, "max_nonturbo_ratio",
|
||||
"%lu", &max_non_turbo_ratio) != 1)
|
||||
max_non_turbo_ratio = 0;
|
||||
if (perf_pmu__scan_file(intel_pt_pmu, "caps/event_trace",
|
||||
"%d", &event_trace) != 1)
|
||||
event_trace = 0;
|
||||
|
||||
filter = intel_pt_find_filter(session->evlist, ptr->intel_pt_pmu);
|
||||
filter_str_len = filter ? strlen(filter) : 0;
|
||||
@ -407,6 +412,8 @@ static int intel_pt_info_fill(struct auxtrace_record *itr,
|
||||
info += len >> 3;
|
||||
}
|
||||
|
||||
*info++ = event_trace;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -46,7 +46,11 @@ struct perf_annotate {
|
||||
struct perf_tool tool;
|
||||
struct perf_session *session;
|
||||
struct annotation_options opts;
|
||||
bool use_tui, use_stdio, use_stdio2, use_gtk;
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
bool use_tui;
|
||||
#endif
|
||||
bool use_stdio, use_stdio2;
|
||||
bool use_gtk;
|
||||
bool skip_missing;
|
||||
bool has_br_stack;
|
||||
bool group_set;
|
||||
@ -190,7 +194,6 @@ static int process_branch_callback(struct evsel *evsel,
|
||||
};
|
||||
|
||||
struct addr_location a;
|
||||
int ret;
|
||||
|
||||
if (machine__resolve(machine, &a, sample) < 0)
|
||||
return -1;
|
||||
@ -203,8 +206,7 @@ static int process_branch_callback(struct evsel *evsel,
|
||||
|
||||
hist__account_cycles(sample->branch_stack, al, sample, false, NULL);
|
||||
|
||||
ret = hist_entry_iter__add(&iter, &a, PERF_MAX_STACK_DEPTH, ann);
|
||||
return ret;
|
||||
return hist_entry_iter__add(&iter, &a, PERF_MAX_STACK_DEPTH, ann);
|
||||
}
|
||||
|
||||
static bool has_annotation(struct perf_annotate *ann)
|
||||
@ -503,7 +505,9 @@ int cmd_annotate(int argc, const char **argv)
|
||||
OPT_BOOLEAN('D', "dump-raw-trace", &dump_trace,
|
||||
"dump raw trace in ASCII"),
|
||||
OPT_BOOLEAN(0, "gtk", &annotate.use_gtk, "Use the GTK interface"),
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
OPT_BOOLEAN(0, "tui", &annotate.use_tui, "Use the TUI interface"),
|
||||
#endif
|
||||
OPT_BOOLEAN(0, "stdio", &annotate.use_stdio, "Use the stdio interface"),
|
||||
OPT_BOOLEAN(0, "stdio2", &annotate.use_stdio2, "Use the stdio interface"),
|
||||
OPT_BOOLEAN(0, "ignore-vmlinux", &symbol_conf.ignore_vmlinux,
|
||||
@ -624,8 +628,10 @@ int cmd_annotate(int argc, const char **argv)
|
||||
|
||||
if (annotate.use_stdio || annotate.use_stdio2)
|
||||
use_browser = 0;
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
else if (annotate.use_tui)
|
||||
use_browser = 1;
|
||||
#endif
|
||||
else if (annotate.use_gtk)
|
||||
use_browser = 2;
|
||||
|
||||
|
||||
@ -44,6 +44,7 @@
|
||||
#include "../perf.h"
|
||||
#include "pmu.h"
|
||||
#include "pmu-hybrid.h"
|
||||
#include "string2.h"
|
||||
|
||||
struct c2c_hists {
|
||||
struct hists hists;
|
||||
@ -1080,7 +1081,7 @@ node_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp,
|
||||
bitmap_zero(set, c2c.cpus_cnt);
|
||||
bitmap_and(set, c2c_he->cpuset, c2c.nodes[node], c2c.cpus_cnt);
|
||||
|
||||
if (!bitmap_weight(set, c2c.cpus_cnt)) {
|
||||
if (bitmap_empty(set, c2c.cpus_cnt)) {
|
||||
if (c2c.node_info == 1) {
|
||||
ret = scnprintf(hpp->buf, hpp->size, "%21s", " ");
|
||||
advance_hpp(hpp, ret);
|
||||
@ -1944,7 +1945,7 @@ static int set_nodestr(struct c2c_hist_entry *c2c_he)
|
||||
if (c2c_he->nodestr)
|
||||
return 0;
|
||||
|
||||
if (bitmap_weight(c2c_he->nodeset, c2c.nodes_cnt)) {
|
||||
if (!bitmap_empty(c2c_he->nodeset, c2c.nodes_cnt)) {
|
||||
len = bitmap_scnprintf(c2c_he->nodeset, c2c.nodes_cnt,
|
||||
buf, sizeof(buf));
|
||||
} else {
|
||||
@ -3025,9 +3026,9 @@ int cmd_c2c(int argc, const char **argv)
|
||||
if (!argc)
|
||||
usage_with_options(c2c_usage, c2c_options);
|
||||
|
||||
if (!strncmp(argv[0], "rec", 3)) {
|
||||
if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
|
||||
return perf_c2c__record(argc, argv);
|
||||
} else if (!strncmp(argv[0], "rep", 3)) {
|
||||
} else if (strlen(argv[0]) > 2 && strstarts("report", argv[0])) {
|
||||
return perf_c2c__report(argc, argv);
|
||||
} else {
|
||||
usage_with_options(c2c_usage, c2c_options);
|
||||
|
||||
@ -62,10 +62,17 @@ static int cmd_data_convert(int argc, const char **argv)
|
||||
pr_err("You cannot specify both --to-ctf and --to-json.\n");
|
||||
return -1;
|
||||
}
|
||||
#ifdef HAVE_LIBBABELTRACE_SUPPORT
|
||||
if (!to_json && !to_ctf) {
|
||||
pr_err("You must specify one of --to-ctf or --to-json.\n");
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
if (!to_json) {
|
||||
pr_err("You must specify --to-json.\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (to_json)
|
||||
return bt_convert__perf2json(input_name, to_json, &opts);
|
||||
|
||||
@ -680,7 +680,8 @@ out:
|
||||
return (done && !workload_exec_errno) ? 0 : -1;
|
||||
}
|
||||
|
||||
static void make_histogram(int buckets[], char *buf, size_t len, char *linebuf)
|
||||
static void make_histogram(int buckets[], char *buf, size_t len, char *linebuf,
|
||||
bool use_nsec)
|
||||
{
|
||||
char *p, *q;
|
||||
char *unit;
|
||||
@ -727,6 +728,9 @@ static void make_histogram(int buckets[], char *buf, size_t len, char *linebuf)
|
||||
if (!unit || strncmp(unit, " us", 3))
|
||||
goto next;
|
||||
|
||||
if (use_nsec)
|
||||
num *= 1000;
|
||||
|
||||
i = log2(num);
|
||||
if (i < 0)
|
||||
i = 0;
|
||||
@ -744,7 +748,7 @@ next:
|
||||
strcat(linebuf, p);
|
||||
}
|
||||
|
||||
static void display_histogram(int buckets[])
|
||||
static void display_histogram(int buckets[], bool use_nsec)
|
||||
{
|
||||
int i;
|
||||
int total = 0;
|
||||
@ -770,12 +774,12 @@ static void display_histogram(int buckets[])
|
||||
for (i = 1; i < NUM_BUCKET - 1; i++) {
|
||||
int start = (1 << (i - 1));
|
||||
int stop = 1 << i;
|
||||
const char *unit = "us";
|
||||
const char *unit = use_nsec ? "ns" : "us";
|
||||
|
||||
if (start >= 1024) {
|
||||
start >>= 10;
|
||||
stop >>= 10;
|
||||
unit = "ms";
|
||||
unit = use_nsec ? "us" : "ms";
|
||||
}
|
||||
bar_len = buckets[i] * bar_total / total;
|
||||
printf(" %4d - %-4d %s | %10d | %.*s%*s |\n",
|
||||
@ -785,8 +789,8 @@ static void display_histogram(int buckets[])
|
||||
|
||||
bar_len = buckets[NUM_BUCKET - 1] * bar_total / total;
|
||||
printf(" %4d - %-4s %s | %10d | %.*s%*s |\n",
|
||||
1, "...", " s", buckets[NUM_BUCKET - 1], bar_len, bar,
|
||||
bar_total - bar_len, "");
|
||||
1, "...", use_nsec ? "ms" : " s", buckets[NUM_BUCKET - 1],
|
||||
bar_len, bar, bar_total - bar_len, "");
|
||||
|
||||
}
|
||||
|
||||
@ -913,7 +917,7 @@ static int __cmd_latency(struct perf_ftrace *ftrace)
|
||||
if (n < 0)
|
||||
break;
|
||||
|
||||
make_histogram(buckets, buf, n, line);
|
||||
make_histogram(buckets, buf, n, line, ftrace->use_nsec);
|
||||
}
|
||||
}
|
||||
|
||||
@ -930,12 +934,12 @@ static int __cmd_latency(struct perf_ftrace *ftrace)
|
||||
int n = read(trace_fd, buf, sizeof(buf) - 1);
|
||||
if (n <= 0)
|
||||
break;
|
||||
make_histogram(buckets, buf, n, line);
|
||||
make_histogram(buckets, buf, n, line, ftrace->use_nsec);
|
||||
}
|
||||
|
||||
read_func_latency(ftrace, buckets);
|
||||
|
||||
display_histogram(buckets);
|
||||
display_histogram(buckets, ftrace->use_nsec);
|
||||
|
||||
out:
|
||||
close(trace_fd);
|
||||
@ -1171,6 +1175,8 @@ int cmd_ftrace(int argc, const char **argv)
|
||||
OPT_BOOLEAN('b', "use-bpf", &ftrace.target.use_bpf,
|
||||
"Use BPF to measure function latency"),
|
||||
#endif
|
||||
OPT_BOOLEAN('n', "--use-nsec", &ftrace.use_nsec,
|
||||
"Use nano-second histogram"),
|
||||
OPT_PARENT(common_options),
|
||||
};
|
||||
const struct option *options = ftrace_options;
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#include "util/synthetic-events.h"
|
||||
#include "util/thread.h"
|
||||
#include "util/namespaces.h"
|
||||
#include "util/util.h"
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <subcmd/parse-options.h>
|
||||
@ -110,7 +111,8 @@ static int perf_event__repipe_op2_synth(struct perf_session *session,
|
||||
|
||||
static int perf_event__repipe_op4_synth(struct perf_session *session,
|
||||
union perf_event *event,
|
||||
u64 data __maybe_unused)
|
||||
u64 data __maybe_unused,
|
||||
const char *str __maybe_unused)
|
||||
{
|
||||
return perf_event__repipe_synth(session->tool, event);
|
||||
}
|
||||
@ -354,7 +356,7 @@ static struct dso *findnew_dso(int pid, int tid, const char *filename,
|
||||
nnsi = nsinfo__copy(nsi);
|
||||
if (nnsi) {
|
||||
nsinfo__put(nsi);
|
||||
nnsi->need_setns = false;
|
||||
nsinfo__clear_need_setns(nnsi);
|
||||
nsi = nnsi;
|
||||
}
|
||||
dso = machine__findnew_vdso(machine, thread);
|
||||
@ -550,6 +552,15 @@ static int dso__read_build_id(struct dso *dso)
|
||||
nsinfo__mountns_enter(dso->nsinfo, &nsc);
|
||||
if (filename__read_build_id(dso->long_name, &dso->bid) > 0)
|
||||
dso->has_build_id = true;
|
||||
else if (dso->nsinfo) {
|
||||
char *new_name;
|
||||
|
||||
new_name = filename_with_chroot(dso->nsinfo->pid,
|
||||
dso->long_name);
|
||||
if (new_name && filename__read_build_id(new_name, &dso->bid) > 0)
|
||||
dso->has_build_id = true;
|
||||
free(new_name);
|
||||
}
|
||||
nsinfo__mountns_exit(&nsc);
|
||||
|
||||
return dso->has_build_id ? 0 : -1;
|
||||
|
||||
@ -1946,7 +1946,7 @@ int cmd_kmem(int argc, const char **argv)
|
||||
kmem_page = 1;
|
||||
}
|
||||
|
||||
if (!strncmp(argv[0], "rec", 3)) {
|
||||
if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
|
||||
symbol__init(NULL);
|
||||
return __cmd_record(argc, argv);
|
||||
}
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include "util/ordered-events.h"
|
||||
#include "util/kvm-stat.h"
|
||||
#include "ui/ui.h"
|
||||
#include "util/string2.h"
|
||||
|
||||
#include <sys/prctl.h>
|
||||
#ifdef HAVE_TIMERFD_SUPPORT
|
||||
@ -771,7 +772,7 @@ static s64 perf_kvm__mmap_read_idx(struct perf_kvm_stat *kvm, int idx,
|
||||
return -1;
|
||||
}
|
||||
|
||||
err = perf_session__queue_event(kvm->session, event, timestamp, 0);
|
||||
err = perf_session__queue_event(kvm->session, event, timestamp, 0, NULL);
|
||||
/*
|
||||
* FIXME: Here we can't consume the event, as perf_session__queue_event will
|
||||
* point to it, and it'll get possibly overwritten by the kernel.
|
||||
@ -1500,10 +1501,10 @@ static int kvm_cmd_stat(const char *file_name, int argc, const char **argv)
|
||||
goto perf_stat;
|
||||
}
|
||||
|
||||
if (!strncmp(argv[1], "rec", 3))
|
||||
if (strlen(argv[1]) > 2 && strstarts("record", argv[1]))
|
||||
return kvm_events_record(&kvm, argc - 1, argv + 1);
|
||||
|
||||
if (!strncmp(argv[1], "rep", 3))
|
||||
if (strlen(argv[1]) > 2 && strstarts("report", argv[1]))
|
||||
return kvm_events_report(&kvm, argc - 1 , argv + 1);
|
||||
|
||||
#ifdef HAVE_TIMERFD_SUPPORT
|
||||
@ -1631,9 +1632,9 @@ int cmd_kvm(int argc, const char **argv)
|
||||
}
|
||||
}
|
||||
|
||||
if (!strncmp(argv[0], "rec", 3))
|
||||
if (strlen(argv[0]) > 2 && strstarts("record", argv[0]))
|
||||
return __cmd_record(file_name, argc, argv);
|
||||
else if (!strncmp(argv[0], "rep", 3))
|
||||
else if (strlen(argv[0]) > 2 && strstarts("report", argv[0]))
|
||||
return __cmd_report(file_name, argc, argv);
|
||||
else if (!strncmp(argv[0], "diff", 4))
|
||||
return cmd_diff(argc, argv);
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
#include "util/session.h"
|
||||
#include "util/tool.h"
|
||||
#include "util/data.h"
|
||||
#include "util/string2.h"
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/prctl.h>
|
||||
@ -38,21 +39,16 @@ static struct perf_session *session;
|
||||
#define LOCKHASH_BITS 12
|
||||
#define LOCKHASH_SIZE (1UL << LOCKHASH_BITS)
|
||||
|
||||
static struct list_head lockhash_table[LOCKHASH_SIZE];
|
||||
static struct hlist_head lockhash_table[LOCKHASH_SIZE];
|
||||
|
||||
#define __lockhashfn(key) hash_long((unsigned long)key, LOCKHASH_BITS)
|
||||
#define lockhashentry(key) (lockhash_table + __lockhashfn((key)))
|
||||
|
||||
struct lock_stat {
|
||||
struct list_head hash_entry;
|
||||
struct hlist_node hash_entry;
|
||||
struct rb_node rb; /* used for sorting */
|
||||
|
||||
/*
|
||||
* FIXME: evsel__intval() returns u64,
|
||||
* so address of lockdep_map should be treated as 64bit.
|
||||
* Is there more better solution?
|
||||
*/
|
||||
void *addr; /* address of lockdep_map, used as ID */
|
||||
u64 addr; /* address of lockdep_map, used as ID */
|
||||
char *name; /* for strcpy(), we cannot use const */
|
||||
|
||||
unsigned int nr_acquire;
|
||||
@ -70,6 +66,7 @@ struct lock_stat {
|
||||
u64 wait_time_max;
|
||||
|
||||
int discard; /* flag of blacklist */
|
||||
int combined;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -106,7 +103,7 @@ struct lock_seq_stat {
|
||||
struct list_head list;
|
||||
int state;
|
||||
u64 prev_event_time;
|
||||
void *addr;
|
||||
u64 addr;
|
||||
|
||||
int read_count;
|
||||
};
|
||||
@ -120,6 +117,8 @@ struct thread_stat {
|
||||
|
||||
static struct rb_root thread_stats;
|
||||
|
||||
static bool combine_locks;
|
||||
|
||||
static struct thread_stat *thread_stat_find(u32 tid)
|
||||
{
|
||||
struct rb_node *node;
|
||||
@ -239,28 +238,65 @@ struct lock_key {
|
||||
* e.g. nr_acquired -> acquired, wait_time_total -> wait_total
|
||||
*/
|
||||
const char *name;
|
||||
/* header: the string printed on the header line */
|
||||
const char *header;
|
||||
/* len: the printing width of the field */
|
||||
int len;
|
||||
/* key: a pointer to function to compare two lock stats for sorting */
|
||||
int (*key)(struct lock_stat*, struct lock_stat*);
|
||||
/* print: a pointer to function to print a given lock stats */
|
||||
void (*print)(struct lock_key*, struct lock_stat*);
|
||||
/* list: list entry to link this */
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
#define PRINT_KEY(member) \
|
||||
static void lock_stat_key_print_ ## member(struct lock_key *key, \
|
||||
struct lock_stat *ls) \
|
||||
{ \
|
||||
pr_info("%*llu", key->len, (unsigned long long)ls->member); \
|
||||
}
|
||||
|
||||
PRINT_KEY(nr_acquired)
|
||||
PRINT_KEY(nr_contended)
|
||||
PRINT_KEY(avg_wait_time)
|
||||
PRINT_KEY(wait_time_total)
|
||||
PRINT_KEY(wait_time_max)
|
||||
|
||||
static void lock_stat_key_print_wait_time_min(struct lock_key *key,
|
||||
struct lock_stat *ls)
|
||||
{
|
||||
u64 wait_time = ls->wait_time_min;
|
||||
|
||||
if (wait_time == ULLONG_MAX)
|
||||
wait_time = 0;
|
||||
|
||||
pr_info("%*"PRIu64, key->len, wait_time);
|
||||
}
|
||||
|
||||
|
||||
static const char *sort_key = "acquired";
|
||||
|
||||
static int (*compare)(struct lock_stat *, struct lock_stat *);
|
||||
|
||||
static struct rb_root sorted; /* place to store intermediate data */
|
||||
static struct rb_root result; /* place to store sorted data */
|
||||
|
||||
#define DEF_KEY_LOCK(name, fn_suffix) \
|
||||
{ #name, lock_stat_key_ ## fn_suffix }
|
||||
static LIST_HEAD(lock_keys);
|
||||
static const char *output_fields;
|
||||
|
||||
#define DEF_KEY_LOCK(name, header, fn_suffix, len) \
|
||||
{ #name, header, len, lock_stat_key_ ## fn_suffix, lock_stat_key_print_ ## fn_suffix, {} }
|
||||
struct lock_key keys[] = {
|
||||
DEF_KEY_LOCK(acquired, nr_acquired),
|
||||
DEF_KEY_LOCK(contended, nr_contended),
|
||||
DEF_KEY_LOCK(avg_wait, avg_wait_time),
|
||||
DEF_KEY_LOCK(wait_total, wait_time_total),
|
||||
DEF_KEY_LOCK(wait_min, wait_time_min),
|
||||
DEF_KEY_LOCK(wait_max, wait_time_max),
|
||||
DEF_KEY_LOCK(acquired, "acquired", nr_acquired, 10),
|
||||
DEF_KEY_LOCK(contended, "contended", nr_contended, 10),
|
||||
DEF_KEY_LOCK(avg_wait, "avg wait (ns)", avg_wait_time, 15),
|
||||
DEF_KEY_LOCK(wait_total, "total wait (ns)", wait_time_total, 15),
|
||||
DEF_KEY_LOCK(wait_max, "max wait (ns)", wait_time_max, 15),
|
||||
DEF_KEY_LOCK(wait_min, "min wait (ns)", wait_time_min, 15),
|
||||
|
||||
/* extra comparisons much complicated should be here */
|
||||
|
||||
{ NULL, NULL }
|
||||
{ }
|
||||
};
|
||||
|
||||
static int select_key(void)
|
||||
@ -270,15 +306,126 @@ static int select_key(void)
|
||||
for (i = 0; keys[i].name; i++) {
|
||||
if (!strcmp(keys[i].name, sort_key)) {
|
||||
compare = keys[i].key;
|
||||
|
||||
/* selected key should be in the output fields */
|
||||
if (list_empty(&keys[i].list))
|
||||
list_add_tail(&keys[i].list, &lock_keys);
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
pr_err("Unknown compare key: %s\n", sort_key);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int add_output_field(struct list_head *head, char *name)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; keys[i].name; i++) {
|
||||
if (strcmp(keys[i].name, name))
|
||||
continue;
|
||||
|
||||
/* prevent double link */
|
||||
if (list_empty(&keys[i].list))
|
||||
list_add_tail(&keys[i].list, head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
pr_err("Unknown output field: %s\n", name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int setup_output_field(const char *str)
|
||||
{
|
||||
char *tok, *tmp, *orig;
|
||||
int i, ret = 0;
|
||||
|
||||
/* no output field given: use all of them */
|
||||
if (str == NULL) {
|
||||
for (i = 0; keys[i].name; i++)
|
||||
list_add_tail(&keys[i].list, &lock_keys);
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; keys[i].name; i++)
|
||||
INIT_LIST_HEAD(&keys[i].list);
|
||||
|
||||
orig = tmp = strdup(str);
|
||||
if (orig == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
while ((tok = strsep(&tmp, ",")) != NULL){
|
||||
ret = add_output_field(&lock_keys, tok);
|
||||
if (ret < 0)
|
||||
break;
|
||||
}
|
||||
free(orig);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void combine_lock_stats(struct lock_stat *st)
|
||||
{
|
||||
struct rb_node **rb = &sorted.rb_node;
|
||||
struct rb_node *parent = NULL;
|
||||
struct lock_stat *p;
|
||||
int ret;
|
||||
|
||||
while (*rb) {
|
||||
p = container_of(*rb, struct lock_stat, rb);
|
||||
parent = *rb;
|
||||
|
||||
if (st->name && p->name)
|
||||
ret = strcmp(st->name, p->name);
|
||||
else
|
||||
ret = !!st->name - !!p->name;
|
||||
|
||||
if (ret == 0) {
|
||||
if (st->discard)
|
||||
goto out;
|
||||
|
||||
p->nr_acquired += st->nr_acquired;
|
||||
p->nr_contended += st->nr_contended;
|
||||
p->wait_time_total += st->wait_time_total;
|
||||
|
||||
if (p->nr_contended)
|
||||
p->avg_wait_time = p->wait_time_total / p->nr_contended;
|
||||
|
||||
if (p->wait_time_min > st->wait_time_min)
|
||||
p->wait_time_min = st->wait_time_min;
|
||||
if (p->wait_time_max < st->wait_time_max)
|
||||
p->wait_time_max = st->wait_time_max;
|
||||
|
||||
/* now it got a new !discard record */
|
||||
p->discard = 0;
|
||||
|
||||
out:
|
||||
st->combined = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
if (ret < 0)
|
||||
rb = &(*rb)->rb_left;
|
||||
else
|
||||
rb = &(*rb)->rb_right;
|
||||
}
|
||||
|
||||
rb_link_node(&st->rb, parent, rb);
|
||||
rb_insert_color(&st->rb, &sorted);
|
||||
|
||||
if (st->discard) {
|
||||
st->nr_acquired = 0;
|
||||
st->nr_contended = 0;
|
||||
st->wait_time_total = 0;
|
||||
st->avg_wait_time = 0;
|
||||
st->wait_time_min = ULLONG_MAX;
|
||||
st->wait_time_max = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void insert_to_result(struct lock_stat *st,
|
||||
int (*bigger)(struct lock_stat *, struct lock_stat *))
|
||||
{
|
||||
@ -286,6 +433,9 @@ static void insert_to_result(struct lock_stat *st,
|
||||
struct rb_node *parent = NULL;
|
||||
struct lock_stat *p;
|
||||
|
||||
if (combine_locks && st->combined)
|
||||
return;
|
||||
|
||||
while (*rb) {
|
||||
p = container_of(*rb, struct lock_stat, rb);
|
||||
parent = *rb;
|
||||
@ -315,12 +465,12 @@ static struct lock_stat *pop_from_result(void)
|
||||
return container_of(node, struct lock_stat, rb);
|
||||
}
|
||||
|
||||
static struct lock_stat *lock_stat_findnew(void *addr, const char *name)
|
||||
static struct lock_stat *lock_stat_findnew(u64 addr, const char *name)
|
||||
{
|
||||
struct list_head *entry = lockhashentry(addr);
|
||||
struct hlist_head *entry = lockhashentry(addr);
|
||||
struct lock_stat *ret, *new;
|
||||
|
||||
list_for_each_entry(ret, entry, hash_entry) {
|
||||
hlist_for_each_entry(ret, entry, hash_entry) {
|
||||
if (ret->addr == addr)
|
||||
return ret;
|
||||
}
|
||||
@ -339,7 +489,7 @@ static struct lock_stat *lock_stat_findnew(void *addr, const char *name)
|
||||
strcpy(new->name, name);
|
||||
new->wait_time_min = ULLONG_MAX;
|
||||
|
||||
list_add(&new->hash_entry, entry);
|
||||
hlist_add_head(&new->hash_entry, entry);
|
||||
return new;
|
||||
|
||||
alloc_failed:
|
||||
@ -361,7 +511,7 @@ struct trace_lock_handler {
|
||||
struct perf_sample *sample);
|
||||
};
|
||||
|
||||
static struct lock_seq_stat *get_seq(struct thread_stat *ts, void *addr)
|
||||
static struct lock_seq_stat *get_seq(struct thread_stat *ts, u64 addr)
|
||||
{
|
||||
struct lock_seq_stat *seq;
|
||||
|
||||
@ -400,16 +550,13 @@ enum acquire_flags {
|
||||
static int report_lock_acquire_event(struct evsel *evsel,
|
||||
struct perf_sample *sample)
|
||||
{
|
||||
void *addr;
|
||||
struct lock_stat *ls;
|
||||
struct thread_stat *ts;
|
||||
struct lock_seq_stat *seq;
|
||||
const char *name = evsel__strval(evsel, sample, "name");
|
||||
u64 tmp = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
u64 addr = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
int flag = evsel__intval(evsel, sample, "flags");
|
||||
|
||||
memcpy(&addr, &tmp, sizeof(void *));
|
||||
|
||||
ls = lock_stat_findnew(addr, name);
|
||||
if (!ls)
|
||||
return -ENOMEM;
|
||||
@ -472,15 +619,12 @@ end:
|
||||
static int report_lock_acquired_event(struct evsel *evsel,
|
||||
struct perf_sample *sample)
|
||||
{
|
||||
void *addr;
|
||||
struct lock_stat *ls;
|
||||
struct thread_stat *ts;
|
||||
struct lock_seq_stat *seq;
|
||||
u64 contended_term;
|
||||
const char *name = evsel__strval(evsel, sample, "name");
|
||||
u64 tmp = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
|
||||
memcpy(&addr, &tmp, sizeof(void *));
|
||||
u64 addr = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
|
||||
ls = lock_stat_findnew(addr, name);
|
||||
if (!ls)
|
||||
@ -535,14 +679,11 @@ end:
|
||||
static int report_lock_contended_event(struct evsel *evsel,
|
||||
struct perf_sample *sample)
|
||||
{
|
||||
void *addr;
|
||||
struct lock_stat *ls;
|
||||
struct thread_stat *ts;
|
||||
struct lock_seq_stat *seq;
|
||||
const char *name = evsel__strval(evsel, sample, "name");
|
||||
u64 tmp = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
|
||||
memcpy(&addr, &tmp, sizeof(void *));
|
||||
u64 addr = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
|
||||
ls = lock_stat_findnew(addr, name);
|
||||
if (!ls)
|
||||
@ -590,14 +731,11 @@ end:
|
||||
static int report_lock_release_event(struct evsel *evsel,
|
||||
struct perf_sample *sample)
|
||||
{
|
||||
void *addr;
|
||||
struct lock_stat *ls;
|
||||
struct thread_stat *ts;
|
||||
struct lock_seq_stat *seq;
|
||||
const char *name = evsel__strval(evsel, sample, "name");
|
||||
u64 tmp = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
|
||||
memcpy(&addr, &tmp, sizeof(void *));
|
||||
u64 addr = evsel__intval(evsel, sample, "lockdep_addr");
|
||||
|
||||
ls = lock_stat_findnew(addr, name);
|
||||
if (!ls)
|
||||
@ -704,18 +842,13 @@ static void print_bad_events(int bad, int total)
|
||||
static void print_result(void)
|
||||
{
|
||||
struct lock_stat *st;
|
||||
struct lock_key *key;
|
||||
char cut_name[20];
|
||||
int bad, total;
|
||||
|
||||
pr_info("%20s ", "Name");
|
||||
pr_info("%10s ", "acquired");
|
||||
pr_info("%10s ", "contended");
|
||||
|
||||
pr_info("%15s ", "avg wait (ns)");
|
||||
pr_info("%15s ", "total wait (ns)");
|
||||
pr_info("%15s ", "max wait (ns)");
|
||||
pr_info("%15s ", "min wait (ns)");
|
||||
|
||||
list_for_each_entry(key, &lock_keys, list)
|
||||
pr_info("%*s ", key->len, key->header);
|
||||
pr_info("\n\n");
|
||||
|
||||
bad = total = 0;
|
||||
@ -727,7 +860,7 @@ static void print_result(void)
|
||||
}
|
||||
bzero(cut_name, 20);
|
||||
|
||||
if (strlen(st->name) < 16) {
|
||||
if (strlen(st->name) < 20) {
|
||||
/* output raw name */
|
||||
pr_info("%20s ", st->name);
|
||||
} else {
|
||||
@ -740,14 +873,10 @@ static void print_result(void)
|
||||
pr_info("%20s ", cut_name);
|
||||
}
|
||||
|
||||
pr_info("%10u ", st->nr_acquired);
|
||||
pr_info("%10u ", st->nr_contended);
|
||||
|
||||
pr_info("%15" PRIu64 " ", st->avg_wait_time);
|
||||
pr_info("%15" PRIu64 " ", st->wait_time_total);
|
||||
pr_info("%15" PRIu64 " ", st->wait_time_max);
|
||||
pr_info("%15" PRIu64 " ", st->wait_time_min == ULLONG_MAX ?
|
||||
0 : st->wait_time_min);
|
||||
list_for_each_entry(key, &lock_keys, list) {
|
||||
key->print(key, st);
|
||||
pr_info(" ");
|
||||
}
|
||||
pr_info("\n");
|
||||
}
|
||||
|
||||
@ -774,6 +903,21 @@ static void dump_threads(void)
|
||||
}
|
||||
}
|
||||
|
||||
static int compare_maps(struct lock_stat *a, struct lock_stat *b)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (a->name && b->name)
|
||||
ret = strcmp(a->name, b->name);
|
||||
else
|
||||
ret = !!a->name - !!b->name;
|
||||
|
||||
if (!ret)
|
||||
return a->addr < b->addr;
|
||||
else
|
||||
return ret < 0;
|
||||
}
|
||||
|
||||
static void dump_map(void)
|
||||
{
|
||||
unsigned int i;
|
||||
@ -781,10 +925,13 @@ static void dump_map(void)
|
||||
|
||||
pr_info("Address of instance: name of class\n");
|
||||
for (i = 0; i < LOCKHASH_SIZE; i++) {
|
||||
list_for_each_entry(st, &lockhash_table[i], hash_entry) {
|
||||
pr_info(" %p: %s\n", st->addr, st->name);
|
||||
hlist_for_each_entry(st, &lockhash_table[i], hash_entry) {
|
||||
insert_to_result(st, compare_maps);
|
||||
}
|
||||
}
|
||||
|
||||
while ((st = pop_from_result()))
|
||||
pr_info(" %#llx: %s\n", (unsigned long long)st->addr, st->name);
|
||||
}
|
||||
|
||||
static int dump_info(void)
|
||||
@ -832,13 +979,28 @@ static int process_sample_event(struct perf_tool *tool __maybe_unused,
|
||||
return err;
|
||||
}
|
||||
|
||||
static void combine_result(void)
|
||||
{
|
||||
unsigned int i;
|
||||
struct lock_stat *st;
|
||||
|
||||
if (!combine_locks)
|
||||
return;
|
||||
|
||||
for (i = 0; i < LOCKHASH_SIZE; i++) {
|
||||
hlist_for_each_entry(st, &lockhash_table[i], hash_entry) {
|
||||
combine_lock_stats(st);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void sort_result(void)
|
||||
{
|
||||
unsigned int i;
|
||||
struct lock_stat *st;
|
||||
|
||||
for (i = 0; i < LOCKHASH_SIZE; i++) {
|
||||
list_for_each_entry(st, &lockhash_table[i], hash_entry) {
|
||||
hlist_for_each_entry(st, &lockhash_table[i], hash_entry) {
|
||||
insert_to_result(st, compare);
|
||||
}
|
||||
}
|
||||
@ -884,6 +1046,9 @@ static int __cmd_report(bool display_info)
|
||||
goto out_delete;
|
||||
}
|
||||
|
||||
if (setup_output_field(output_fields))
|
||||
goto out_delete;
|
||||
|
||||
if (select_key())
|
||||
goto out_delete;
|
||||
|
||||
@ -895,6 +1060,7 @@ static int __cmd_report(bool display_info)
|
||||
if (display_info) /* used for info subcommand */
|
||||
err = dump_info();
|
||||
else {
|
||||
combine_result();
|
||||
sort_result();
|
||||
print_result();
|
||||
}
|
||||
@ -907,7 +1073,7 @@ out_delete:
|
||||
static int __cmd_record(int argc, const char **argv)
|
||||
{
|
||||
const char *record_args[] = {
|
||||
"record", "-R", "-m", "1024", "-c", "1",
|
||||
"record", "-R", "-m", "1024", "-c", "1", "--synth", "no",
|
||||
};
|
||||
unsigned int rec_argc, i, j, ret;
|
||||
const char **rec_argv;
|
||||
@ -968,7 +1134,11 @@ int cmd_lock(int argc, const char **argv)
|
||||
const struct option report_options[] = {
|
||||
OPT_STRING('k', "key", &sort_key, "acquired",
|
||||
"key for sorting (acquired / contended / avg_wait / wait_total / wait_max / wait_min)"),
|
||||
OPT_STRING('F', "field", &output_fields, NULL,
|
||||
"output fields (acquired / contended / avg_wait / wait_total / wait_max / wait_min)"),
|
||||
/* TODO: type */
|
||||
OPT_BOOLEAN('c', "combine-locks", &combine_locks,
|
||||
"combine locks in the same class"),
|
||||
OPT_PARENT(lock_options)
|
||||
};
|
||||
|
||||
@ -990,16 +1160,16 @@ int cmd_lock(int argc, const char **argv)
|
||||
int rc = 0;
|
||||
|
||||
for (i = 0; i < LOCKHASH_SIZE; i++)
|
||||
INIT_LIST_HEAD(lockhash_table + i);
|
||||
INIT_HLIST_HEAD(lockhash_table + i);
|
||||
|
||||
argc = parse_options_subcommand(argc, argv, lock_options, lock_subcommands,
|
||||
lock_usage, PARSE_OPT_STOP_AT_NON_OPTION);
|
||||
if (!argc)
|
||||
usage_with_options(lock_usage, lock_options);
|
||||
|
||||
if (!strncmp(argv[0], "rec", 3)) {
|
||||
if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
|
||||
return __cmd_record(argc, argv);
|
||||
} else if (!strncmp(argv[0], "report", 6)) {
|
||||
} else if (strlen(argv[0]) > 2 && strstarts("report", argv[0])) {
|
||||
trace_handler = &report_lock_ops;
|
||||
if (argc) {
|
||||
argc = parse_options(argc, argv,
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#include "util/symbol.h"
|
||||
#include "util/pmu.h"
|
||||
#include "util/pmu-hybrid.h"
|
||||
#include "util/string2.h"
|
||||
#include <linux/err.h>
|
||||
|
||||
#define MEM_OPERATION_LOAD 0x1
|
||||
@ -496,9 +497,9 @@ int cmd_mem(int argc, const char **argv)
|
||||
mem.input_name = "perf.data";
|
||||
}
|
||||
|
||||
if (!strncmp(argv[0], "rec", 3))
|
||||
if (strlen(argv[0]) > 2 && strstarts("record", argv[0]))
|
||||
return __cmd_record(argc, argv, &mem);
|
||||
else if (!strncmp(argv[0], "rep", 3))
|
||||
else if (strlen(argv[0]) > 2 && strstarts("report", argv[0]))
|
||||
return report_events(argc, argv, &mem);
|
||||
else
|
||||
usage_with_options(mem_usage, mem_options);
|
||||
|
||||
@ -217,7 +217,7 @@ static int opt_set_target_ns(const struct option *opt __maybe_unused,
|
||||
return ret;
|
||||
}
|
||||
nsip = nsinfo__new(ns_pid);
|
||||
if (nsip && nsip->need_setns)
|
||||
if (nsip && nsinfo__need_setns(nsip))
|
||||
params.nsi = nsinfo__get(nsip);
|
||||
nsinfo__put(nsip);
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -71,7 +71,11 @@ struct report {
|
||||
struct perf_tool tool;
|
||||
struct perf_session *session;
|
||||
struct evswitch evswitch;
|
||||
bool use_tui, use_gtk, use_stdio;
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
bool use_tui;
|
||||
#endif
|
||||
bool use_gtk;
|
||||
bool use_stdio;
|
||||
bool show_full_info;
|
||||
bool show_threads;
|
||||
bool inverted_callchain;
|
||||
@ -1206,7 +1210,9 @@ int cmd_report(int argc, const char **argv)
|
||||
"Show per-thread event counters"),
|
||||
OPT_STRING(0, "pretty", &report.pretty_printing_style, "key",
|
||||
"pretty printing style key: normal raw"),
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
OPT_BOOLEAN(0, "tui", &report.use_tui, "Use the TUI interface"),
|
||||
#endif
|
||||
OPT_BOOLEAN(0, "gtk", &report.use_gtk, "Use the GTK2 interface"),
|
||||
OPT_BOOLEAN(0, "stdio", &report.use_stdio,
|
||||
"Use the stdio interface"),
|
||||
@ -1492,8 +1498,10 @@ repeat:
|
||||
|
||||
if (report.use_stdio)
|
||||
use_browser = 0;
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
else if (report.use_tui)
|
||||
use_browser = 1;
|
||||
#endif
|
||||
else if (report.use_gtk)
|
||||
use_browser = 2;
|
||||
|
||||
|
||||
@ -3561,7 +3561,7 @@ int cmd_sched(int argc, const char **argv)
|
||||
if (!strcmp(argv[0], "script"))
|
||||
return cmd_script(argc, argv);
|
||||
|
||||
if (!strncmp(argv[0], "rec", 3)) {
|
||||
if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
|
||||
return __cmd_record(argc, argv);
|
||||
} else if (!strncmp(argv[0], "lat", 3)) {
|
||||
sched.tp_handler = &lat_ops;
|
||||
@ -3581,7 +3581,7 @@ int cmd_sched(int argc, const char **argv)
|
||||
sched.tp_handler = &map_ops;
|
||||
setup_sorting(&sched, latency_options, latency_usage);
|
||||
return perf_sched__map(&sched);
|
||||
} else if (!strncmp(argv[0], "rep", 3)) {
|
||||
} else if (strlen(argv[0]) > 2 && strstarts("replay", argv[0])) {
|
||||
sched.tp_handler = &replay_ops;
|
||||
if (argc) {
|
||||
argc = parse_options(argc, argv, replay_options, replay_usage, 0);
|
||||
|
||||
@ -124,6 +124,7 @@ enum perf_output_field {
|
||||
PERF_OUTPUT_DATA_PAGE_SIZE = 1ULL << 33,
|
||||
PERF_OUTPUT_CODE_PAGE_SIZE = 1ULL << 34,
|
||||
PERF_OUTPUT_INS_LAT = 1ULL << 35,
|
||||
PERF_OUTPUT_BRSTACKINSNLEN = 1ULL << 36,
|
||||
};
|
||||
|
||||
struct perf_script {
|
||||
@ -191,6 +192,7 @@ struct output_option {
|
||||
{.str = "data_page_size", .field = PERF_OUTPUT_DATA_PAGE_SIZE},
|
||||
{.str = "code_page_size", .field = PERF_OUTPUT_CODE_PAGE_SIZE},
|
||||
{.str = "ins_lat", .field = PERF_OUTPUT_INS_LAT},
|
||||
{.str = "brstackinsnlen", .field = PERF_OUTPUT_BRSTACKINSNLEN},
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -488,7 +490,7 @@ static int evsel__check_attr(struct evsel *evsel, struct perf_session *session)
|
||||
"selected. Hence, no address to lookup the source line number.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (PRINT_FIELD(BRSTACKINSN) && !allow_user_set &&
|
||||
if ((PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN)) && !allow_user_set &&
|
||||
!(evlist__combined_branch_type(session->evlist) & PERF_SAMPLE_BRANCH_ANY)) {
|
||||
pr_err("Display of branch stack assembler requested, but non all-branch filter set\n"
|
||||
"Hint: run 'perf record -b ...'\n");
|
||||
@ -857,6 +859,16 @@ mispred_str(struct branch_entry *br)
|
||||
return br->flags.predicted ? 'P' : 'M';
|
||||
}
|
||||
|
||||
static int print_bstack_flags(FILE *fp, struct branch_entry *br)
|
||||
{
|
||||
return fprintf(fp, "/%c/%c/%c/%d/%s ",
|
||||
mispred_str(br),
|
||||
br->flags.in_tx ? 'X' : '-',
|
||||
br->flags.abort ? 'A' : '-',
|
||||
br->flags.cycles,
|
||||
br->flags.type ? branch_type_name(br->flags.type) : "-");
|
||||
}
|
||||
|
||||
static int perf_sample__fprintf_brstack(struct perf_sample *sample,
|
||||
struct thread *thread,
|
||||
struct perf_event_attr *attr, FILE *fp)
|
||||
@ -895,11 +907,7 @@ static int perf_sample__fprintf_brstack(struct perf_sample *sample,
|
||||
printed += fprintf(fp, ")");
|
||||
}
|
||||
|
||||
printed += fprintf(fp, "/%c/%c/%c/%d ",
|
||||
mispred_str(entries + i),
|
||||
entries[i].flags.in_tx ? 'X' : '-',
|
||||
entries[i].flags.abort ? 'A' : '-',
|
||||
entries[i].flags.cycles);
|
||||
printed += print_bstack_flags(fp, entries + i);
|
||||
}
|
||||
|
||||
return printed;
|
||||
@ -941,11 +949,7 @@ static int perf_sample__fprintf_brstacksym(struct perf_sample *sample,
|
||||
printed += map__fprintf_dsoname(alt.map, fp);
|
||||
printed += fprintf(fp, ")");
|
||||
}
|
||||
printed += fprintf(fp, "/%c/%c/%c/%d ",
|
||||
mispred_str(entries + i),
|
||||
entries[i].flags.in_tx ? 'X' : '-',
|
||||
entries[i].flags.abort ? 'A' : '-',
|
||||
entries[i].flags.cycles);
|
||||
printed += print_bstack_flags(fp, entries + i);
|
||||
}
|
||||
|
||||
return printed;
|
||||
@ -991,11 +995,7 @@ static int perf_sample__fprintf_brstackoff(struct perf_sample *sample,
|
||||
printed += map__fprintf_dsoname(alt.map, fp);
|
||||
printed += fprintf(fp, ")");
|
||||
}
|
||||
printed += fprintf(fp, "/%c/%c/%c/%d ",
|
||||
mispred_str(entries + i),
|
||||
entries[i].flags.in_tx ? 'X' : '-',
|
||||
entries[i].flags.abort ? 'A' : '-',
|
||||
entries[i].flags.cycles);
|
||||
printed += print_bstack_flags(fp, entries + i);
|
||||
}
|
||||
|
||||
return printed;
|
||||
@ -1122,10 +1122,17 @@ static int print_srccode(struct thread *thread, u8 cpumode, uint64_t addr)
|
||||
|
||||
static int ip__fprintf_jump(uint64_t ip, struct branch_entry *en,
|
||||
struct perf_insn *x, u8 *inbuf, int len,
|
||||
int insn, FILE *fp, int *total_cycles)
|
||||
int insn, FILE *fp, int *total_cycles,
|
||||
struct perf_event_attr *attr)
|
||||
{
|
||||
int printed = fprintf(fp, "\t%016" PRIx64 "\t%-30s\t#%s%s%s%s", ip,
|
||||
dump_insn(x, ip, inbuf, len, NULL),
|
||||
int ilen = 0;
|
||||
int printed = fprintf(fp, "\t%016" PRIx64 "\t%-30s\t", ip,
|
||||
dump_insn(x, ip, inbuf, len, &ilen));
|
||||
|
||||
if (PRINT_FIELD(BRSTACKINSNLEN))
|
||||
printed += fprintf(fp, "ilen: %d\t", ilen);
|
||||
|
||||
printed += fprintf(fp, "#%s%s%s%s",
|
||||
en->flags.predicted ? " PRED" : "",
|
||||
en->flags.mispred ? " MISPRED" : "",
|
||||
en->flags.in_tx ? " INTX" : "",
|
||||
@ -1211,7 +1218,8 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
|
||||
printed += ip__fprintf_sym(entries[nr - 1].from, thread,
|
||||
x.cpumode, x.cpu, &lastsym, attr, fp);
|
||||
printed += ip__fprintf_jump(entries[nr - 1].from, &entries[nr - 1],
|
||||
&x, buffer, len, 0, fp, &total_cycles);
|
||||
&x, buffer, len, 0, fp, &total_cycles,
|
||||
attr);
|
||||
if (PRINT_FIELD(SRCCODE))
|
||||
printed += print_srccode(thread, x.cpumode, entries[nr - 1].from);
|
||||
}
|
||||
@ -1242,14 +1250,17 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
|
||||
printed += ip__fprintf_sym(ip, thread, x.cpumode, x.cpu, &lastsym, attr, fp);
|
||||
if (ip == end) {
|
||||
printed += ip__fprintf_jump(ip, &entries[i], &x, buffer + off, len - off, ++insn, fp,
|
||||
&total_cycles);
|
||||
&total_cycles, attr);
|
||||
if (PRINT_FIELD(SRCCODE))
|
||||
printed += print_srccode(thread, x.cpumode, ip);
|
||||
break;
|
||||
} else {
|
||||
ilen = 0;
|
||||
printed += fprintf(fp, "\t%016" PRIx64 "\t%s\n", ip,
|
||||
printed += fprintf(fp, "\t%016" PRIx64 "\t%s", ip,
|
||||
dump_insn(&x, ip, buffer + off, len - off, &ilen));
|
||||
if (PRINT_FIELD(BRSTACKINSNLEN))
|
||||
printed += fprintf(fp, "\tilen: %d", ilen);
|
||||
printed += fprintf(fp, "\n");
|
||||
if (ilen == 0)
|
||||
break;
|
||||
if (PRINT_FIELD(SRCCODE))
|
||||
@ -1292,16 +1303,23 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
|
||||
machine, thread, &x.is64bit, &x.cpumode, false);
|
||||
if (len <= 0)
|
||||
goto out;
|
||||
printed += fprintf(fp, "\t%016" PRIx64 "\t%s\n", sample->ip,
|
||||
dump_insn(&x, sample->ip, buffer, len, NULL));
|
||||
ilen = 0;
|
||||
printed += fprintf(fp, "\t%016" PRIx64 "\t%s", sample->ip,
|
||||
dump_insn(&x, sample->ip, buffer, len, &ilen));
|
||||
if (PRINT_FIELD(BRSTACKINSNLEN))
|
||||
printed += fprintf(fp, "\tilen: %d", ilen);
|
||||
printed += fprintf(fp, "\n");
|
||||
if (PRINT_FIELD(SRCCODE))
|
||||
print_srccode(thread, x.cpumode, sample->ip);
|
||||
goto out;
|
||||
}
|
||||
for (off = 0; off <= end - start; off += ilen) {
|
||||
ilen = 0;
|
||||
printed += fprintf(fp, "\t%016" PRIx64 "\t%s\n", start + off,
|
||||
printed += fprintf(fp, "\t%016" PRIx64 "\t%s", start + off,
|
||||
dump_insn(&x, start + off, buffer + off, len - off, &ilen));
|
||||
if (PRINT_FIELD(BRSTACKINSNLEN))
|
||||
printed += fprintf(fp, "\tilen: %d", ilen);
|
||||
printed += fprintf(fp, "\n");
|
||||
if (ilen == 0)
|
||||
break;
|
||||
if (arch_is_branch(buffer + off, len - off, x.is64bit) && start + off != sample->ip) {
|
||||
@ -1459,7 +1477,7 @@ static int perf_sample__fprintf_insn(struct perf_sample *sample,
|
||||
for (i = 0; i < sample->insn_len; i++)
|
||||
printed += fprintf(fp, " %02x", (unsigned char)sample->insn[i]);
|
||||
}
|
||||
if (PRINT_FIELD(BRSTACKINSN))
|
||||
if (PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN))
|
||||
printed += perf_sample__fprintf_brstackinsn(sample, thread, attr, machine, fp);
|
||||
|
||||
return printed;
|
||||
@ -1579,26 +1597,34 @@ static const char *sample_flags_to_name(u32 flags)
|
||||
|
||||
int perf_sample__sprintf_flags(u32 flags, char *str, size_t sz)
|
||||
{
|
||||
u32 xf = PERF_IP_FLAG_IN_TX | PERF_IP_FLAG_INTR_DISABLE |
|
||||
PERF_IP_FLAG_INTR_TOGGLE;
|
||||
const char *chars = PERF_IP_FLAG_CHARS;
|
||||
const size_t n = strlen(PERF_IP_FLAG_CHARS);
|
||||
bool in_tx = flags & PERF_IP_FLAG_IN_TX;
|
||||
const char *name = NULL;
|
||||
size_t i, pos = 0;
|
||||
char xs[16] = {0};
|
||||
|
||||
name = sample_flags_to_name(flags & ~PERF_IP_FLAG_IN_TX);
|
||||
if (flags & xf)
|
||||
snprintf(xs, sizeof(xs), "(%s%s%s)",
|
||||
flags & PERF_IP_FLAG_IN_TX ? "x" : "",
|
||||
flags & PERF_IP_FLAG_INTR_DISABLE ? "D" : "",
|
||||
flags & PERF_IP_FLAG_INTR_TOGGLE ? "t" : "");
|
||||
|
||||
name = sample_flags_to_name(flags & ~xf);
|
||||
if (name)
|
||||
return snprintf(str, sz, "%-15s%4s", name, in_tx ? "(x)" : "");
|
||||
return snprintf(str, sz, "%-15s%6s", name, xs);
|
||||
|
||||
if (flags & PERF_IP_FLAG_TRACE_BEGIN) {
|
||||
name = sample_flags_to_name(flags & ~(PERF_IP_FLAG_IN_TX | PERF_IP_FLAG_TRACE_BEGIN));
|
||||
name = sample_flags_to_name(flags & ~(xf | PERF_IP_FLAG_TRACE_BEGIN));
|
||||
if (name)
|
||||
return snprintf(str, sz, "tr strt %-7s%4s", name, in_tx ? "(x)" : "");
|
||||
return snprintf(str, sz, "tr strt %-7s%6s", name, xs);
|
||||
}
|
||||
|
||||
if (flags & PERF_IP_FLAG_TRACE_END) {
|
||||
name = sample_flags_to_name(flags & ~(PERF_IP_FLAG_IN_TX | PERF_IP_FLAG_TRACE_END));
|
||||
name = sample_flags_to_name(flags & ~(xf | PERF_IP_FLAG_TRACE_END));
|
||||
if (name)
|
||||
return snprintf(str, sz, "tr end %-7s%4s", name, in_tx ? "(x)" : "");
|
||||
return snprintf(str, sz, "tr end %-7s%6s", name, xs);
|
||||
}
|
||||
|
||||
for (i = 0; i < n; i++, flags >>= 1) {
|
||||
@ -1620,7 +1646,7 @@ static int perf_sample__fprintf_flags(u32 flags, FILE *fp)
|
||||
char str[SAMPLE_FLAGS_BUF_SIZE];
|
||||
|
||||
perf_sample__sprintf_flags(flags, str, sizeof(str));
|
||||
return fprintf(fp, " %-19s ", str);
|
||||
return fprintf(fp, " %-21s ", str);
|
||||
}
|
||||
|
||||
struct printer_data {
|
||||
@ -1811,6 +1837,56 @@ static int perf_sample__fprintf_synth_psb(struct perf_sample *sample, FILE *fp)
|
||||
return len + perf_sample__fprintf_pt_spacing(len, fp);
|
||||
}
|
||||
|
||||
/* Intel PT Event Trace */
|
||||
static int perf_sample__fprintf_synth_evt(struct perf_sample *sample, FILE *fp)
|
||||
{
|
||||
struct perf_synth_intel_evt *data = perf_sample__synth_ptr(sample);
|
||||
const char *cfe[32] = {NULL, "INTR", "IRET", "SMI", "RSM", "SIPI",
|
||||
"INIT", "VMENTRY", "VMEXIT", "VMEXIT_INTR",
|
||||
"SHUTDOWN"};
|
||||
const char *evd[64] = {"PFA", "VMXQ", "VMXR"};
|
||||
const char *s;
|
||||
int len, i;
|
||||
|
||||
if (perf_sample__bad_synth_size(sample, *data))
|
||||
return 0;
|
||||
|
||||
s = cfe[data->type];
|
||||
if (s) {
|
||||
len = fprintf(fp, " cfe: %s IP: %d vector: %u",
|
||||
s, data->ip, data->vector);
|
||||
} else {
|
||||
len = fprintf(fp, " cfe: %u IP: %d vector: %u",
|
||||
data->type, data->ip, data->vector);
|
||||
}
|
||||
for (i = 0; i < data->evd_cnt; i++) {
|
||||
unsigned int et = data->evd[i].evd_type & 0x3f;
|
||||
|
||||
s = evd[et];
|
||||
if (s) {
|
||||
len += fprintf(fp, " %s: %#" PRIx64,
|
||||
s, data->evd[i].payload);
|
||||
} else {
|
||||
len += fprintf(fp, " EVD_%u: %#" PRIx64,
|
||||
et, data->evd[i].payload);
|
||||
}
|
||||
}
|
||||
return len + perf_sample__fprintf_pt_spacing(len, fp);
|
||||
}
|
||||
|
||||
static int perf_sample__fprintf_synth_iflag_chg(struct perf_sample *sample, FILE *fp)
|
||||
{
|
||||
struct perf_synth_intel_iflag_chg *data = perf_sample__synth_ptr(sample);
|
||||
int len;
|
||||
|
||||
if (perf_sample__bad_synth_size(sample, *data))
|
||||
return 0;
|
||||
|
||||
len = fprintf(fp, " IFLAG: %d->%d %s branch", !data->iflag, data->iflag,
|
||||
data->via_branch ? "via" : "non");
|
||||
return len + perf_sample__fprintf_pt_spacing(len, fp);
|
||||
}
|
||||
|
||||
static int perf_sample__fprintf_synth(struct perf_sample *sample,
|
||||
struct evsel *evsel, FILE *fp)
|
||||
{
|
||||
@ -1829,6 +1905,10 @@ static int perf_sample__fprintf_synth(struct perf_sample *sample,
|
||||
return perf_sample__fprintf_synth_cbr(sample, fp);
|
||||
case PERF_SYNTH_INTEL_PSB:
|
||||
return perf_sample__fprintf_synth_psb(sample, fp);
|
||||
case PERF_SYNTH_INTEL_EVT:
|
||||
return perf_sample__fprintf_synth_evt(sample, fp);
|
||||
case PERF_SYNTH_INTEL_IFLAG_CHG:
|
||||
return perf_sample__fprintf_synth_iflag_chg(sample, fp);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -3716,7 +3796,7 @@ int cmd_script(int argc, const char **argv)
|
||||
"Valid types: hw,sw,trace,raw,synth. "
|
||||
"Fields: comm,tid,pid,time,cpu,event,trace,ip,sym,dso,"
|
||||
"addr,symoff,srcline,period,iregs,uregs,brstack,"
|
||||
"brstacksym,flags,bpf-output,brstackinsn,brstackoff,"
|
||||
"brstacksym,flags,bpf-output,brstackinsn,brstackinsnlen,brstackoff,"
|
||||
"callindent,insn,insnlen,synth,phys_addr,metric,misc,ipc,tod,"
|
||||
"data_page_size,code_page_size,ins_lat",
|
||||
parse_output_fields),
|
||||
@ -3842,13 +3922,13 @@ int cmd_script(int argc, const char **argv)
|
||||
if (symbol__validate_sym_arguments())
|
||||
return -1;
|
||||
|
||||
if (argc > 1 && !strncmp(argv[0], "rec", strlen("rec"))) {
|
||||
if (argc > 1 && strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
|
||||
rec_script_path = get_script_path(argv[1], RECORD_SUFFIX);
|
||||
if (!rec_script_path)
|
||||
return cmd_record(argc, argv);
|
||||
}
|
||||
|
||||
if (argc > 1 && !strncmp(argv[0], "rep", strlen("rep"))) {
|
||||
if (argc > 1 && strlen(argv[0]) > 2 && strstarts("report", argv[0])) {
|
||||
rep_script_path = get_script_path(argv[1], REPORT_SUFFIX);
|
||||
if (!rep_script_path) {
|
||||
fprintf(stderr,
|
||||
|
||||
@ -955,10 +955,10 @@ try_again_reset:
|
||||
* Enable counters and exec the command:
|
||||
*/
|
||||
if (forks) {
|
||||
evlist__start_workload(evsel_list);
|
||||
err = enable_counters();
|
||||
if (err)
|
||||
return -1;
|
||||
evlist__start_workload(evsel_list);
|
||||
|
||||
t0 = rdclock();
|
||||
clock_gettime(CLOCK_MONOTONIC, &ref_time);
|
||||
@ -2271,11 +2271,11 @@ int cmd_stat(int argc, const char **argv)
|
||||
} else
|
||||
stat_config.csv_sep = DEFAULT_SEPARATOR;
|
||||
|
||||
if (argc && !strncmp(argv[0], "rec", 3)) {
|
||||
if (argc && strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
|
||||
argc = __cmd_record(argc, argv);
|
||||
if (argc < 0)
|
||||
return -1;
|
||||
} else if (argc && !strncmp(argv[0], "rep", 3))
|
||||
} else if (argc && strlen(argv[0]) > 2 && strstarts("report", argv[0]))
|
||||
return __cmd_report(argc, argv);
|
||||
|
||||
interval = stat_config.interval;
|
||||
|
||||
@ -35,6 +35,7 @@
|
||||
#include "util/tool.h"
|
||||
#include "util/data.h"
|
||||
#include "util/debug.h"
|
||||
#include "util/string2.h"
|
||||
#include <linux/err.h>
|
||||
|
||||
#ifdef LACKS_OPEN_MEMSTREAM_PROTOTYPE
|
||||
@ -1983,7 +1984,7 @@ int cmd_timechart(int argc, const char **argv)
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (argc && !strncmp(argv[0], "rec", 3)) {
|
||||
if (argc && strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
|
||||
argc = parse_options(argc, argv, timechart_record_options,
|
||||
timechart_record_usage,
|
||||
PARSE_OPT_STOP_AT_NON_OPTION);
|
||||
|
||||
@ -746,7 +746,6 @@ static void perf_event__process_sample(struct perf_tool *tool,
|
||||
{
|
||||
struct perf_top *top = container_of(tool, struct perf_top, tool);
|
||||
struct addr_location al;
|
||||
int err;
|
||||
|
||||
if (!machine && perf_guest) {
|
||||
static struct intlist *seen;
|
||||
@ -839,8 +838,7 @@ static void perf_event__process_sample(struct perf_tool *tool,
|
||||
|
||||
pthread_mutex_lock(&hists->lock);
|
||||
|
||||
err = hist_entry_iter__add(&iter, &al, top->max_stack, top);
|
||||
if (err < 0)
|
||||
if (hist_entry_iter__add(&iter, &al, top->max_stack, top) < 0)
|
||||
pr_err("Problem incrementing symbol period, skipping event\n");
|
||||
|
||||
pthread_mutex_unlock(&hists->lock);
|
||||
@ -888,7 +886,7 @@ static void perf_top__mmap_read_idx(struct perf_top *top, int idx)
|
||||
if (ret && ret != -1)
|
||||
break;
|
||||
|
||||
ret = ordered_events__queue(top->qe.in, event, last_timestamp, 0);
|
||||
ret = ordered_events__queue(top->qe.in, event, last_timestamp, 0, NULL);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
@ -1486,7 +1484,9 @@ int cmd_top(int argc, const char **argv)
|
||||
"display this many functions"),
|
||||
OPT_BOOLEAN('U', "hide_user_symbols", &top.hide_user_symbols,
|
||||
"hide user symbols"),
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
OPT_BOOLEAN(0, "tui", &top.use_tui, "Use the TUI interface"),
|
||||
#endif
|
||||
OPT_BOOLEAN(0, "stdio", &top.use_stdio, "Use the stdio interface"),
|
||||
OPT_INCR('v', "verbose", &verbose,
|
||||
"be more verbose (show counter open errors, etc)"),
|
||||
@ -1667,8 +1667,10 @@ int cmd_top(int argc, const char **argv)
|
||||
|
||||
if (top.use_stdio)
|
||||
use_browser = 0;
|
||||
#ifdef HAVE_SLANG_SUPPORT
|
||||
else if (top.use_tui)
|
||||
use_browser = 1;
|
||||
#endif
|
||||
|
||||
setup_browser(false);
|
||||
|
||||
|
||||
@ -3789,7 +3789,7 @@ static int trace__deliver_event(struct trace *trace, union perf_event *event)
|
||||
if (err && err != -1)
|
||||
return err;
|
||||
|
||||
err = ordered_events__queue(&trace->oe.data, event, trace->oe.last, 0);
|
||||
err = ordered_events__queue(&trace->oe.data, event, trace->oe.last, 0, NULL);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
||||
@ -146,6 +146,7 @@ done
|
||||
check arch/x86/lib/memcpy_64.S '-I "^EXPORT_SYMBOL" -I "^#include <asm/export.h>" -I"^SYM_FUNC_START\(_LOCAL\)*(memcpy_\(erms\|orig\))"'
|
||||
check arch/x86/lib/memset_64.S '-I "^EXPORT_SYMBOL" -I "^#include <asm/export.h>" -I"^SYM_FUNC_START\(_LOCAL\)*(memset_\(erms\|orig\))"'
|
||||
check arch/x86/include/asm/amd-ibs.h '-I "^#include [<\"]\(asm/\)*msr-index.h"'
|
||||
check arch/arm64/include/asm/cputype.h '-I "^#include [<\"]\(asm/\)*sysreg.h"'
|
||||
check include/uapi/asm-generic/mman.h '-I "^#include <\(uapi/\)*asm-generic/mman-common\(-tools\)*.h>"'
|
||||
check include/uapi/linux/mman.h '-I "^#include <\(uapi/\)*asm/mman.h>"'
|
||||
check include/linux/build_bug.h '-I "^#\(ifndef\|endif\)\( \/\/\)* static_assert$"'
|
||||
|
||||
@ -0,0 +1,81 @@
|
||||
[
|
||||
{
|
||||
"ConfigCode": "0x00",
|
||||
"EventName": "cpa_cycles",
|
||||
"BriefDescription": "count of CPA cycles",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0x61",
|
||||
"EventName": "cpa_p1_wr_dat",
|
||||
"BriefDescription": "Number of write ops transmitted by the P1 port",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0x62",
|
||||
"EventName": "cpa_p1_rd_dat",
|
||||
"BriefDescription": "Number of read ops transmitted by the P1 port",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0x3",
|
||||
"EventName": "cpa_p1_rd_dat_64b",
|
||||
"BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0x4",
|
||||
"EventName": "cpa_p1_rd_dat_32b",
|
||||
"BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0xE1",
|
||||
"EventName": "cpa_p0_wr_dat",
|
||||
"BriefDescription": "Number of write ops transmitted by the P0 port",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0xE2",
|
||||
"EventName": "cpa_p0_rd_dat",
|
||||
"BriefDescription": "Number of read ops transmitted by the P0 port",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0x83",
|
||||
"EventName": "cpa_p0_rd_dat_64b",
|
||||
"BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"ConfigCode": "0x84",
|
||||
"EventName": "cpa_p0_rd_dat_32b",
|
||||
"BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles",
|
||||
"BriefDescription": "Average bandwidth of CPA Port 1",
|
||||
"MetricGroup": "CPA",
|
||||
"MetricName": "cpa_p1_avg_bw",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
},
|
||||
{
|
||||
"MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles",
|
||||
"BriefDescription": "Average bandwidth of CPA Port 0",
|
||||
"MetricGroup": "CPA",
|
||||
"MetricName": "cpa_p0_avg_bw",
|
||||
"Compat": "0x00000030",
|
||||
"Unit": "hisi_sicl,cpa"
|
||||
}
|
||||
]
|
||||
1140
tools/perf/pmu-events/arch/x86/alderlake/cache.json
Normal file
1140
tools/perf/pmu-events/arch/x86/alderlake/cache.json
Normal file
File diff suppressed because it is too large
Load Diff
158
tools/perf/pmu-events/arch/x86/alderlake/floating-point.json
Normal file
158
tools/perf/pmu-events/arch/x86/alderlake/floating-point.json
Normal file
@ -0,0 +1,158 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0xc3",
|
||||
"EventName": "MACHINE_CLEARS.FP_ASSIST",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "20003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0xc2",
|
||||
"EventName": "UOPS_RETIRED.FPDIV",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0xb0",
|
||||
"EventName": "ARITH.FPDIV_ACTIVE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts all microcode FP assists.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc1",
|
||||
"EventName": "ASSISTS.FP",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc1",
|
||||
"EventName": "ASSISTS.SSE_AVX_MIX",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xb3",
|
||||
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xb3",
|
||||
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xb3",
|
||||
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
}
|
||||
]
|
||||
491
tools/perf/pmu-events/arch/x86/alderlake/frontend.json
Normal file
491
tools/perf/pmu-events/arch/x86/alderlake/frontend.json
Normal file
@ -0,0 +1,491 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0xe6",
|
||||
"EventName": "BACLEARS.ANY",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.ACCESSES",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x3",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of instruction cache misses.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x87",
|
||||
"EventName": "DECODE.LCP",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "500009",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x61",
|
||||
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced DSB miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x1",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.DSB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x11",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x14",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.L1I_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x12",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.L2_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x13",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x600106",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x608006",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x601006",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x600206",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x610006",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x100206",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x602006",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x600406",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x620006",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x604006",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x600806",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.STLB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x15",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc6",
|
||||
"EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x17",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE_DATA.STALLS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "500009",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x83",
|
||||
"EventName": "ICACHE_TAG.STALLS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_CYCLES_ANY",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "6",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_CYCLES_OK",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles MITE is delivering any Uop",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_CYCLES_ANY",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "6",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_CYCLES_OK",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_CYCLES_ANY",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of switches from DSB or MITE to the MS",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_SWITCHES",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to IDQ while MS is busy",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x20",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x9c",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "6",
|
||||
"EventCode": "0x9c",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x9c",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"Invert": "1",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
}
|
||||
]
|
||||
318
tools/perf/pmu-events/arch/x86/alderlake/memory.json
Normal file
318
tools/perf/pmu-events/arch/x86/alderlake/memory.json
Normal file
@ -0,0 +1,318 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "LD_HEAD.ANY_AT_RET",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0xff",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "LD_HEAD.L1_BOUND_AT_RET",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0xf4",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases when load subsequently retires when load subsequently retires.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "LD_HEAD.OTHER_AT_RET",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0xc0",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk when load subsequently retires.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "LD_HEAD.PGWALK_AT_RET",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0xa0",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match when load subsequently retires.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "LD_HEAD.ST_ADDR_AT_RET",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x84",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0xc3",
|
||||
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "20003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xB7",
|
||||
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x3F84400001",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xB7",
|
||||
"EventName": "OCR.DEMAND_RFO.L3_MISS",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x3F84400002",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "6",
|
||||
"EventCode": "0xa3",
|
||||
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x6",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc3",
|
||||
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "2",
|
||||
"EventCode": "0x47",
|
||||
"EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "3",
|
||||
"EventCode": "0x47",
|
||||
"EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x3",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "5",
|
||||
"EventCode": "0x47",
|
||||
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x5",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "9",
|
||||
"EventCode": "0x47",
|
||||
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x9",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x80",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "1009",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x10",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "20011",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x100",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "503",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x20",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x4",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x200",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "101",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x40",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "2003",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "1,2,3,4,5,6,7",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x8",
|
||||
"PEBS": "2",
|
||||
"PEBScounters": "1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "50021",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0xcd",
|
||||
"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
|
||||
"PEBS": "2",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2A,0x2B",
|
||||
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x3FBFC00001",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2A,0x2B",
|
||||
"EventName": "OCR.DEMAND_RFO.L3_MISS",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x3FBFC00002",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
}
|
||||
]
|
||||
146
tools/perf/pmu-events/arch/x86/alderlake/other.json
Normal file
146
tools/perf/pmu-events/arch/x86/alderlake/other.json
Normal file
@ -0,0 +1,146 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Counts demand data reads that have any type of response.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xB7",
|
||||
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x10001",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xB7",
|
||||
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x10002",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts streaming stores that have any type of response.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xB7",
|
||||
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x10800",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc1",
|
||||
"EventName": "ASSISTS.ANY",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1f",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc1",
|
||||
"EventName": "ASSISTS.HARDWARE",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc1",
|
||||
"EventName": "ASSISTS.PAGE_FAULT",
|
||||
"PEBScounters": "0,1,2,3,4,5,6,7",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x28",
|
||||
"EventName": "CORE_POWER.LICENSE_1",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x28",
|
||||
"EventName": "CORE_POWER.LICENSE_2",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x28",
|
||||
"EventName": "CORE_POWER.LICENSE_3",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts demand data reads that have any type of response.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2A,0x2B",
|
||||
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x10001",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2A,0x2B",
|
||||
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x10002",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts streaming stores that have any type of response.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2A,0x2B",
|
||||
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"MSRValue": "0x10800",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "TBD",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x2d",
|
||||
"EventName": "XQ.FULL_CYCLES",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1",
|
||||
"Unit": "cpu_core"
|
||||
}
|
||||
]
|
||||
1721
tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
Normal file
1721
tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
Normal file
File diff suppressed because it is too large
Load Diff
222
tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
Normal file
222
tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
Normal file
@ -0,0 +1,222 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Number of clocks",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x01",
|
||||
"EventName": "UNC_M_CLOCKTICKS",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Incoming VC0 read request",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x02",
|
||||
"EventName": "UNC_M_VC0_REQUESTS_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Incoming VC0 write request",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x03",
|
||||
"EventName": "UNC_M_VC0_REQUESTS_WR",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Incoming VC1 read request",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x04",
|
||||
"EventName": "UNC_M_VC1_REQUESTS_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Incoming VC1 write request",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "UNC_M_VC1_REQUESTS_WR",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Incoming read prefetch request from IA",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x0A",
|
||||
"EventName": "UNC_M_PREFETCH_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Any Rank at Hot state",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x19",
|
||||
"EventName": "UNC_M_DRAM_THERMAL_HOT",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Any Rank at Warm state",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x1A",
|
||||
"EventName": "UNC_M_DRAM_THERMAL_WARM",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "incoming read request page status is Page Hit",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x1C",
|
||||
"EventName": "UNC_M_DRAM_PAGE_HIT_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "incoming read request page status is Page Empty",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x1D",
|
||||
"EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "incoming read request page status is Page Miss",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x1E",
|
||||
"EventName": "UNC_M_DRAM_PAGE_MISS_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "incoming write request page status is Page Hit",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x1F",
|
||||
"EventName": "UNC_M_DRAM_PAGE_HIT_WR",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "incoming write request page status is Page Empty",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x20",
|
||||
"EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "incoming write request page status is Page Miss",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x21",
|
||||
"EventName": "UNC_M_DRAM_PAGE_MISS_WR",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Read CAS command sent to DRAM",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x22",
|
||||
"EventName": "UNC_M_CAS_COUNT_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Write CAS command sent to DRAM",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x23",
|
||||
"EventName": "UNC_M_CAS_COUNT_WR",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "ACT command for a read request sent to DRAM",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x24",
|
||||
"EventName": "UNC_M_ACT_COUNT_RD",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "ACT command for a write request sent to DRAM",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x25",
|
||||
"EventName": "UNC_M_ACT_COUNT_WR",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "ACT command sent to DRAM",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x26",
|
||||
"EventName": "UNC_M_ACT_COUNT_TOTAL",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "PRE command sent to DRAM for a read/write request",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x27",
|
||||
"EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
|
||||
"Counter": "0,1,2,3,4",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x28",
|
||||
"EventName": "UNC_M_PRE_COUNT_IDLE",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)",
|
||||
"CounterType": "FREERUN",
|
||||
"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)",
|
||||
"Counter": "3",
|
||||
"CounterType": "FREERUN",
|
||||
"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
|
||||
"Counter": "1",
|
||||
"CounterType": "FREERUN",
|
||||
"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
|
||||
"Counter": "4",
|
||||
"CounterType": "FREERUN",
|
||||
"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
|
||||
"PerPkg": "1",
|
||||
"Unit": "iMC"
|
||||
}
|
||||
]
|
||||
40
tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
Normal file
40
tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
Normal file
@ -0,0 +1,40 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
|
||||
"Counter": "Fixed",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0xff",
|
||||
"EventName": "UNC_CLOCK.SOCKET",
|
||||
"PerPkg": "1",
|
||||
"Unit": "CLOCK"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC",
|
||||
"Counter": "0,1",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x81",
|
||||
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
|
||||
"PerPkg": "1",
|
||||
"UMask": "0x01",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of requests allocated in Coherency Tracker",
|
||||
"Counter": "0,1",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x84",
|
||||
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
|
||||
"PerPkg": "1",
|
||||
"UMask": "0x01",
|
||||
"Unit": "ARB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic",
|
||||
"CounterType": "PGMABLE",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
|
||||
"PerPkg": "1",
|
||||
"UMask": "0x01",
|
||||
"Unit": "ARB"
|
||||
}
|
||||
]
|
||||
258
tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
Normal file
258
tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
Normal file
@ -0,0 +1,258 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0xe",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0xe",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3,4,5",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
|
||||
"PEBScounters": "0,1,2,3,4,5",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x90",
|
||||
"Unit": "cpu_atom"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x11",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x11",
|
||||
"EventName": "ITLB_MISSES.WALK_ACTIVE",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x11",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x11",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x11",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2",
|
||||
"Unit": "cpu_core"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x11",
|
||||
"EventName": "ITLB_MISSES.WALK_PENDING",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10",
|
||||
"Unit": "cpu_core"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,261 +1,261 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x10",
|
||||
"BriefDescription": "Floating point assists for retired operations.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "X87_COMP_OPS_EXE.ANY.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Floating point computational micro-ops executed."
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventName": "X87_COMP_OPS_EXE.ANY.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Floating point computational micro-ops retired."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "X87_COMP_OPS_EXE.FXCH.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "FXCH uops executed."
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x82",
|
||||
"EventName": "X87_COMP_OPS_EXE.FXCH.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "FXCH uops retired."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x11",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "FP_ASSIST.S",
|
||||
"SampleAfterValue": "10000",
|
||||
"BriefDescription": "Floating point assists."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x11",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventName": "FP_ASSIST.AR",
|
||||
"SampleAfterValue": "10000",
|
||||
"BriefDescription": "Floating point assists for retired operations."
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB0",
|
||||
"BriefDescription": "Floating point assists.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "SIMD_UOPS_EXEC.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD micro-ops executed (excluding stores)."
|
||||
"EventCode": "0x11",
|
||||
"EventName": "FP_ASSIST.S",
|
||||
"SampleAfterValue": "10000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"EventCode": "0xB0",
|
||||
"BriefDescription": "SIMD assists invoked.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x80",
|
||||
"EventName": "SIMD_UOPS_EXEC.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD micro-ops retired (excluding stores)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "SIMD_SAT_UOP_EXEC.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD saturated arithmetic micro-ops executed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x80",
|
||||
"EventName": "SIMD_SAT_UOP_EXEC.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD saturated arithmetic micro-ops retired."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed multiply micro-ops executed"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed multiply micro-ops retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed shift micro-ops executed"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x82",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed shift micro-ops retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x4",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed micro-ops executed"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x84",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed micro-ops retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD unpacked micro-ops executed"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x88",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD unpacked micro-ops retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x10",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed logical micro-ops executed"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x90",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed logical micro-ops retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x20",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed arithmetic micro-ops executed"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xa0",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD packed arithmetic micro-ops retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8",
|
||||
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x10",
|
||||
"EventName": "SIMD_INST_RETIRED.VECTOR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8",
|
||||
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "SIMD_ASSIST",
|
||||
"SampleAfterValue": "100000",
|
||||
"BriefDescription": "SIMD assists invoked."
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCE",
|
||||
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD Instructions retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xCE",
|
||||
"EventName": "SIMD_INSTR_RETIRED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "SIMD Instructions retired."
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCF",
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "SIMD_INST_RETIRED.VECTOR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Saturated arithmetic instructions retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xCF",
|
||||
"EventName": "SIMD_SAT_INSTR_RETIRED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Saturated arithmetic instructions retired."
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB1",
|
||||
"EventName": "SIMD_SAT_UOP_EXEC.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB1",
|
||||
"EventName": "SIMD_SAT_UOP_EXEC.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD micro-ops retired (excluding stores).",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB0",
|
||||
"EventName": "SIMD_UOPS_EXEC.AR",
|
||||
"PEBS": "2",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD micro-ops executed (excluding stores).",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB0",
|
||||
"EventName": "SIMD_UOPS_EXEC.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed arithmetic micro-ops retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0xa0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed arithmetic micro-ops executed",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed logical micro-ops retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x90"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed logical micro-ops executed",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed multiply micro-ops retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed multiply micro-ops executed",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed micro-ops retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x84"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed micro-ops executed",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed shift micro-ops retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x82"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD packed shift micro-ops executed",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD unpacked micro-ops retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x88"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "SIMD unpacked micro-ops executed",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xB3",
|
||||
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating point computational micro-ops retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x10",
|
||||
"EventName": "X87_COMP_OPS_EXE.ANY.AR",
|
||||
"PEBS": "2",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating point computational micro-ops executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x10",
|
||||
"EventName": "X87_COMP_OPS_EXE.ANY.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "FXCH uops retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x10",
|
||||
"EventName": "X87_COMP_OPS_EXE.FXCH.AR",
|
||||
"PEBS": "2",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x82"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "FXCH uops executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x10",
|
||||
"EventName": "X87_COMP_OPS_EXE.FXCH.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
}
|
||||
]
|
||||
@ -1,83 +1,91 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"BriefDescription": "BACLEARS asserted.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x3",
|
||||
"EventName": "ICACHE.ACCESSES",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Instruction fetches."
|
||||
"EventCode": "0xE6",
|
||||
"EventName": "BACLEARS.ANY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"BriefDescription": "Cycles during which instruction fetches are stalled.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Icache hit"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Icache miss"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x86",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Cycles during which instruction fetches are stalled."
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x87",
|
||||
"BriefDescription": "Decode stall due to IQ full",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "DECODE_STALL.PFB_EMPTY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Decode stall due to PFB empty"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x87",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "DECODE_STALL.IQ_FULL",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Decode stall due to IQ full"
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xAA",
|
||||
"BriefDescription": "Decode stall due to PFB empty",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
|
||||
"EventCode": "0x87",
|
||||
"EventName": "DECODE_STALL.PFB_EMPTY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Non-CISC nacro instructions decoded"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xAA",
|
||||
"BriefDescription": "Instruction fetches.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "MACRO_INSTS.CISC_DECODED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "CISC macro instructions decoded"
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.ACCESSES",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xAA",
|
||||
"BriefDescription": "Icache hit",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Icache miss",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All Instructions decoded",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xAA",
|
||||
"EventName": "MACRO_INSTS.ALL_DECODED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "All Instructions decoded"
|
||||
"UMask": "0x3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA9",
|
||||
"BriefDescription": "CISC macro instructions decoded",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventCode": "0xAA",
|
||||
"EventName": "MACRO_INSTS.CISC_DECODED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Non-CISC nacro instructions decoded",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xAA",
|
||||
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
|
||||
"Counter": "0,1",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0xA9",
|
||||
"EventName": "UOPS.MS_CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
|
||||
"CounterMask": "1"
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
@ -1,154 +1,154 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"BriefDescription": "Nonzero segbase 1 bubble",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xf",
|
||||
"EventName": "MISALIGN_MEM_REF.SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Memory references that cross an 8-byte boundary."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x9",
|
||||
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Load splits"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xa",
|
||||
"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Store splits"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8f",
|
||||
"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x89",
|
||||
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Load splits (At Retirement)"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8a",
|
||||
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Store splits (Ar Retirement)"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8c",
|
||||
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "ld-op-st splits"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x97",
|
||||
"EventName": "MISALIGN_MEM_REF.BUBBLE",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Nonzero segbase 1 bubble"
|
||||
"UMask": "0x97"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"BriefDescription": "Nonzero segbase load 1 bubble",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x91",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Nonzero segbase load 1 bubble"
|
||||
"UMask": "0x91"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"BriefDescription": "Load splits",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x92",
|
||||
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Nonzero segbase store 1 bubble"
|
||||
"UMask": "0x9"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5",
|
||||
"BriefDescription": "Load splits (At Retirement)",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x94",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x89"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble"
|
||||
"UMask": "0x94"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "ld-op-st splits",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventName": "PREFETCH.PREFETCHT0",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed."
|
||||
"UMask": "0x8c"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "Memory references that cross an 8-byte boundary.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x82",
|
||||
"EventName": "PREFETCH.PREFETCHT1",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed."
|
||||
"UMask": "0xf"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x84",
|
||||
"EventName": "PREFETCH.PREFETCHT2",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed."
|
||||
"UMask": "0x8f"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "Nonzero segbase store 1 bubble",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x86",
|
||||
"EventName": "PREFETCH.SW_L2",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed"
|
||||
"UMask": "0x92"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "Store splits",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x88",
|
||||
"EventName": "PREFETCH.PREFETCHNTA",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed"
|
||||
"UMask": "0xa"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "Store splits (Ar Retirement)",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x10",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x8a"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L1 hardware prefetch request",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.HW_PREFETCH",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "L1 hardware prefetch request"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xf",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.PREFETCHNTA",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x88"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.PREFETCHT0",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.PREFETCHT1",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x82"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.PREFETCHT2",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x84"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Any Software prefetch",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Any Software prefetch"
|
||||
"UMask": "0xf"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7",
|
||||
"BriefDescription": "Any Software prefetch",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8f",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Any Software prefetch"
|
||||
"UMask": "0x8f"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7",
|
||||
"EventName": "PREFETCH.SW_L2",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x86"
|
||||
}
|
||||
]
|
||||
@ -1,450 +1,450 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x6",
|
||||
"BriefDescription": "Bus queue is empty.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x80",
|
||||
"EventName": "SEGMENT_REG_LOADS.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of segment register loads."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x20",
|
||||
"EventName": "DISPATCH_BLOCKED.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3A",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "EIST_TRANS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3B",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xc0",
|
||||
"EventName": "THERMAL_TRIP",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of thermal trips"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x60",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Outstanding cacheable data read bus requests duration."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x60",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_REQUEST_OUTSTANDING.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Outstanding cacheable data read bus requests duration."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x61",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x20",
|
||||
"EventName": "BUS_BNR_DRV.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of Bus Not Ready signals asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x61",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "BUS_BNR_DRV.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of Bus Not Ready signals asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x62",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x20",
|
||||
"EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus cycles when data is sent on the bus."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x62",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus cycles when data is sent on the bus."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x63",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus cycles when a LOCK signal is asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x63",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_LOCK_CLOCKS.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus cycles when a LOCK signal is asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x64",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_DATA_RCV.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus cycles while processor receives data."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x65",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_BRD.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Burst read bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x65",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_BRD.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Burst read bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x66",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_RFO.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "RFO bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x66",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_RFO.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "RFO bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x67",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_WB.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Explicit writeback bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x67",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_WB.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Explicit writeback bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x68",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Instruction-fetch bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x68",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_IFETCH.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Instruction-fetch bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x69",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Invalidate bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x69",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_INVAL.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Invalidate bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6A",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_PWR.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Partial write bus transaction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6A",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_PWR.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Partial write bus transaction."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6B",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_P.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Partial bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6B",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_P.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Partial bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6C",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_IO.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "IO bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6C",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_IO.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "IO bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6D",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_DEF.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Deferred bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6D",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_DEF.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Deferred bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6E",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_BURST.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Burst (full cache-line) bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6E",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_BURST.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Burst (full cache-line) bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6F",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_MEM.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Memory bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x6F",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_MEM.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Memory bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x70",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "BUS_TRANS_ANY.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "All bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x70",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_TRANS_ANY.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "All bus transactions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xb",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.HITM",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2b",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x21",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x22",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x77",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x28",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "External snoops."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7A",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x20",
|
||||
"EventName": "BUS_HIT_DRV.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "HIT signal asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7A",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "BUS_HIT_DRV.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "HIT signal asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7B",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x20",
|
||||
"EventName": "BUS_HITM_DRV.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "HITM signal asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7B",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "BUS_HITM_DRV.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "HITM signal asserted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7D",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUSQ_EMPTY.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus queue is empty."
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7E",
|
||||
"BriefDescription": "Number of Bus Not Ready signals asserted.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xe0",
|
||||
"EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
|
||||
"EventCode": "0x61",
|
||||
"EventName": "BUS_BNR_DRV.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus stalled for snoops."
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x7E",
|
||||
"BriefDescription": "Number of Bus Not Ready signals asserted.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "SNOOP_STALL_DRV.SELF",
|
||||
"EventCode": "0x61",
|
||||
"EventName": "BUS_BNR_DRV.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus stalled for snoops."
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Bus cycles while processor receives data.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x64",
|
||||
"EventName": "BUS_DATA_RCV.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Bus cycles when data is sent on the bus.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x62",
|
||||
"EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Bus cycles when data is sent on the bus.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x62",
|
||||
"EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "HITM signal asserted.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7B",
|
||||
"EventName": "BUS_HITM_DRV.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "HITM signal asserted.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7B",
|
||||
"EventName": "BUS_HITM_DRV.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "HIT signal asserted.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7A",
|
||||
"EventName": "BUS_HIT_DRV.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "HIT signal asserted.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7A",
|
||||
"EventName": "BUS_HIT_DRV.THIS_AGENT",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "IO requests waiting in the bus queue.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7F",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x40",
|
||||
"EventName": "BUS_IO_WAIT.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "IO requests waiting in the bus queue."
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventCode": "0x63",
|
||||
"EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x63",
|
||||
"EventName": "BUS_LOCK_CLOCKS.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x60",
|
||||
"EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x60",
|
||||
"EventName": "BUS_REQUEST_OUTSTANDING.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x70",
|
||||
"EventName": "BUS_TRANS_ANY.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x70",
|
||||
"EventName": "BUS_TRANS_ANY.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Burst read bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x65",
|
||||
"EventName": "BUS_TRANS_BRD.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Burst read bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x65",
|
||||
"EventName": "BUS_TRANS_BRD.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Burst (full cache-line) bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6E",
|
||||
"EventName": "BUS_TRANS_BURST.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Burst (full cache-line) bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6E",
|
||||
"EventName": "BUS_TRANS_BURST.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Deferred bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6D",
|
||||
"EventName": "BUS_TRANS_DEF.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Deferred bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6D",
|
||||
"EventName": "BUS_TRANS_DEF.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction-fetch bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x68",
|
||||
"EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction-fetch bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x68",
|
||||
"EventName": "BUS_TRANS_IFETCH.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Invalidate bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x69",
|
||||
"EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Invalidate bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x69",
|
||||
"EventName": "BUS_TRANS_INVAL.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "IO bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6C",
|
||||
"EventName": "BUS_TRANS_IO.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "IO bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6C",
|
||||
"EventName": "BUS_TRANS_IO.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Memory bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6F",
|
||||
"EventName": "BUS_TRANS_MEM.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Memory bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6F",
|
||||
"EventName": "BUS_TRANS_MEM.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Partial bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6B",
|
||||
"EventName": "BUS_TRANS_P.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Partial bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6B",
|
||||
"EventName": "BUS_TRANS_P.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Partial write bus transaction.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6A",
|
||||
"EventName": "BUS_TRANS_PWR.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Partial write bus transaction.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6A",
|
||||
"EventName": "BUS_TRANS_PWR.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "RFO bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x66",
|
||||
"EventName": "BUS_TRANS_RFO.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "RFO bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x66",
|
||||
"EventName": "BUS_TRANS_RFO.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Explicit writeback bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x67",
|
||||
"EventName": "BUS_TRANS_WB.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Explicit writeback bus transactions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x67",
|
||||
"EventName": "BUS_TRANS_WB.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles during which interrupts are disabled.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC6",
|
||||
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Cycles during which interrupts are disabled."
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"BriefDescription": "Cycles during which interrupts are pending and disabled.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventCode": "0xC6",
|
||||
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Cycles during which interrupts are pending and disabled."
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC8",
|
||||
"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventCode": "0x9",
|
||||
"EventName": "DISPATCH_BLOCKED.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x3A",
|
||||
"EventName": "EIST_TRANS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x2b"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x21"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x22"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x28"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xb"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x77",
|
||||
"EventName": "EXT_SNOOP.THIS_AGENT.HITM",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Hardware interrupts received.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC8",
|
||||
"EventName": "HW_INT_RCV",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Hardware interrupts received."
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of segment register loads.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x6",
|
||||
"EventName": "SEGMENT_REG_LOADS.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Bus stalled for snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7E",
|
||||
"EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Bus stalled for snoops.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x7E",
|
||||
"EventName": "SNOOP_STALL_DRV.SELF",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of thermal trips",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x3B",
|
||||
"EventName": "THERMAL_TRIP",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xc0"
|
||||
}
|
||||
]
|
||||
@ -1,364 +1,356 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x2",
|
||||
"BriefDescription": "Bogus branches",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x83",
|
||||
"EventName": "STORE_FORWARDS.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "All store forwards"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x2",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventName": "STORE_FORWARDS.GOOD",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Good store forwards"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x7f",
|
||||
"EventName": "REISSUE.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Micro-op reissues for any cause"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xff",
|
||||
"EventName": "REISSUE.ANY.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Micro-op reissues for any cause (At Retirement)"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x12",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MUL.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Multiply operations executed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x12",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventName": "MUL.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Multiply operations retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x13",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "DIV.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Divide operations executed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x13",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventName": "DIV.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Divide operations retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x14",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "CYCLES_DIV_BUSY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Cycles the divider is busy."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "CPU_CLK_UNHALTED.CORE_P",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Core cycles when core is not halted"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "CPU_CLK_UNHALTED.BUS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Bus cycles when core is not halted"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA",
|
||||
"Counter": "Fixed counter 2",
|
||||
"UMask": "0x0",
|
||||
"EventName": "CPU_CLK_UNHALTED.CORE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Core cycles when core is not halted"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA",
|
||||
"Counter": "Fixed counter 3",
|
||||
"UMask": "0x0",
|
||||
"EventName": "CPU_CLK_UNHALTED.REF",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Reference cycles when core is not halted."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x88",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.COND",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "All macro conditional branch instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x88",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.UNCOND",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x88",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x4",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.IND",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "All indirect branches that are not calls."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x88",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.RET",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "All indirect branches that have a return mnemonic"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x88",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x10",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "All non-indirect calls"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x88",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x20",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "All indirect calls, including both register and memory indirect."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x88",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x41",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Only taken macro conditional branch instructions"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x89",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.COND",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Mispredicted cond branch instructions retired"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x89",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.IND",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Mispredicted ind branches that are not calls"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x89",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x4",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Mispredicted return branches"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x89",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Mispredicted indirect calls, including both register and memory indirect."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x89",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x11",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Mispredicted and taken cond branch instructions retired"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"EventCode": "0xC0",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "INST_RETIRED.ANY_P",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Instructions retired (precise event)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA",
|
||||
"Counter": "Fixed counter 1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "INST_RETIRED.ANY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Instructions retired."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC2",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x10",
|
||||
"EventName": "UOPS_RETIRED.ANY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Micro-ops retired."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC2",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x10",
|
||||
"EventName": "UOPS_RETIRED.STALLED_CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Cycles no micro-ops retired."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC2",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x10",
|
||||
"EventName": "UOPS_RETIRED.STALLS",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Periods no micro-ops retired."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC3",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MACHINE_CLEARS.SMC",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Self-Modifying Code detected."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "BR_INST_RETIRED.ANY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired branch instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired branch instructions that were predicted not-taken."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Retired branch instructions that were mispredicted not-taken."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x4",
|
||||
"EventName": "BR_INST_RETIRED.PRED_TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired branch instructions that were predicted taken."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x8",
|
||||
"EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Retired branch instructions that were mispredicted taken."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xc",
|
||||
"EventName": "BR_INST_RETIRED.TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired taken branch instructions."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xf",
|
||||
"EventName": "BR_INST_RETIRED.ANY1",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Retired branch instructions."
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"EventCode": "0xC5",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x0",
|
||||
"EventName": "BR_INST_RETIRED.MISPRED",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Retired mispredicted branch instructions (precise event)."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xDC",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "RESOURCE_STALLS.DIV_BUSY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Cycles issue is stalled due to div busy."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xE0",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "BR_INST_DECODED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Branch instructions decoded"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xE4",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "BOGUS_BR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Bogus branches"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xE6",
|
||||
"BriefDescription": "Branch instructions decoded",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "BACLEARS.ANY",
|
||||
"EventCode": "0xE0",
|
||||
"EventName": "BR_INST_DECODED",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "BACLEARS asserted."
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3",
|
||||
"BriefDescription": "Retired branch instructions.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventCode": "0xC4",
|
||||
"EventName": "BR_INST_RETIRED.ANY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired branch instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC4",
|
||||
"EventName": "BR_INST_RETIRED.ANY1",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0xf"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired mispredicted branch instructions (precise event).",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC5",
|
||||
"EventName": "BR_INST_RETIRED.MISPRED",
|
||||
"PEBS": "1",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC4",
|
||||
"EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired branch instructions that were mispredicted taken.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC4",
|
||||
"EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired branch instructions that were predicted not-taken.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC4",
|
||||
"EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired branch instructions that were predicted taken.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC4",
|
||||
"EventName": "BR_INST_RETIRED.PRED_TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired taken branch instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC4",
|
||||
"EventName": "BR_INST_RETIRED.TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0xc"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All macro conditional branch instructions.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x88",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.COND",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Only taken macro conditional branch instructions",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x88",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x41"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All non-indirect calls",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x88",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All indirect branches that are not calls.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x88",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.IND",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All indirect calls, including both register and memory indirect.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x88",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All indirect branches that have a return mnemonic",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x88",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.RET",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x88",
|
||||
"EventName": "BR_INST_TYPE_RETIRED.UNCOND",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Mispredicted cond branch instructions retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x89",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.COND",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Mispredicted and taken cond branch instructions retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x89",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x11"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Mispredicted ind branches that are not calls",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x89",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.IND",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x89",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Mispredicted return branches",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x89",
|
||||
"EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Bus cycles when core is not halted",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x3C",
|
||||
"EventName": "CPU_CLK_UNHALTED.BUS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core cycles when core is not halted",
|
||||
"Counter": "Fixed counter 2",
|
||||
"EventCode": "0xA",
|
||||
"EventName": "CPU_CLK_UNHALTED.CORE",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core cycles when core is not halted",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x3C",
|
||||
"EventName": "CPU_CLK_UNHALTED.CORE_P",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Reference cycles when core is not halted.",
|
||||
"Counter": "Fixed counter 3",
|
||||
"EventCode": "0xA",
|
||||
"EventName": "CPU_CLK_UNHALTED.REF",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles the divider is busy.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x14",
|
||||
"EventName": "CYCLES_DIV_BUSY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Divide operations retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DIV.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Divide operations executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x13",
|
||||
"EventName": "DIV.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions retired.",
|
||||
"Counter": "Fixed counter 1",
|
||||
"EventCode": "0xA",
|
||||
"EventName": "INST_RETIRED.ANY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions retired (precise event).",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC0",
|
||||
"EventName": "INST_RETIRED.ANY_P",
|
||||
"PEBS": "2",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Self-Modifying Code detected.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC3",
|
||||
"EventName": "MACHINE_CLEARS.SMC",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Multiply operations retired",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "MUL.AR",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Multiply operations executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x12",
|
||||
"EventName": "MUL.S",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Micro-op reissues for any cause",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x3",
|
||||
"EventName": "REISSUE.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x7f"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Micro-op reissues for any cause (At Retirement)",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x3",
|
||||
"EventName": "REISSUE.ANY.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Micro-op reissues on a store-load collision",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x3",
|
||||
"EventName": "REISSUE.OVERLAP_STORE",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Micro-op reissues on a store-load collision"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3",
|
||||
"BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x81",
|
||||
"EventCode": "0x3",
|
||||
"EventName": "REISSUE.OVERLAP_STORE.AR",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)"
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles issue is stalled due to div busy.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xDC",
|
||||
"EventName": "RESOURCE_STALLS.DIV_BUSY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "All store forwards",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x2",
|
||||
"EventName": "STORE_FORWARDS.ANY",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x83"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Good store forwards",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x2",
|
||||
"EventName": "STORE_FORWARDS.GOOD",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x81"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Micro-ops retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC2",
|
||||
"EventName": "UOPS_RETIRED.ANY",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles no micro-ops retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC2",
|
||||
"EventName": "UOPS_RETIRED.STALLED_CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Periods no micro-ops retired.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC2",
|
||||
"EventName": "UOPS_RETIRED.STALLS",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x10"
|
||||
}
|
||||
]
|
||||
@ -1,124 +1,124 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x8",
|
||||
"BriefDescription": "Memory accesses that missed the DTLB.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x7",
|
||||
"EventCode": "0x8",
|
||||
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Memory accesses that missed the DTLB."
|
||||
"UMask": "0x7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x8",
|
||||
"BriefDescription": "DTLB misses due to load operations.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x5",
|
||||
"EventCode": "0x8",
|
||||
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "DTLB misses due to load operations."
|
||||
"UMask": "0x5"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x8",
|
||||
"BriefDescription": "DTLB misses due to store operations.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x9",
|
||||
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "L0 DTLB misses due to load operations."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x8",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x6",
|
||||
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "DTLB misses due to store operations."
|
||||
"UMask": "0x6"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x8",
|
||||
"BriefDescription": "L0 DTLB misses due to load operations.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0xa",
|
||||
"EventCode": "0x8",
|
||||
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x9"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L0 DTLB misses due to store operations",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x8",
|
||||
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "L0 DTLB misses due to store operations"
|
||||
"UMask": "0xa"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC",
|
||||
"BriefDescription": "ITLB flushes.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x3",
|
||||
"EventName": "PAGE_WALKS.WALKS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of page-walks executed."
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x3",
|
||||
"EventName": "PAGE_WALKS.CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Duration of page-walks in core cycles"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of D-side only page walks"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Duration of D-side only page walks"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Number of I-Side page walks"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"BriefDescription": "Duration of I-Side page walks"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x82",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ITLB.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "ITLB hits."
|
||||
},
|
||||
{
|
||||
"EventCode": "0x82",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x4",
|
||||
"EventName": "ITLB.FLUSH",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "ITLB flushes."
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"BriefDescription": "ITLB hits.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0x82",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x2",
|
||||
"EventName": "ITLB.MISSES",
|
||||
"EventName": "ITLB.HIT",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "ITLB misses."
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"EventCode": "0xCB",
|
||||
"BriefDescription": "ITLB misses.",
|
||||
"Counter": "0,1",
|
||||
"UMask": "0x4",
|
||||
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
|
||||
"EventCode": "0x82",
|
||||
"EventName": "ITLB.MISSES",
|
||||
"PEBS": "2",
|
||||
"SampleAfterValue": "200000",
|
||||
"BriefDescription": "Retired loads that miss the DTLB (precise event)."
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired loads that miss the DTLB (precise event).",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xCB",
|
||||
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
|
||||
"PEBS": "1",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Duration of page-walks in core cycles",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC",
|
||||
"EventName": "PAGE_WALKS.CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x3"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Duration of D-side only page walks",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC",
|
||||
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of D-side only page walks",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC",
|
||||
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Duration of I-Side page walks",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC",
|
||||
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
|
||||
"SampleAfterValue": "2000000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of I-Side page walks",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC",
|
||||
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of page-walks executed.",
|
||||
"Counter": "0,1",
|
||||
"EventCode": "0xC",
|
||||
"EventName": "PAGE_WALKS.WALKS",
|
||||
"SampleAfterValue": "200000",
|
||||
"UMask": "0x3"
|
||||
}
|
||||
]
|
||||
@ -1,196 +1,170 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Frontend_Bound",
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Frontend_Bound_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Bad_Speculation",
|
||||
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Bad_Speculation_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )",
|
||||
"MetricConstraint": "NO_NMI_WATCHDOG",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Backend_Bound",
|
||||
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Backend_Bound_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Retiring",
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. "
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. "
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Retiring_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "TopDownL1",
|
||||
"MetricGroup": "Ret;Summary",
|
||||
"MetricName": "IPC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops Per Instruction",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Pipeline;Retire",
|
||||
"MetricGroup": "Pipeline;Ret;Retire",
|
||||
"MetricName": "UPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction per taken branch",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fetch_BW;PGO",
|
||||
"MetricName": "IpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch instructions per taken branch. ",
|
||||
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;PGO",
|
||||
"MetricName": "BpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions",
|
||||
"MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
|
||||
"MetricGroup": "PGO;IcMiss",
|
||||
"MetricName": "IFetch_Line_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
|
||||
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
|
||||
"MetricGroup": "DSB;Fetch_BW",
|
||||
"MetricName": "DSB_Coverage"
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;FetchBW",
|
||||
"MetricName": "UpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
|
||||
"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
|
||||
"MetricGroup": "Pipeline;Summary",
|
||||
"MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "Pipeline;Mem",
|
||||
"MetricName": "CPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricGroup": "Pipeline",
|
||||
"MetricName": "CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
|
||||
"MetricExpr": "4 * cycles",
|
||||
"MetricGroup": "TopDownL1",
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
|
||||
"MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "TmaL1",
|
||||
"MetricName": "SLOTS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
|
||||
"MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopDownL1_SMT",
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
|
||||
"MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "TmaL1_SMT",
|
||||
"MetricName": "SLOTS_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Load (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
|
||||
"MetricGroup": "Instruction_Type",
|
||||
"MetricName": "IpL"
|
||||
"BriefDescription": "The ratio of Executed- by Issued-Uops",
|
||||
"MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
|
||||
"MetricGroup": "Cor;Pipeline",
|
||||
"MetricName": "Execute_per_Issue",
|
||||
"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Store (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
|
||||
"MetricGroup": "Instruction_Type",
|
||||
"MetricName": "IpS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Branch (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Branches;Instruction_Type",
|
||||
"MetricName": "IpB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
|
||||
"MetricGroup": "Branches",
|
||||
"MetricName": "IpCall"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total number of retired Instructions",
|
||||
"MetricExpr": "INST_RETIRED.ANY",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricName": "Instructions"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / cycles",
|
||||
"MetricGroup": "SMT",
|
||||
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Ret;SMT;TmaL1",
|
||||
"MetricName": "CoreIPC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "SMT",
|
||||
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Ret;SMT;TmaL1_SMT",
|
||||
"MetricName": "CoreIPC_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating Point Operations Per Cycle",
|
||||
"MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / cycles",
|
||||
"MetricGroup": "FLOPS",
|
||||
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Ret;Flops",
|
||||
"MetricName": "FLOPc"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating Point Operations Per Cycle",
|
||||
"MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "FLOPS_SMT",
|
||||
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Ret;Flops_SMT",
|
||||
"MetricName": "FLOPc_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)",
|
||||
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",
|
||||
"MetricGroup": "Cor;Flops;HPC",
|
||||
"MetricName": "FP_Arith_Utilization",
|
||||
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",
|
||||
"MetricGroup": "Cor;Flops;HPC_SMT",
|
||||
"MetricName": "FP_Arith_Utilization_SMT",
|
||||
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
|
||||
"MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
|
||||
"MetricGroup": "Pipeline",
|
||||
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
|
||||
"MetricName": "ILP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)",
|
||||
"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "BrMispredicts",
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
|
||||
"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Bad;BrMispredicts",
|
||||
"MetricName": "Branch_Misprediction_Cost"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)",
|
||||
"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "BrMispredicts_SMT",
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
|
||||
"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Bad;BrMispredicts_SMT",
|
||||
"MetricName": "Branch_Misprediction_Cost_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "BrMispredicts",
|
||||
"MetricGroup": "Bad;BadSpec;BrMispredicts",
|
||||
"MetricName": "IpMispredict"
|
||||
},
|
||||
{
|
||||
@ -200,87 +174,196 @@
|
||||
"MetricName": "CORE_CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
|
||||
"BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
|
||||
"MetricGroup": "InsType",
|
||||
"MetricName": "IpLoad"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
|
||||
"MetricGroup": "InsType",
|
||||
"MetricName": "IpStore"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Branches;Fed;InsType",
|
||||
"MetricName": "IpBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
|
||||
"MetricGroup": "Branches;Fed;PGO",
|
||||
"MetricName": "IpCall"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction per taken branch",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
|
||||
"MetricName": "IpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch instructions per taken branch. ",
|
||||
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;PGO",
|
||||
"MetricName": "BpTkBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;InsType",
|
||||
"MetricName": "IpFLOP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )",
|
||||
"MetricGroup": "Flops;InsType",
|
||||
"MetricName": "IpArith",
|
||||
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"MetricGroup": "Flops;FpScalar;InsType",
|
||||
"MetricName": "IpArith_Scalar_SP",
|
||||
"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"MetricGroup": "Flops;FpScalar;InsType",
|
||||
"MetricName": "IpArith_Scalar_DP",
|
||||
"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;FpVector;InsType",
|
||||
"MetricName": "IpArith_AVX128",
|
||||
"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;FpVector;InsType",
|
||||
"MetricName": "IpArith_AVX256",
|
||||
"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
|
||||
"MetricExpr": "INST_RETIRED.ANY",
|
||||
"MetricGroup": "Summary;TmaL1",
|
||||
"MetricName": "Instructions"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
|
||||
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
|
||||
"MetricGroup": "DSB;Fed;FetchBW",
|
||||
"MetricName": "DSB_Coverage"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
|
||||
"MetricGroup": "Memory_Bound;Memory_Lat",
|
||||
"MetricName": "Load_Miss_Real_Latency"
|
||||
"MetricGroup": "Mem;MemoryBound;MemoryLat",
|
||||
"MetricName": "Load_Miss_Real_Latency",
|
||||
"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
|
||||
"MetricGroup": "Memory_Bound;Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBound;MemoryBW",
|
||||
"MetricName": "MLP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / cycles",
|
||||
"MetricGroup": "TLB",
|
||||
"MetricName": "Page_Walks_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TLB_SMT",
|
||||
"MetricName": "Page_Walks_Utilization_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
|
||||
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L1D_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
|
||||
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L2_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
|
||||
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L3_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L1MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;Backend;CacheMisses",
|
||||
"MetricName": "L2MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses;Offcore",
|
||||
"MetricName": "L2MPKI_All"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2MPKI_Load"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
|
||||
"MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2HPKI_All"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2HPKI_Load"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L3MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricConstraint": "NO_NMI_WATCHDOG",
|
||||
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Mem;MemoryTLB",
|
||||
"MetricName": "Page_Walks_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Mem;MemoryTLB_SMT",
|
||||
"MetricName": "Page_Walks_Utilization_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average CPU Utilization",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricGroup": "HPC;Summary",
|
||||
"MetricName": "CPU_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
|
||||
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
|
||||
"MetricGroup": "Summary;Power",
|
||||
"MetricName": "Average_Frequency"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Giga Floating Point Operations Per Second",
|
||||
"MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 ) / duration_time",
|
||||
"MetricGroup": "FLOPS;Summary",
|
||||
"MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
|
||||
"MetricGroup": "Cor;Flops;HPC",
|
||||
"MetricName": "GFLOPs"
|
||||
},
|
||||
{
|
||||
@ -291,22 +374,46 @@
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
|
||||
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
|
||||
"MetricGroup": "SMT;Summary",
|
||||
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
|
||||
"MetricGroup": "SMT",
|
||||
"MetricName": "SMT_2T_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of cycles spent in Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Summary",
|
||||
"BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "OS",
|
||||
"MetricName": "Kernel_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
|
||||
"MetricGroup": "OS",
|
||||
"MetricName": "Kernel_CPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
|
||||
"MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
|
||||
"MetricName": "DRAM_BW_Use"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
|
||||
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
|
||||
"MetricGroup": "Mem;SoC",
|
||||
"MetricName": "MEM_Request_Latency"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
|
||||
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
|
||||
"MetricGroup": "Mem;SoC",
|
||||
"MetricName": "MEM_Parallel_Requests"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
|
||||
"MetricGroup": "Branches;OS",
|
||||
"MetricName": "IpFarBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "C3 residency percent per core",
|
||||
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,172 +1,193 @@
|
||||
[
|
||||
{
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
|
||||
"EventCode": "0xC1",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"Errata": "BDM30",
|
||||
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable (Precise Event)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
|
||||
"EventCode": "0xC1",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"Errata": "BDM30",
|
||||
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable (Precise Event)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x15",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
|
||||
"SampleAfterValue": "2000006",
|
||||
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2a",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
|
||||
"SampleAfterValue": "2000005",
|
||||
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
|
||||
"SampleAfterValue": "2000006",
|
||||
"UMask": "0x15"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x3c",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
|
||||
"SampleAfterValue": "2000004",
|
||||
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x3c"
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
|
||||
"EventCode": "0xCA",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "FP_ASSIST.X87_OUTPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise Event)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3"
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
|
||||
"EventCode": "0xCA",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "FP_ASSIST.X87_INPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand (Precise Event)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
|
||||
"EventCode": "0xCA",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "FP_ASSIST.SIMD_OUTPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "SSE* FP micro-code assist when output value is invalid. (Precise Event)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts any input SSE* floating-point (FP) assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
|
||||
"EventCode": "0xCA",
|
||||
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "FP_ASSIST.SIMD_INPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Any input SSE* FP Assist - (Precise Event)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
|
||||
"SampleAfterValue": "2000005",
|
||||
"UMask": "0x2a"
|
||||
},
|
||||
{
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. Uses PEBS.",
|
||||
"EventCode": "0xCA",
|
||||
"BriefDescription": "Cycles with any input/output SSE or FP assist",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1e",
|
||||
"EventName": "FP_ASSIST.ANY",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts any FP_ASSIST umask was incrementing (Precise Event)",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.ANY",
|
||||
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1e"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD FP assists due to input values",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.SIMD_INPUT",
|
||||
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD FP assists due to Output values",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.SIMD_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of X87 assists due to input value.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.X87_INPUT",
|
||||
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of X87 assists due to output value.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.X87_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x58",
|
||||
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x58",
|
||||
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM30",
|
||||
"EventCode": "0xC1",
|
||||
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
|
||||
"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM30",
|
||||
"EventCode": "0xC1",
|
||||
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
|
||||
"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xA0",
|
||||
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
|
||||
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3"
|
||||
}
|
||||
]
|
||||
@ -1,286 +1,295 @@
|
||||
[
|
||||
{
|
||||
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "IDQ.EMPTY",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xe6",
|
||||
"EventName": "BACLEARS.ANY",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1f"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xAB",
|
||||
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
|
||||
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "IDQ.MITE_CYCLES",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.IFDATA_STALL",
|
||||
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "IDQ.DSB_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "IDQ.MS_DSB_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "IDQ.MS_DSB_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EdgeDetect": "1",
|
||||
"EventName": "IDQ.MS_DSB_OCCUR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x18",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "4",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x18",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "IDQ.MS_MITE_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x24",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles MITE is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "4",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x24",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles MITE is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x30",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x30",
|
||||
"EventName": "IDQ.MS_CYCLES",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.EMPTY",
|
||||
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_ALL_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3c"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x30",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_OCCUR",
|
||||
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_SWITCHES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x3c",
|
||||
"EventName": "IDQ.MITE_ALL_UOPS",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"SampleAfterValue": "200003",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "ICACHE.IFDATA_STALL",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding \u201c4 \u2013 x\u201d when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "4",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"CounterMask": "3",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"Invert": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "3",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "2",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
|
||||
"CounterMask": "2",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"Invert": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0\u20132 cycles.",
|
||||
"EventCode": "0xAB",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,44 +1,44 @@
|
||||
[
|
||||
{
|
||||
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
|
||||
"EventCode": "0x5C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "CPL_CYCLES.RING0",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING0",
|
||||
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
|
||||
"EventCode": "0x5C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EdgeDetect": "1",
|
||||
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x5C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "CPL_CYCLES.RING123",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||||
"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
|
||||
"SampleAfterValue": "100007",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
|
||||
"EventCode": "0x63",
|
||||
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING123",
|
||||
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x63",
|
||||
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
|
||||
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,388 +1,388 @@
|
||||
[
|
||||
{
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0xe",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"EventCode": "0x08",
|
||||
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x40",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x60",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0xe",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
|
||||
"SampleAfterValue": "100003",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x40",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x60",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
|
||||
"EventCode": "0x4F",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "EPT.WALK_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycle count for an Extended Page table walk.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Misses at all ITLB levels that cause page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0xe",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventName": "ITLB_MISSES.WALK_DURATION",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_4K",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "Cycle count for an Extended Page table walk.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x40",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_2M",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x4F",
|
||||
"EventName": "EPT.WALK_CYCLES",
|
||||
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xAE",
|
||||
"EventName": "ITLB.ITLB_FLUSH",
|
||||
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
|
||||
"SampleAfterValue": "100007",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Misses at all ITLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x60",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
|
||||
"EventCode": "0xAE",
|
||||
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ITLB.ITLB_FLUSH",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x11",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x11"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L2.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x12",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L2.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x12"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x14",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"BriefDescription": "Number of DTLB page walker hits in Memory.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x18",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of DTLB page walker hits in Memory.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x21",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x21"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L2.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x22",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L2.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x22"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x24",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
|
||||
"EventCode": "0xBD",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "TLB_FLUSH.DTLB_THREAD",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xBD",
|
||||
"EventName": "TLB_FLUSH.DTLB_THREAD",
|
||||
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
|
||||
"SampleAfterValue": "100007",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
|
||||
"EventCode": "0xBD",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "TLB_FLUSH.STLB_ANY",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "STLB flush attempts",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xBD",
|
||||
"EventName": "TLB_FLUSH.STLB_ANY",
|
||||
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
|
||||
"SampleAfterValue": "100007",
|
||||
"UMask": "0x20"
|
||||
}
|
||||
]
|
||||
@ -1,104 +1,369 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per logical thread)",
|
||||
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Frontend_Bound",
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Frontend_Bound_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Bad_Speculation",
|
||||
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Bad_Speculation_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
|
||||
"MetricConstraint": "NO_NMI_WATCHDOG",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Backend_Bound",
|
||||
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Backend_Bound_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Retiring",
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Retiring_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "TopDownL1",
|
||||
"MetricGroup": "Ret;Summary",
|
||||
"MetricName": "IPC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops Per Instruction",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Pipeline",
|
||||
"MetricGroup": "Pipeline;Ret;Retire",
|
||||
"MetricName": "UPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions",
|
||||
"MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
|
||||
"MetricGroup": "Frontend",
|
||||
"MetricName": "IFetch_Line_Utilization"
|
||||
"BriefDescription": "Instruction per taken branch",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;FetchBW",
|
||||
"MetricName": "UpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)",
|
||||
"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
|
||||
"MetricGroup": "DSB; Frontend_Bandwidth",
|
||||
"MetricName": "DSB_Coverage"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Per Instruction (threaded)",
|
||||
"MetricExpr": "1 / INST_RETIRED.ANY / cycles",
|
||||
"MetricGroup": "Pipeline;Summary",
|
||||
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
|
||||
"MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "Pipeline;Mem",
|
||||
"MetricName": "CPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune.",
|
||||
"BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricGroup": "Pipeline",
|
||||
"MetricName": "CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total issue-pipeline slots",
|
||||
"MetricExpr": "4*( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles",
|
||||
"MetricGroup": "TopDownL1",
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
|
||||
"MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "TmaL1",
|
||||
"MetricName": "SLOTS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total number of retired Instructions",
|
||||
"MetricExpr": "INST_RETIRED.ANY",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricName": "Instructions"
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
|
||||
"MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "TmaL1_SMT",
|
||||
"MetricName": "SLOTS_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles",
|
||||
"MetricGroup": "SMT",
|
||||
"BriefDescription": "The ratio of Executed- by Issued-Uops",
|
||||
"MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
|
||||
"MetricGroup": "Cor;Pipeline",
|
||||
"MetricName": "Execute_per_Issue",
|
||||
"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Ret;SMT;TmaL1",
|
||||
"MetricName": "CoreIPC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Ret;SMT;TmaL1_SMT",
|
||||
"MetricName": "CoreIPC_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating Point Operations Per Cycle",
|
||||
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Ret;Flops",
|
||||
"MetricName": "FLOPc"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating Point Operations Per Cycle",
|
||||
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Ret;Flops_SMT",
|
||||
"MetricName": "FLOPc_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)",
|
||||
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",
|
||||
"MetricGroup": "Cor;Flops;HPC",
|
||||
"MetricName": "FP_Arith_Utilization",
|
||||
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",
|
||||
"MetricGroup": "Cor;Flops;HPC_SMT",
|
||||
"MetricName": "FP_Arith_Utilization_SMT",
|
||||
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
|
||||
"MetricExpr": "UOPS_EXECUTED.THREAD / ( cpu@uops_executed.core\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
|
||||
"MetricGroup": "Pipeline;Ports_Utilization",
|
||||
"MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
|
||||
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
|
||||
"MetricName": "ILP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average Branch Address Clear Cost (fraction of cycles)",
|
||||
"MetricExpr": "2* ( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL - ( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7* ITLB_MISSES.WALK_COMPLETED ) ) / RS_EVENTS.EMPTY_END",
|
||||
"MetricGroup": "Unknown_Branches",
|
||||
"MetricName": "BAClear_Cost"
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
|
||||
"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Bad;BrMispredicts",
|
||||
"MetricName": "Branch_Misprediction_Cost"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core actual clocks when any thread is active on the physical core",
|
||||
"MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD",
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
|
||||
"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Bad;BrMispredicts_SMT",
|
||||
"MetricName": "Branch_Misprediction_Cost_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Bad;BadSpec;BrMispredicts",
|
||||
"MetricName": "IpMispredict"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
|
||||
"MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "SMT",
|
||||
"MetricName": "CORE_CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
|
||||
"MetricGroup": "Memory_Bound;Memory_Lat",
|
||||
"MetricName": "Load_Miss_Real_Latency"
|
||||
"BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
|
||||
"MetricGroup": "InsType",
|
||||
"MetricName": "IpLoad"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / ( cpu@l1d_pend_miss.pending_cycles\\,any\\=1@ / 2) if #SMT_on else L1D_PEND_MISS.PENDING_CYCLES",
|
||||
"MetricGroup": "Memory_Bound;Memory_BW",
|
||||
"BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
|
||||
"MetricGroup": "InsType",
|
||||
"MetricName": "IpStore"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Branches;Fed;InsType",
|
||||
"MetricName": "IpBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
|
||||
"MetricGroup": "Branches;Fed;PGO",
|
||||
"MetricName": "IpCall"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction per taken branch",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
|
||||
"MetricName": "IpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch instructions per taken branch.",
|
||||
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;PGO",
|
||||
"MetricName": "BpTkBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;InsType",
|
||||
"MetricName": "IpFLOP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )",
|
||||
"MetricGroup": "Flops;InsType",
|
||||
"MetricName": "IpArith",
|
||||
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"MetricGroup": "Flops;FpScalar;InsType",
|
||||
"MetricName": "IpArith_Scalar_SP",
|
||||
"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"MetricGroup": "Flops;FpScalar;InsType",
|
||||
"MetricName": "IpArith_Scalar_DP",
|
||||
"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;FpVector;InsType",
|
||||
"MetricName": "IpArith_AVX128",
|
||||
"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;FpVector;InsType",
|
||||
"MetricName": "IpArith_AVX256",
|
||||
"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
|
||||
"MetricExpr": "INST_RETIRED.ANY",
|
||||
"MetricGroup": "Summary;TmaL1",
|
||||
"MetricName": "Instructions"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
|
||||
"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
|
||||
"MetricGroup": "DSB;Fed;FetchBW",
|
||||
"MetricName": "DSB_Coverage"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
|
||||
"MetricGroup": "Mem;MemoryBound;MemoryLat",
|
||||
"MetricName": "Load_Miss_Real_Latency",
|
||||
"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
|
||||
"MetricGroup": "Mem;MemoryBound;MemoryBW",
|
||||
"MetricName": "MLP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
|
||||
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L1D_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
|
||||
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L2_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
|
||||
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L3_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L1MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;Backend;CacheMisses",
|
||||
"MetricName": "L2MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses;Offcore",
|
||||
"MetricName": "L2MPKI_All"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2MPKI_Load"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
|
||||
"MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2HPKI_All"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2HPKI_Load"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L3MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7*(DTLB_STORE_MISSES.WALK_COMPLETED+DTLB_LOAD_MISSES.WALK_COMPLETED+ITLB_MISSES.WALK_COMPLETED)) / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles",
|
||||
"MetricGroup": "TLB",
|
||||
"MetricConstraint": "NO_NMI_WATCHDOG",
|
||||
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Mem;MemoryTLB",
|
||||
"MetricName": "Page_Walks_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Mem;MemoryTLB_SMT",
|
||||
"MetricName": "Page_Walks_Utilization_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average CPU Utilization",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricGroup": "HPC;Summary",
|
||||
"MetricName": "CPU_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
|
||||
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
|
||||
"MetricGroup": "Summary;Power",
|
||||
"MetricName": "Average_Frequency"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Giga Floating Point Operations Per Second",
|
||||
"MetricExpr": "( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 / duration_time",
|
||||
"MetricGroup": "FLOPS;Summary",
|
||||
"MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
|
||||
"MetricGroup": "Cor;Flops;HPC",
|
||||
"MetricName": "GFLOPs"
|
||||
},
|
||||
{
|
||||
@ -108,17 +373,53 @@
|
||||
"MetricName": "Turbo_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of cycles where both hardware threads were active",
|
||||
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
|
||||
"MetricGroup": "SMT;Summary",
|
||||
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
|
||||
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
|
||||
"MetricGroup": "SMT",
|
||||
"MetricName": "SMT_2T_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of cycles spent in Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Summary",
|
||||
"BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "OS",
|
||||
"MetricName": "Kernel_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
|
||||
"MetricGroup": "OS",
|
||||
"MetricName": "Kernel_CPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
|
||||
"MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time",
|
||||
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
|
||||
"MetricName": "DRAM_BW_Use"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
|
||||
"MetricExpr": "1000000000 * ( cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@ ) / ( cbox_0@event\\=0x0@ / duration_time )",
|
||||
"MetricGroup": "Mem;MemoryLat;SoC",
|
||||
"MetricName": "MEM_Read_Latency"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
|
||||
"MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
|
||||
"MetricGroup": "Mem;MemoryBW;SoC",
|
||||
"MetricName": "MEM_Parallel_Reads"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Socket actual clocks when any core is active on that socket",
|
||||
"MetricExpr": "cbox_0@event\\=0x0@",
|
||||
"MetricGroup": "SoC",
|
||||
"MetricName": "Socket_CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
|
||||
"MetricGroup": "Branches;OS",
|
||||
"MetricName": "IpFarBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "C3 residency percent per core",
|
||||
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,165 +1,193 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0xC1",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
|
||||
"Errata": "BDM30",
|
||||
"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC1",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
|
||||
"Errata": "BDM30",
|
||||
"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x3",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x15",
|
||||
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
|
||||
"SampleAfterValue": "2000006",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc7",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x2a",
|
||||
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
|
||||
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
|
||||
"SampleAfterValue": "2000005",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
|
||||
"SampleAfterValue": "2000006",
|
||||
"UMask": "0x15"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x3c",
|
||||
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
|
||||
"SampleAfterValue": "2000004",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x3c"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of X87 assists due to output value.",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.X87_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Number of X87 assists due to input value.",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.X87_INPUT",
|
||||
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of SIMD FP assists due to Output values",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.SIMD_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
|
||||
"SampleAfterValue": "2000005",
|
||||
"UMask": "0x2a"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with any input/output SSE or FP assist",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x10",
|
||||
"EventName": "FP_ASSIST.ANY",
|
||||
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1e"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD FP assists due to input values",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.SIMD_INPUT",
|
||||
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x1e",
|
||||
"BriefDescription": "Cycles with any input/output SSE or FP assist",
|
||||
"BriefDescription": "Number of SIMD FP assists due to Output values",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.ANY",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.SIMD_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of X87 assists due to input value.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.X87_INPUT",
|
||||
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of X87 assists due to output value.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.X87_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x58",
|
||||
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x58",
|
||||
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM30",
|
||||
"EventCode": "0xC1",
|
||||
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
|
||||
"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM30",
|
||||
"EventCode": "0xC1",
|
||||
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
|
||||
"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xA0",
|
||||
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
|
||||
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3"
|
||||
}
|
||||
]
|
||||
@ -1,286 +1,295 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
|
||||
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.EMPTY",
|
||||
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xe6",
|
||||
"EventName": "BACLEARS.ANY",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1f"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MITE_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.DSB_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_DSB_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_DSB_OCCUR",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x18",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x18",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x24",
|
||||
"BriefDescription": "Cycles MITE is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x24",
|
||||
"BriefDescription": "Cycles MITE is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x30",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x30",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x30",
|
||||
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_SWITCHES",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x3c",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MITE_ALL_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
|
||||
"SampleAfterValue": "200003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ICACHE.IFDATA_STALL",
|
||||
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
|
||||
"CounterMask": "3",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
|
||||
"CounterMask": "2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xAB",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xAB",
|
||||
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
|
||||
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.IFDATA_STALL",
|
||||
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "4",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles MITE is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "4",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles MITE is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.EMPTY",
|
||||
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_ALL_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3c"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_OCCUR",
|
||||
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_SWITCHES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "4",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"Invert": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "3",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "2",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
@ -1,432 +1,432 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x05",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "MISALIGN_MEM_REF.LOADS",
|
||||
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x05",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "MISALIGN_MEM_REF.STORES",
|
||||
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x54",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of times a TSX line had a cache conflict",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_MEM.ABORT_CONFLICT",
|
||||
"PublicDescription": "Number of times a TSX line had a cache conflict.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x54",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x54",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x54",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x54",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x54",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x54",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Number of times we could not allocate Lock Buffer",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
|
||||
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5d",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_EXEC.MISC1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5d",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_EXEC.MISC2",
|
||||
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5d",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_EXEC.MISC3",
|
||||
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5d",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_EXEC.MISC4",
|
||||
"PublicDescription": "RTM region detected inside HLE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5d",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "TX_EXEC.MISC5",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC3",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
|
||||
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "HLE_RETIRED.START",
|
||||
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of times HLE commit succeeded",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "HLE_RETIRED.COMMIT",
|
||||
"PublicDescription": "Number of times HLE commit succeeded.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Number of times HLE abort was triggered (PEBS)",
|
||||
"PEBS": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.ABORTED",
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "Number of times HLE abort was triggered (PEBS).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.ABORTED_MISC1",
|
||||
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.ABORTED_MISC2",
|
||||
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.ABORTED_MISC3",
|
||||
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.ABORTED_MISC4",
|
||||
"PublicDescription": "Number of times HLE caused a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc8",
|
||||
"UMask": "0x80",
|
||||
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.ABORTED_MISC5",
|
||||
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
|
||||
"BriefDescription": "Number of times HLE commit succeeded",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "RTM_RETIRED.START",
|
||||
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.COMMIT",
|
||||
"PublicDescription": "Number of times HLE commit succeeded.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of times RTM commit succeeded",
|
||||
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "RTM_RETIRED.COMMIT",
|
||||
"PublicDescription": "Number of times RTM commit succeeded.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xc8",
|
||||
"EventName": "HLE_RETIRED.START",
|
||||
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC3",
|
||||
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
|
||||
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 128",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x80",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above 128.",
|
||||
"SampleAfterValue": "1009",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 16",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x10",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above 16.",
|
||||
"SampleAfterValue": "20011",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 256",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x100",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above 256.",
|
||||
"SampleAfterValue": "503",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 32",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x20",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above 32.",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 4",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x4",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above four.",
|
||||
"SampleAfterValue": "100003",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 512",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x200",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above 512.",
|
||||
"SampleAfterValue": "101",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 64",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x40",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above 64.",
|
||||
"SampleAfterValue": "2003",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Loads with latency value being above 8",
|
||||
"Counter": "3",
|
||||
"CounterHTOff": "3",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
|
||||
"MSRIndex": "0x3F6",
|
||||
"MSRValue": "0x8",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "This event counts loads with latency value being above eight.",
|
||||
"SampleAfterValue": "50021",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "MISALIGN_MEM_REF.LOADS",
|
||||
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x05",
|
||||
"EventName": "MISALIGN_MEM_REF.STORES",
|
||||
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Number of times RTM abort was triggered (PEBS)",
|
||||
"PEBS": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.ABORTED",
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "Number of times RTM abort was triggered (PEBS).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.ABORTED_MISC1",
|
||||
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.ABORTED_MISC2",
|
||||
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.ABORTED_MISC3",
|
||||
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.ABORTED_MISC4",
|
||||
"PublicDescription": "Number of times a RTM caused a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xc9",
|
||||
"UMask": "0x80",
|
||||
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.ABORTED_MISC5",
|
||||
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 4",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x4",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above four.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Number of times RTM commit succeeded",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.COMMIT",
|
||||
"PublicDescription": "Number of times RTM commit succeeded.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 8",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x8",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above eight.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "50021",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc9",
|
||||
"EventName": "RTM_RETIRED.START",
|
||||
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 16",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x10",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above 16.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "20011",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5d",
|
||||
"EventName": "TX_EXEC.MISC1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 32",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x20",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above 32.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5d",
|
||||
"EventName": "TX_EXEC.MISC2",
|
||||
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 64",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x40",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above 64.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "2003",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5d",
|
||||
"EventName": "TX_EXEC.MISC3",
|
||||
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 128",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x80",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above 128.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "1009",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5d",
|
||||
"EventName": "TX_EXEC.MISC4",
|
||||
"PublicDescription": "RTM region detected inside HLE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 256",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x100",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above 256.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "503",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5d",
|
||||
"EventName": "TX_EXEC.MISC5",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Loads with latency value being above 512",
|
||||
"PEBS": "2",
|
||||
"MSRValue": "0x200",
|
||||
"Counter": "3",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
|
||||
"MSRIndex": "0x3F6",
|
||||
"Errata": "BDM100, BDM35",
|
||||
"PublicDescription": "This event counts loads with latency value being above 512.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "101",
|
||||
"CounterHTOff": "3"
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x54",
|
||||
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of times a TSX line had a cache conflict",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x54",
|
||||
"EventName": "TX_MEM.ABORT_CONFLICT",
|
||||
"PublicDescription": "Number of times a TSX line had a cache conflict.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x54",
|
||||
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x54",
|
||||
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x54",
|
||||
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x54",
|
||||
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
|
||||
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of times we could not allocate Lock Buffer",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x54",
|
||||
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
|
||||
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x40"
|
||||
}
|
||||
]
|
||||
@ -1,44 +1,44 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x5C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING0",
|
||||
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x5C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||||
"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5C",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING123",
|
||||
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x63",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x63",
|
||||
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
|
||||
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,388 +1,388 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0xe",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"Errata": "BDM69",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x60",
|
||||
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
|
||||
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0xe",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x60",
|
||||
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4F",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycle count for an Extended Page table walk.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x4F",
|
||||
"EventName": "EPT.WALK_CYCLES",
|
||||
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Misses at all ITLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0xe",
|
||||
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"Errata": "BDM69",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_DURATION",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x60",
|
||||
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xAE",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xAE",
|
||||
"EventName": "ITLB.ITLB_FLUSH",
|
||||
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Misses at all ITLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x11",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x11"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x12",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L2.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x12"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x14",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x18",
|
||||
"BriefDescription": "Number of DTLB page walker hits in Memory.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x21",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x21"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x22",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L2.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x22"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x24",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xBD",
|
||||
"EventName": "TLB_FLUSH.DTLB_THREAD",
|
||||
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBD",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "STLB flush attempts",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xBD",
|
||||
"EventName": "TLB_FLUSH.STLB_ANY",
|
||||
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x20"
|
||||
}
|
||||
]
|
||||
@ -1,196 +1,170 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Frontend_Bound",
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
|
||||
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Frontend_Bound_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Bad_Speculation",
|
||||
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
|
||||
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Bad_Speculation_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )",
|
||||
"MetricConstraint": "NO_NMI_WATCHDOG",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Backend_Bound",
|
||||
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )",
|
||||
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Backend_Bound_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "TopdownL1",
|
||||
"MetricName": "Retiring",
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. "
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. "
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopdownL1_SMT",
|
||||
"MetricName": "Retiring_SMT",
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "TopDownL1",
|
||||
"MetricGroup": "Ret;Summary",
|
||||
"MetricName": "IPC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops Per Instruction",
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Pipeline;Retire",
|
||||
"MetricGroup": "Pipeline;Ret;Retire",
|
||||
"MetricName": "UPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction per taken branch",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fetch_BW;PGO",
|
||||
"MetricName": "IpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch instructions per taken branch. ",
|
||||
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;PGO",
|
||||
"MetricName": "BpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions",
|
||||
"MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
|
||||
"MetricGroup": "PGO;IcMiss",
|
||||
"MetricName": "IFetch_Line_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
|
||||
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
|
||||
"MetricGroup": "DSB;Fetch_BW",
|
||||
"MetricName": "DSB_Coverage"
|
||||
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;FetchBW",
|
||||
"MetricName": "UpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
|
||||
"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
|
||||
"MetricGroup": "Pipeline;Summary",
|
||||
"MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
|
||||
"MetricGroup": "Pipeline;Mem",
|
||||
"MetricName": "CPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricGroup": "Pipeline",
|
||||
"MetricName": "CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
|
||||
"MetricExpr": "4 * cycles",
|
||||
"MetricGroup": "TopDownL1",
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
|
||||
"MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "TmaL1",
|
||||
"MetricName": "SLOTS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
|
||||
"MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "TopDownL1_SMT",
|
||||
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
|
||||
"MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "TmaL1_SMT",
|
||||
"MetricName": "SLOTS_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Load (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
|
||||
"MetricGroup": "Instruction_Type",
|
||||
"MetricName": "IpL"
|
||||
"BriefDescription": "The ratio of Executed- by Issued-Uops",
|
||||
"MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
|
||||
"MetricGroup": "Cor;Pipeline",
|
||||
"MetricName": "Execute_per_Issue",
|
||||
"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Store (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
|
||||
"MetricGroup": "Instruction_Type",
|
||||
"MetricName": "IpS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Branch (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Branches;Instruction_Type",
|
||||
"MetricName": "IpB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
|
||||
"MetricGroup": "Branches",
|
||||
"MetricName": "IpCall"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total number of retired Instructions",
|
||||
"MetricExpr": "INST_RETIRED.ANY",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricName": "Instructions"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / cycles",
|
||||
"MetricGroup": "SMT",
|
||||
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Ret;SMT;TmaL1",
|
||||
"MetricName": "CoreIPC"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions Per Cycle (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "SMT",
|
||||
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Ret;SMT;TmaL1_SMT",
|
||||
"MetricName": "CoreIPC_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating Point Operations Per Cycle",
|
||||
"MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / cycles",
|
||||
"MetricGroup": "FLOPS",
|
||||
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Ret;Flops",
|
||||
"MetricName": "FLOPc"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating Point Operations Per Cycle",
|
||||
"MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
|
||||
"MetricGroup": "FLOPS_SMT",
|
||||
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
|
||||
"MetricGroup": "Ret;Flops_SMT",
|
||||
"MetricName": "FLOPc_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)",
|
||||
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",
|
||||
"MetricGroup": "Cor;Flops;HPC",
|
||||
"MetricName": "FP_Arith_Utilization",
|
||||
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.",
|
||||
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",
|
||||
"MetricGroup": "Cor;Flops;HPC_SMT",
|
||||
"MetricName": "FP_Arith_Utilization_SMT",
|
||||
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
|
||||
"MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
|
||||
"MetricGroup": "Pipeline",
|
||||
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
|
||||
"MetricName": "ILP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)",
|
||||
"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "BrMispredicts",
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
|
||||
"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Bad;BrMispredicts",
|
||||
"MetricName": "Branch_Misprediction_Cost"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)",
|
||||
"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "BrMispredicts_SMT",
|
||||
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
|
||||
"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Bad;BrMispredicts_SMT",
|
||||
"MetricName": "Branch_Misprediction_Cost_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "BrMispredicts",
|
||||
"MetricGroup": "Bad;BadSpec;BrMispredicts",
|
||||
"MetricName": "IpMispredict"
|
||||
},
|
||||
{
|
||||
@ -200,87 +174,196 @@
|
||||
"MetricName": "CORE_CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
|
||||
"BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
|
||||
"MetricGroup": "InsType",
|
||||
"MetricName": "IpLoad"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
|
||||
"MetricGroup": "InsType",
|
||||
"MetricName": "IpStore"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
|
||||
"MetricGroup": "Branches;Fed;InsType",
|
||||
"MetricName": "IpBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
|
||||
"MetricGroup": "Branches;Fed;PGO",
|
||||
"MetricName": "IpCall"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction per taken branch",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
|
||||
"MetricName": "IpTB"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Branch instructions per taken branch. ",
|
||||
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
|
||||
"MetricGroup": "Branches;Fed;PGO",
|
||||
"MetricName": "BpTkBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;InsType",
|
||||
"MetricName": "IpFLOP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )",
|
||||
"MetricGroup": "Flops;InsType",
|
||||
"MetricName": "IpArith",
|
||||
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"MetricGroup": "Flops;FpScalar;InsType",
|
||||
"MetricName": "IpArith_Scalar_SP",
|
||||
"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"MetricGroup": "Flops;FpScalar;InsType",
|
||||
"MetricName": "IpArith_Scalar_DP",
|
||||
"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;FpVector;InsType",
|
||||
"MetricName": "IpArith_AVX128",
|
||||
"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
|
||||
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
|
||||
"MetricGroup": "Flops;FpVector;InsType",
|
||||
"MetricName": "IpArith_AVX256",
|
||||
"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
|
||||
"MetricExpr": "INST_RETIRED.ANY",
|
||||
"MetricGroup": "Summary;TmaL1",
|
||||
"MetricName": "Instructions"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
|
||||
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
|
||||
"MetricGroup": "DSB;Fed;FetchBW",
|
||||
"MetricName": "DSB_Coverage"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
|
||||
"MetricGroup": "Memory_Bound;Memory_Lat",
|
||||
"MetricName": "Load_Miss_Real_Latency"
|
||||
"MetricGroup": "Mem;MemoryBound;MemoryLat",
|
||||
"MetricName": "Load_Miss_Real_Latency",
|
||||
"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
|
||||
"MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
|
||||
"MetricGroup": "Memory_Bound;Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBound;MemoryBW",
|
||||
"MetricName": "MLP"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * cycles )",
|
||||
"MetricGroup": "TLB",
|
||||
"MetricName": "Page_Walks_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) )",
|
||||
"MetricGroup": "TLB_SMT",
|
||||
"MetricName": "Page_Walks_Utilization_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
|
||||
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L1D_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
|
||||
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L2_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
|
||||
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "Mem;MemoryBW",
|
||||
"MetricName": "L3_Cache_Fill_BW"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L1MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;Backend;CacheMisses",
|
||||
"MetricName": "L2MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses;Offcore",
|
||||
"MetricName": "L2MPKI_All"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2MPKI_Load"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
|
||||
"MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2HPKI_All"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
|
||||
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L2HPKI_Load"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
|
||||
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
|
||||
"MetricGroup": "Cache_Misses",
|
||||
"MetricGroup": "Mem;CacheMisses",
|
||||
"MetricName": "L3MPKI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricConstraint": "NO_NMI_WATCHDOG",
|
||||
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",
|
||||
"MetricGroup": "Mem;MemoryTLB",
|
||||
"MetricName": "Page_Walks_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
|
||||
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",
|
||||
"MetricGroup": "Mem;MemoryTLB_SMT",
|
||||
"MetricName": "Page_Walks_Utilization_SMT"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average CPU Utilization",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
|
||||
"MetricGroup": "Summary",
|
||||
"MetricGroup": "HPC;Summary",
|
||||
"MetricName": "CPU_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
|
||||
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
|
||||
"MetricGroup": "Summary;Power",
|
||||
"MetricName": "Average_Frequency"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Giga Floating Point Operations Per Second",
|
||||
"MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 ) / duration_time",
|
||||
"MetricGroup": "FLOPS;Summary",
|
||||
"MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
|
||||
"MetricGroup": "Cor;Flops;HPC",
|
||||
"MetricName": "GFLOPs"
|
||||
},
|
||||
{
|
||||
@ -291,40 +374,52 @@
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
|
||||
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
|
||||
"MetricGroup": "SMT;Summary",
|
||||
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
|
||||
"MetricGroup": "SMT",
|
||||
"MetricName": "SMT_2T_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Fraction of cycles spent in Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "Summary",
|
||||
"BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
|
||||
"MetricGroup": "OS",
|
||||
"MetricName": "Kernel_Utilization"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
|
||||
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
|
||||
"MetricGroup": "OS",
|
||||
"MetricName": "Kernel_CPI"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
|
||||
"MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
|
||||
"MetricName": "DRAM_BW_Use"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
|
||||
"MetricExpr": "1000000000 * ( cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@ ) / ( cbox_0@event\\=0x0@ / duration_time )",
|
||||
"MetricGroup": "Memory_Lat",
|
||||
"MetricName": "DRAM_Read_Latency"
|
||||
"MetricGroup": "Mem;MemoryLat;SoC",
|
||||
"MetricName": "MEM_Read_Latency"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
|
||||
"MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
|
||||
"MetricGroup": "Memory_BW",
|
||||
"MetricName": "DRAM_Parallel_Reads"
|
||||
"MetricGroup": "Mem;MemoryBW;SoC",
|
||||
"MetricName": "MEM_Parallel_Reads"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Socket actual clocks when any core is active on that socket",
|
||||
"MetricExpr": "cbox_0@event\\=0x0@",
|
||||
"MetricGroup": "",
|
||||
"MetricGroup": "SoC",
|
||||
"MetricName": "Socket_CLKS"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
|
||||
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
|
||||
"MetricGroup": "Branches;OS",
|
||||
"MetricName": "IpFarBranch"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "C3 residency percent per core",
|
||||
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,165 +1,193 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0xC1",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
|
||||
"Errata": "BDM30",
|
||||
"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC1",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
|
||||
"Errata": "BDM30",
|
||||
"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x3",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x15",
|
||||
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
|
||||
"SampleAfterValue": "2000006",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x2a",
|
||||
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
|
||||
"SampleAfterValue": "2000005",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
|
||||
"SampleAfterValue": "2000006",
|
||||
"UMask": "0x15"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC7",
|
||||
"UMask": "0x3c",
|
||||
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)",
|
||||
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
|
||||
"SampleAfterValue": "2000004",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x3c"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of X87 assists due to output value.",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.X87_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Number of X87 assists due to input value.",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.X87_INPUT",
|
||||
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Number of SIMD FP assists due to Output values",
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.SIMD_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xc7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
|
||||
"SampleAfterValue": "2000005",
|
||||
"UMask": "0x2a"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with any input/output SSE or FP assist",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x10",
|
||||
"EventName": "FP_ASSIST.ANY",
|
||||
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1e"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD FP assists due to input values",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.SIMD_INPUT",
|
||||
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCA",
|
||||
"UMask": "0x1e",
|
||||
"BriefDescription": "Cycles with any input/output SSE or FP assist",
|
||||
"BriefDescription": "Number of SIMD FP assists due to Output values",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FP_ASSIST.ANY",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.SIMD_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of X87 assists due to input value.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.X87_INPUT",
|
||||
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of X87 assists due to output value.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCA",
|
||||
"EventName": "FP_ASSIST.X87_OUTPUT",
|
||||
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x58",
|
||||
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x58",
|
||||
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM30",
|
||||
"EventCode": "0xC1",
|
||||
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
|
||||
"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM30",
|
||||
"EventCode": "0xC1",
|
||||
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
|
||||
"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xA0",
|
||||
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
|
||||
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3"
|
||||
}
|
||||
]
|
||||
@ -1,286 +1,295 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
|
||||
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.EMPTY",
|
||||
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xe6",
|
||||
"EventName": "BACLEARS.ANY",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1f"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MITE_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.DSB_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_DSB_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_DSB_OCCUR",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x18",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x18",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x24",
|
||||
"BriefDescription": "Cycles MITE is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x24",
|
||||
"BriefDescription": "Cycles MITE is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x30",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x30",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x30",
|
||||
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MS_SWITCHES",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x79",
|
||||
"UMask": "0x3c",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ.MITE_ALL_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
|
||||
"SampleAfterValue": "200003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x80",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ICACHE.IFDATA_STALL",
|
||||
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
|
||||
"CounterMask": "3",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
|
||||
"CounterMask": "2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0x9C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xAB",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xAB",
|
||||
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
|
||||
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.IFDATA_STALL",
|
||||
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "4",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles MITE is delivering 4 Uops",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "4",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles MITE is delivering any Uop",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
|
||||
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.EMPTY",
|
||||
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_ALL_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3c"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_CYCLES",
|
||||
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_OCCUR",
|
||||
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_DSB_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_MITE_UOPS",
|
||||
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_SWITCHES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x30"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "4",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"Invert": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "3",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
|
||||
"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "2",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"CounterMask": "1",
|
||||
"EventCode": "0x9C",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,44 +1,44 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x5C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING0",
|
||||
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x5C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"CounterMask": "1",
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||||
"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5C",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x5C",
|
||||
"EventName": "CPL_CYCLES.RING123",
|
||||
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x63",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x63",
|
||||
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
|
||||
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,388 +1,388 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0xe",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"Errata": "BDM69",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"UMask": "0x60",
|
||||
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
|
||||
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0xe",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x08",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x49",
|
||||
"UMask": "0x60",
|
||||
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x49",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4F",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycle count for an Extended Page table walk.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x4F",
|
||||
"EventName": "EPT.WALK_CYCLES",
|
||||
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Misses at all ITLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x4",
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x8",
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0xe",
|
||||
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"Errata": "BDM69",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.WALK_DURATION",
|
||||
"Errata": "BDM69",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x85",
|
||||
"UMask": "0x60",
|
||||
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xAE",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xAE",
|
||||
"EventName": "ITLB.ITLB_FLUSH",
|
||||
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Misses at all ITLB levels that cause page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x60"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_2M",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT_4K",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0xe"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
|
||||
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "BDM69",
|
||||
"EventCode": "0x85",
|
||||
"EventName": "ITLB_MISSES.WALK_DURATION",
|
||||
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x11",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x11"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x12",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L2.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x12"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x14",
|
||||
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x18",
|
||||
"BriefDescription": "Number of DTLB page walker hits in Memory.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x18"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x21",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x21"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x22",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L2.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x22"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBC",
|
||||
"UMask": "0x24",
|
||||
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"Errata": "BDM69, BDM98",
|
||||
"EventCode": "0xBC",
|
||||
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
"UMask": "0x24"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBD",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xBD",
|
||||
"EventName": "TLB_FLUSH.DTLB_THREAD",
|
||||
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xBD",
|
||||
"UMask": "0x20",
|
||||
"BriefDescription": "STLB flush attempts",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xBD",
|
||||
"EventName": "TLB_FLUSH.STLB_ANY",
|
||||
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
"UMask": "0x20"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -1,37 +1,41 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
|
||||
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
|
||||
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
|
||||
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
|
||||
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
@ -41,6 +45,7 @@
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
|
||||
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
@ -50,27 +55,60 @@
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
|
||||
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||||
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||||
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xC7",
|
||||
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||||
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCF",
|
||||
"EventName": "FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16",
|
||||
"PublicDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction. Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCF",
|
||||
"EventName": "FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16",
|
||||
"PublicDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"EventCode": "0xCF",
|
||||
"EventName": "FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16",
|
||||
"PublicDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction. Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles with any input/output SSE or FP assist",
|
||||
"Counter": "0,1,2,3",
|
||||
|
||||
@ -30,7 +30,21 @@
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.",
|
||||
"BriefDescription": "Retired Instructions who experienced DSB miss.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC6",
|
||||
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x1",
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3",
|
||||
"EventCode": "0xC6",
|
||||
@ -38,7 +52,7 @@
|
||||
"MSRIndex": "0x3F7",
|
||||
"MSRValue": "0x11",
|
||||
"PEBS": "1",
|
||||
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
|
||||
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
|
||||
"SampleAfterValue": "100007",
|
||||
"TakenAlone": "1",
|
||||
"UMask": "0x1"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -435,6 +435,17 @@
|
||||
"PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
|
||||
"SampleAfterValue": "2000003"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of all retired NOP instructions.",
|
||||
"Counter": "0,1,2,3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||||
"Errata": "SKL091, SKL044",
|
||||
"EventCode": "0xC0",
|
||||
"EventName": "INST_RETIRED.NOP",
|
||||
"PEBS": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
|
||||
"Counter": "1",
|
||||
|
||||
@ -558,6 +558,18 @@
|
||||
"PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.",
|
||||
"Unit": "IIO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xC2",
|
||||
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
|
||||
"FCMask": "0x4",
|
||||
"PerPkg": "1",
|
||||
"PortMask": "0x0f",
|
||||
"PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
|
||||
"UMask": "0x03",
|
||||
"Unit": "IIO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
|
||||
"Counter": "0,1,2,3",
|
||||
@ -606,6 +618,17 @@
|
||||
"UMask": "0x03",
|
||||
"Unit": "IIO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
|
||||
"Counter": "2,3",
|
||||
"EventCode": "0xD5",
|
||||
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
|
||||
"FCMask": "0x04",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
|
||||
"UMask": "0x0f",
|
||||
"Unit": "IIO"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
|
||||
"Counter": "2,3",
|
||||
|
||||
@ -179,246 +179,5 @@
|
||||
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
|
||||
"SampleAfterValue": "100003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x6"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.ALL",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This event is deprecated.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.ALL",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.CISC",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.DECODE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.ITLB",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.OTHER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of consumed retirement slots.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xc2",
|
||||
"EventName": "TOPDOWN_RETIRING.ALL",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003"
|
||||
}
|
||||
]
|
||||
@ -262,6 +262,247 @@
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "20003"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x6"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.ALL",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This event is deprecated.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.ALL",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.CISC",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.DECODE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.ITLB",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.OTHER",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
|
||||
"PDIR_COUNTER": "na",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the total number of consumed retirement slots.",
|
||||
"CollectPEBSRecord": "2",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xc2",
|
||||
"EventName": "TOPDOWN_RETIRING.ALL",
|
||||
"PEBS": "1",
|
||||
"PEBScounters": "0,1,2,3",
|
||||
"SampleAfterValue": "1000003"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
|
||||
"CollectPEBSRecord": "2",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
33
tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
Normal file
33
tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
Normal file
@ -0,0 +1,33 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Cycles the FP divide unit is busy",
|
||||
"CollectPEBSRecord": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xCD",
|
||||
"EventName": "CYCLES_DIV_BUSY.FPDIV",
|
||||
"PublicDescription": "Counts core cycles the floating point divide unit is busy.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Machine clears due to FP assists",
|
||||
"CollectPEBSRecord": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xC3",
|
||||
"EventName": "MACHINE_CLEARS.FP_ASSIST",
|
||||
"PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Floating point divide uops retired. (Precise Event Capable)",
|
||||
"CollectPEBSRecord": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xC2",
|
||||
"EventName": "UOPS_RETIRED.FPDIV",
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Counts the number of floating point divide uops retired.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x8"
|
||||
}
|
||||
]
|
||||
@ -1,52 +1,82 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "BACLEARs asserted for any branch type",
|
||||
"CollectPEBSRecord": "1",
|
||||
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"EventCode": "0xE6",
|
||||
"EventName": "BACLEARS.ALL",
|
||||
"PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
|
||||
"SampleAfterValue": "200003",
|
||||
"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "BACLEARs asserted for conditional branch",
|
||||
"CollectPEBSRecord": "1",
|
||||
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"EventCode": "0xE6",
|
||||
"EventName": "BACLEARS.COND",
|
||||
"PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
|
||||
"SampleAfterValue": "200003",
|
||||
"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture"
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "BACLEARs asserted for return branch",
|
||||
"CollectPEBSRecord": "1",
|
||||
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x3",
|
||||
"EventName": "ICACHE.ACCESSES",
|
||||
"EventCode": "0xE6",
|
||||
"EventName": "BACLEARS.RETURN",
|
||||
"PublicDescription": "Counts BACLEARS on return instructions.",
|
||||
"SampleAfterValue": "200003",
|
||||
"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture"
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Decode restrictions due to predicting wrong instruction length",
|
||||
"CollectPEBSRecord": "1",
|
||||
"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
|
||||
"EventCode": "0xE7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MS_DECODED.MS_ENTRY",
|
||||
"SampleAfterValue": "200003",
|
||||
"BriefDescription": "MS decode starts"
|
||||
},
|
||||
{
|
||||
"CollectPEBSRecord": "1",
|
||||
"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
|
||||
"EventCode": "0xE9",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
|
||||
"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
|
||||
"SampleAfterValue": "200003",
|
||||
"BriefDescription": "Decode restrictions due to predicting wrong instruction length"
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
|
||||
"CollectPEBSRecord": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.ACCESSES",
|
||||
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x3"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
|
||||
"CollectPEBSRecord": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
|
||||
"CollectPEBSRecord": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "MS decode starts",
|
||||
"CollectPEBSRecord": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xE7",
|
||||
"EventName": "MS_DECODED.MS_ENTRY",
|
||||
"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
|
||||
"SampleAfterValue": "200003",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user