mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-12-28 16:56:26 +00:00
Timekeeping and clocksource/event driver updates the second batch:
- A trivial documentation fix in the timekeeping core
- A really boring set of small fixes, enhancements and cleanups in the
drivers code. No new clocksource/clockevent drivers for a change.
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Merge tag 'timers-core-2023-04-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull more timer updates from Thomas Gleixner:
"Timekeeping and clocksource/event driver updates the second batch:
- A trivial documentation fix in the timekeeping core
- A really boring set of small fixes, enhancements and cleanups in
the drivers code. No new clocksource/clockevent drivers for a
change"
* tag 'timers-core-2023-04-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
timekeeping: Fix references to nonexistent ktime_get_fast_ns()
dt-bindings: timer: rockchip: Add rk3588 compatible
dt-bindings: timer: rockchip: Drop superfluous rk3288 compatible
clocksource/drivers/ti: Use of_property_read_bool() for boolean properties
clocksource/drivers/timer-ti-dm: Fix finding alwon timer
clocksource/drivers/davinci: Fix memory leak in davinci_timer_register when init fails
clocksource/drivers/stm32-lp: Drop of_match_ptr for ID table
clocksource/drivers/timer-ti-dm: Convert to platform remove callback returning void
clocksource/drivers/timer-tegra186: Convert to platform remove callback returning void
clocksource/drivers/timer-ti-dm: Improve error message in .remove
clocksource/drivers/timer-stm32-lp: Mark driver as non-removable
clocksource/drivers/sh_mtu2: Mark driver as non-removable
clocksource/drivers/timer-ti-dm: Use of_address_to_resource()
clocksource/drivers/timer-imx-gpt: Remove non-DT function
clocksource/drivers/timer-mediatek: Split out CPUXGPT timers
clocksource/drivers/exynos_mct: Explicitly return 0 for shared timer
This commit is contained in:
Linus Torvalds
commit
7d8d20191c
@ -23,8 +23,8 @@ properties:
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- rockchip,rk3188-timer
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- rockchip,rk3228-timer
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- rockchip,rk3229-timer
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- rockchip,rk3288-timer
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- rockchip,rk3368-timer
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- rockchip,rk3588-timer
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- rockchip,px30-timer
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- const: rockchip,rk3288-timer
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reg:
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@ -479,6 +479,15 @@ config MTK_TIMER
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help
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Support for Mediatek timer driver.
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config MTK_CPUX_TIMER
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bool "MediaTek CPUX timer driver" if COMPILE_TEST
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depends on HAS_IOMEM
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default ARCH_MEDIATEK
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select TIMER_OF
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select CLKSRC_MMIO
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help
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Support for MediaTek CPUXGPT timer driver.
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config SPRD_TIMER
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bool "Spreadtrum timer driver" if EXPERT
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depends on HAS_IOMEM
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@ -51,6 +51,7 @@ obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o
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obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o
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obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o
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obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
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obj-$(CONFIG_MTK_CPUX_TIMER) += timer-mediatek-cpux.o
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obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o
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obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
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obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
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@ -682,7 +682,7 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
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* processor cannot use the global comparator.
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*/
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if (frc_shared)
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return ret;
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return 0;
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return exynos4_clockevent_init();
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}
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@ -484,11 +484,6 @@ static int sh_mtu2_probe(struct platform_device *pdev)
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return 0;
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}
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static int sh_mtu2_remove(struct platform_device *pdev)
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{
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return -EBUSY; /* cannot unregister clockevent */
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}
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static const struct platform_device_id sh_mtu2_id_table[] = {
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{ "sh-mtu2", 0 },
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{ },
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@ -503,10 +498,10 @@ MODULE_DEVICE_TABLE(of, sh_mtu2_of_table);
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static struct platform_driver sh_mtu2_device_driver = {
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.probe = sh_mtu2_probe,
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.remove = sh_mtu2_remove,
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.driver = {
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.name = "sh_mtu2",
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.of_match_table = of_match_ptr(sh_mtu2_of_table),
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.suppress_bind_attrs = true,
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},
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.id_table = sh_mtu2_id_table,
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};
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@ -257,21 +257,25 @@ int __init davinci_timer_register(struct clk *clk,
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resource_size(&timer_cfg->reg),
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"davinci-timer")) {
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pr_err("Unable to request memory region\n");
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return -EBUSY;
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rv = -EBUSY;
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goto exit_clk_disable;
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}
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base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg));
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if (!base) {
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pr_err("Unable to map the register range\n");
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return -ENOMEM;
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rv = -ENOMEM;
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goto exit_mem_region;
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}
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davinci_timer_init(base);
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tick_rate = clk_get_rate(clk);
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clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL);
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if (!clockevent)
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return -ENOMEM;
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if (!clockevent) {
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rv = -ENOMEM;
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goto exit_iounmap_base;
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}
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clockevent->dev.name = "tim12";
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clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT;
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@ -296,7 +300,7 @@ int __init davinci_timer_register(struct clk *clk,
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"clockevent/tim12", clockevent);
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if (rv) {
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pr_err("Unable to request the clockevent interrupt\n");
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return rv;
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goto exit_free_clockevent;
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}
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davinci_clocksource.dev.rating = 300;
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@ -323,13 +327,27 @@ int __init davinci_timer_register(struct clk *clk,
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rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
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if (rv) {
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pr_err("Unable to register clocksource\n");
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return rv;
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goto exit_free_irq;
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}
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sched_clock_register(davinci_timer_read_sched_clock,
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DAVINCI_TIMER_CLKSRC_BITS, tick_rate);
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return 0;
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exit_free_irq:
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free_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start,
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clockevent);
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exit_free_clockevent:
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kfree(clockevent);
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exit_iounmap_base:
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iounmap(base);
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exit_mem_region:
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release_mem_region(timer_cfg->reg.start,
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resource_size(&timer_cfg->reg));
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exit_clk_disable:
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clk_disable_unprepare(clk);
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return rv;
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}
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static int __init of_davinci_timer_register(struct device_node *np)
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@ -420,25 +420,6 @@ static int __init _mxc_timer_init(struct imx_timer *imxtm)
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return mxc_clockevent_init(imxtm);
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}
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void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
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{
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struct imx_timer *imxtm;
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imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
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BUG_ON(!imxtm);
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imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
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imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
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imxtm->base = ioremap(pbase, SZ_4K);
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BUG_ON(!imxtm->base);
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imxtm->type = type;
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imxtm->irq = irq;
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_mxc_timer_init(imxtm);
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}
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static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
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{
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struct imx_timer *imxtm;
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140
drivers/clocksource/timer-mediatek-cpux.c
Normal file
140
drivers/clocksource/timer-mediatek-cpux.c
Normal file
@ -0,0 +1,140 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MediaTek SoCs CPUX General Purpose Timer handling
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*
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* Based on timer-mediatek.c:
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* Copyright (C) 2014 Matthias Brugger <matthias.bgg@gmail.com>
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*
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* Copyright (C) 2022 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include "timer-of.h"
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#define TIMER_SYNC_TICKS 3
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/* cpux mcusys wrapper */
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#define CPUX_CON_REG 0x0
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#define CPUX_IDX_REG 0x4
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/* cpux */
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#define CPUX_IDX_GLOBAL_CTRL 0x0
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#define CPUX_ENABLE BIT(0)
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#define CPUX_CLK_DIV_MASK GENMASK(10, 8)
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#define CPUX_CLK_DIV1 BIT(8)
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#define CPUX_CLK_DIV2 BIT(9)
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#define CPUX_CLK_DIV4 BIT(10)
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#define CPUX_IDX_GLOBAL_IRQ 0x30
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static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to)
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{
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writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
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return readl(timer_of_base(to) + CPUX_CON_REG);
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}
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static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)
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{
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writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
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writel(val, timer_of_base(to) + CPUX_CON_REG);
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}
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static void mtk_cpux_set_irq(struct timer_of *to, bool enable)
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{
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const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask);
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u32 val;
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val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);
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if (enable)
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val |= *irq_mask;
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else
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val &= ~(*irq_mask);
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mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);
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}
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static int mtk_cpux_clkevt_shutdown(struct clock_event_device *clkevt)
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{
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/* Clear any irq */
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mtk_cpux_set_irq(to_timer_of(clkevt), false);
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|
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/*
|
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* Disabling CPUXGPT timer will crash the platform, especially
|
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* if Trusted Firmware is using it (usually, for sleep states),
|
||||
* so we only mask the IRQ and call it a day.
|
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*/
|
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return 0;
|
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}
|
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|
||||
static int mtk_cpux_clkevt_resume(struct clock_event_device *clkevt)
|
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{
|
||||
mtk_cpux_set_irq(to_timer_of(clkevt), true);
|
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return 0;
|
||||
}
|
||||
|
||||
static struct timer_of to = {
|
||||
/*
|
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* There are per-cpu interrupts for the CPUX General Purpose Timer
|
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* but since this timer feeds the AArch64 System Timer we can rely
|
||||
* on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
|
||||
*/
|
||||
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
|
||||
|
||||
.clkevt = {
|
||||
.name = "mtk-cpuxgpt",
|
||||
.cpumask = cpu_possible_mask,
|
||||
.rating = 10,
|
||||
.set_state_shutdown = mtk_cpux_clkevt_shutdown,
|
||||
.tick_resume = mtk_cpux_clkevt_resume,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mtk_cpux_init(struct device_node *node)
|
||||
{
|
||||
u32 freq, val;
|
||||
int ret;
|
||||
|
||||
/* If this fails, bad things are about to happen... */
|
||||
ret = timer_of_init(node, &to);
|
||||
if (ret) {
|
||||
WARN(1, "Cannot start CPUX timers.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if we're given a clock with the right frequency for this
|
||||
* timer, otherwise warn but keep going with the setup anyway, as
|
||||
* that makes it possible to still boot the kernel, even though
|
||||
* it may not work correctly (random lockups, etc).
|
||||
* The reason behind this is that having an early UART may not be
|
||||
* possible for everyone and this gives a chance to retrieve kmsg
|
||||
* for eventual debugging even on consumer devices.
|
||||
*/
|
||||
freq = timer_of_rate(&to);
|
||||
if (freq > 13000000)
|
||||
WARN(1, "Requested unsupported timer frequency %u\n", freq);
|
||||
|
||||
/* Clock input is 26MHz, set DIV2 to achieve 13MHz clock */
|
||||
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);
|
||||
val &= ~CPUX_CLK_DIV_MASK;
|
||||
val |= CPUX_CLK_DIV2;
|
||||
mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to);
|
||||
|
||||
/* Enable all CPUXGPT timers */
|
||||
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);
|
||||
mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to);
|
||||
|
||||
clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
TIMER_OF_DECLARE(mtk_mt6795, "mediatek,mt6795-systimer", mtk_cpux_init);
|
||||
@ -22,19 +22,6 @@
|
||||
|
||||
#define TIMER_SYNC_TICKS (3)
|
||||
|
||||
/* cpux mcusys wrapper */
|
||||
#define CPUX_CON_REG 0x0
|
||||
#define CPUX_IDX_REG 0x4
|
||||
|
||||
/* cpux */
|
||||
#define CPUX_IDX_GLOBAL_CTRL 0x0
|
||||
#define CPUX_ENABLE BIT(0)
|
||||
#define CPUX_CLK_DIV_MASK GENMASK(10, 8)
|
||||
#define CPUX_CLK_DIV1 BIT(8)
|
||||
#define CPUX_CLK_DIV2 BIT(9)
|
||||
#define CPUX_CLK_DIV4 BIT(10)
|
||||
#define CPUX_IDX_GLOBAL_IRQ 0x30
|
||||
|
||||
/* gpt */
|
||||
#define GPT_IRQ_EN_REG 0x00
|
||||
#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
|
||||
@ -85,52 +72,6 @@
|
||||
|
||||
static void __iomem *gpt_sched_reg __read_mostly;
|
||||
|
||||
static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to)
|
||||
{
|
||||
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
|
||||
return readl(timer_of_base(to) + CPUX_CON_REG);
|
||||
}
|
||||
|
||||
static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)
|
||||
{
|
||||
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
|
||||
writel(val, timer_of_base(to) + CPUX_CON_REG);
|
||||
}
|
||||
|
||||
static void mtk_cpux_set_irq(struct timer_of *to, bool enable)
|
||||
{
|
||||
const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask);
|
||||
u32 val;
|
||||
|
||||
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);
|
||||
|
||||
if (enable)
|
||||
val |= *irq_mask;
|
||||
else
|
||||
val &= ~(*irq_mask);
|
||||
|
||||
mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);
|
||||
}
|
||||
|
||||
static int mtk_cpux_clkevt_shutdown(struct clock_event_device *clkevt)
|
||||
{
|
||||
/* Clear any irq */
|
||||
mtk_cpux_set_irq(to_timer_of(clkevt), false);
|
||||
|
||||
/*
|
||||
* Disabling CPUXGPT timer will crash the platform, especially
|
||||
* if Trusted Firmware is using it (usually, for sleep states),
|
||||
* so we only mask the IRQ and call it a day.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_cpux_clkevt_resume(struct clock_event_device *clkevt)
|
||||
{
|
||||
mtk_cpux_set_irq(to_timer_of(clkevt), true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_syst_ack_irq(struct timer_of *to)
|
||||
{
|
||||
/* Clear and disable interrupt */
|
||||
@ -340,60 +281,6 @@ static struct timer_of to = {
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mtk_cpux_init(struct device_node *node)
|
||||
{
|
||||
static struct timer_of to_cpux;
|
||||
u32 freq, val;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* There are per-cpu interrupts for the CPUX General Purpose Timer
|
||||
* but since this timer feeds the AArch64 System Timer we can rely
|
||||
* on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
|
||||
*/
|
||||
to_cpux.flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
|
||||
to_cpux.clkevt.name = "mtk-cpuxgpt";
|
||||
to_cpux.clkevt.rating = 10;
|
||||
to_cpux.clkevt.cpumask = cpu_possible_mask;
|
||||
to_cpux.clkevt.set_state_shutdown = mtk_cpux_clkevt_shutdown;
|
||||
to_cpux.clkevt.tick_resume = mtk_cpux_clkevt_resume;
|
||||
|
||||
/* If this fails, bad things are about to happen... */
|
||||
ret = timer_of_init(node, &to_cpux);
|
||||
if (ret) {
|
||||
WARN(1, "Cannot start CPUX timers.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if we're given a clock with the right frequency for this
|
||||
* timer, otherwise warn but keep going with the setup anyway, as
|
||||
* that makes it possible to still boot the kernel, even though
|
||||
* it may not work correctly (random lockups, etc).
|
||||
* The reason behind this is that having an early UART may not be
|
||||
* possible for everyone and this gives a chance to retrieve kmsg
|
||||
* for eventual debugging even on consumer devices.
|
||||
*/
|
||||
freq = timer_of_rate(&to_cpux);
|
||||
if (freq > 13000000)
|
||||
WARN(1, "Requested unsupported timer frequency %u\n", freq);
|
||||
|
||||
/* Clock input is 26MHz, set DIV2 to achieve 13MHz clock */
|
||||
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux);
|
||||
val &= ~CPUX_CLK_DIV_MASK;
|
||||
val |= CPUX_CLK_DIV2;
|
||||
mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to_cpux);
|
||||
|
||||
/* Enable all CPUXGPT timers */
|
||||
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux);
|
||||
mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to_cpux);
|
||||
|
||||
clockevents_config_and_register(&to_cpux.clkevt, timer_of_rate(&to_cpux),
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init mtk_syst_init(struct device_node *node)
|
||||
{
|
||||
int ret;
|
||||
@ -452,4 +339,3 @@ static int __init mtk_gpt_init(struct device_node *node)
|
||||
}
|
||||
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
|
||||
TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
|
||||
TIMER_OF_DECLARE(mtk_mt6795, "mediatek,mt6795-systimer", mtk_cpux_init);
|
||||
|
||||
@ -195,11 +195,6 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_clkevent_lp_remove(struct platform_device *pdev)
|
||||
{
|
||||
return -EBUSY; /* cannot unregister clockevent */
|
||||
}
|
||||
|
||||
static const struct of_device_id stm32_clkevent_lp_of_match[] = {
|
||||
{ .compatible = "st,stm32-lptimer-timer", },
|
||||
{},
|
||||
@ -207,11 +202,11 @@ static const struct of_device_id stm32_clkevent_lp_of_match[] = {
|
||||
MODULE_DEVICE_TABLE(of, stm32_clkevent_lp_of_match);
|
||||
|
||||
static struct platform_driver stm32_clkevent_lp_driver = {
|
||||
.probe = stm32_clkevent_lp_probe,
|
||||
.remove = stm32_clkevent_lp_remove,
|
||||
.probe = stm32_clkevent_lp_probe,
|
||||
.driver = {
|
||||
.name = "stm32-lptimer-timer",
|
||||
.of_match_table = of_match_ptr(stm32_clkevent_lp_of_match),
|
||||
.of_match_table = stm32_clkevent_lp_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
module_platform_driver(stm32_clkevent_lp_driver);
|
||||
|
||||
@ -447,15 +447,13 @@ static int tegra186_timer_probe(struct platform_device *pdev)
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tegra186_timer_remove(struct platform_device *pdev)
|
||||
static void tegra186_timer_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra186_timer *tegra = platform_get_drvdata(pdev);
|
||||
|
||||
clocksource_unregister(&tegra->usec);
|
||||
clocksource_unregister(&tegra->osc);
|
||||
clocksource_unregister(&tegra->tsc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused tegra186_timer_suspend(struct device *dev)
|
||||
@ -505,7 +503,7 @@ static struct platform_driver tegra186_wdt_driver = {
|
||||
.of_match_table = tegra186_timer_of_match,
|
||||
},
|
||||
.probe = tegra186_timer_probe,
|
||||
.remove = tegra186_timer_remove,
|
||||
.remove_new = tegra186_timer_remove,
|
||||
};
|
||||
module_platform_driver(tegra186_wdt_driver);
|
||||
|
||||
|
||||
@ -251,24 +251,24 @@ static void __init dmtimer_systimer_assign_alwon(void)
|
||||
counter_32k = -ENODEV;
|
||||
|
||||
for_each_matching_node(np, dmtimer_match_table) {
|
||||
struct resource res;
|
||||
if (!dmtimer_is_preferred(np))
|
||||
continue;
|
||||
|
||||
if (of_property_read_bool(np, "ti,timer-alwon")) {
|
||||
const __be32 *addr;
|
||||
if (!of_property_read_bool(np, "ti,timer-alwon"))
|
||||
continue;
|
||||
|
||||
addr = of_get_address(np, 0, NULL, NULL);
|
||||
pa = of_translate_address(np, addr);
|
||||
if (pa) {
|
||||
/* Quirky omap3 boards must use dmtimer12 */
|
||||
if (quirk_unreliable_oscillator &&
|
||||
pa == 0x48318000)
|
||||
continue;
|
||||
if (of_address_to_resource(np, 0, &res))
|
||||
continue;
|
||||
|
||||
of_node_put(np);
|
||||
break;
|
||||
}
|
||||
}
|
||||
pa = res.start;
|
||||
|
||||
/* Quirky omap3 boards must use dmtimer12 */
|
||||
if (quirk_unreliable_oscillator && pa == 0x48318000)
|
||||
continue;
|
||||
|
||||
of_node_put(np);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Usually no need for dmtimer clocksource if we have counter32 */
|
||||
@ -285,24 +285,22 @@ static void __init dmtimer_systimer_assign_alwon(void)
|
||||
static u32 __init dmtimer_systimer_find_first_available(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const __be32 *addr;
|
||||
u32 pa = 0;
|
||||
|
||||
for_each_matching_node(np, dmtimer_match_table) {
|
||||
struct resource res;
|
||||
if (!dmtimer_is_preferred(np))
|
||||
continue;
|
||||
|
||||
addr = of_get_address(np, 0, NULL, NULL);
|
||||
pa = of_translate_address(np, addr);
|
||||
if (pa) {
|
||||
if (pa == clocksource || pa == clockevent) {
|
||||
pa = 0;
|
||||
continue;
|
||||
}
|
||||
if (of_address_to_resource(np, 0, &res))
|
||||
continue;
|
||||
|
||||
of_node_put(np);
|
||||
break;
|
||||
}
|
||||
if (res.start == clocksource || res.start == clockevent)
|
||||
continue;
|
||||
|
||||
pa = res.start;
|
||||
of_node_put(np);
|
||||
break;
|
||||
}
|
||||
|
||||
return pa;
|
||||
@ -586,7 +584,7 @@ static int __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
|
||||
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
|
||||
|
||||
pr_info("TI gptimer %s: %s%lu Hz at %pOF\n",
|
||||
name, of_find_property(np, "ti,timer-alwon", NULL) ?
|
||||
name, of_property_read_bool(np, "ti,timer-alwon") ?
|
||||
"always-on " : "", t->rate, np->parent);
|
||||
|
||||
return 0;
|
||||
@ -787,7 +785,7 @@ static int __init dmtimer_clocksource_init(struct device_node *np)
|
||||
t->base + t->ctrl);
|
||||
|
||||
pr_info("TI gptimer clocksource: %s%pOF\n",
|
||||
of_find_property(np, "ti,timer-alwon", NULL) ?
|
||||
of_property_read_bool(np, "ti,timer-alwon") ?
|
||||
"always-on " : "", np->parent);
|
||||
|
||||
if (!dmtimer_sched_clock_counter) {
|
||||
@ -812,7 +810,7 @@ static int __init dmtimer_clocksource_init(struct device_node *np)
|
||||
*/
|
||||
static int __init dmtimer_systimer_init(struct device_node *np)
|
||||
{
|
||||
const __be32 *addr;
|
||||
struct resource res;
|
||||
u32 pa;
|
||||
|
||||
/* One time init for the preferred timer configuration */
|
||||
@ -826,8 +824,9 @@ static int __init dmtimer_systimer_init(struct device_node *np)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
addr = of_get_address(np, 0, NULL, NULL);
|
||||
pa = of_translate_address(np, addr);
|
||||
|
||||
of_address_to_resource(np, 0, &res);
|
||||
pa = (u32)res.start;
|
||||
if (!pa)
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
@ -1104,13 +1104,13 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
||||
platform_set_drvdata(pdev, timer);
|
||||
|
||||
if (dev->of_node) {
|
||||
if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
|
||||
if (of_property_read_bool(dev->of_node, "ti,timer-alwon"))
|
||||
timer->capability |= OMAP_TIMER_ALWON;
|
||||
if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
|
||||
if (of_property_read_bool(dev->of_node, "ti,timer-dsp"))
|
||||
timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
|
||||
if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
|
||||
if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
|
||||
timer->capability |= OMAP_TIMER_HAS_PWM;
|
||||
if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
|
||||
if (of_property_read_bool(dev->of_node, "ti,timer-secure"))
|
||||
timer->capability |= OMAP_TIMER_SECURE;
|
||||
} else {
|
||||
timer->id = pdev->id;
|
||||
@ -1177,7 +1177,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
||||
* In addition to freeing platform resources it also deletes the timer
|
||||
* entry from the local list.
|
||||
*/
|
||||
static int omap_dm_timer_remove(struct platform_device *pdev)
|
||||
static void omap_dm_timer_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dmtimer *timer;
|
||||
unsigned long flags;
|
||||
@ -1197,7 +1197,8 @@ static int omap_dm_timer_remove(struct platform_device *pdev)
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n");
|
||||
}
|
||||
|
||||
static const struct omap_dm_timer_ops dmtimer_ops = {
|
||||
@ -1272,7 +1273,7 @@ MODULE_DEVICE_TABLE(of, omap_timer_match);
|
||||
|
||||
static struct platform_driver omap_dm_timer_driver = {
|
||||
.probe = omap_dm_timer_probe,
|
||||
.remove = omap_dm_timer_remove,
|
||||
.remove_new = omap_dm_timer_remove,
|
||||
.driver = {
|
||||
.name = "omap_timer",
|
||||
.of_match_table = omap_timer_match,
|
||||
|
||||
@ -13,11 +13,4 @@ enum imx_gpt_type {
|
||||
GPT_TYPE_IMX6DL, /* i.MX6DL/SX/SL */
|
||||
};
|
||||
|
||||
/*
|
||||
* This is a stop-gap solution for clock drivers like imx1/imx21 which call
|
||||
* mxc_timer_init() to initialize timer for non-DT boot. It can be removed
|
||||
* when these legacy non-DT support is converted or dropped.
|
||||
*/
|
||||
void mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type);
|
||||
|
||||
#endif /* __SOC_IMX_TIMER_H__ */
|
||||
|
||||
@ -526,7 +526,7 @@ EXPORT_SYMBOL_GPL(ktime_get_raw_fast_ns);
|
||||
* partially updated. Since the tk->offs_boot update is a rare event, this
|
||||
* should be a rare occurrence which postprocessing should be able to handle.
|
||||
*
|
||||
* The caveats vs. timestamp ordering as documented for ktime_get_fast_ns()
|
||||
* The caveats vs. timestamp ordering as documented for ktime_get_mono_fast_ns()
|
||||
* apply as well.
|
||||
*/
|
||||
u64 notrace ktime_get_boot_fast_ns(void)
|
||||
@ -576,7 +576,7 @@ static __always_inline u64 __ktime_get_real_fast(struct tk_fast *tkf, u64 *mono)
|
||||
/**
|
||||
* ktime_get_real_fast_ns: - NMI safe and fast access to clock realtime.
|
||||
*
|
||||
* See ktime_get_fast_ns() for documentation of the time stamp ordering.
|
||||
* See ktime_get_mono_fast_ns() for documentation of the time stamp ordering.
|
||||
*/
|
||||
u64 ktime_get_real_fast_ns(void)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user