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- Several drivers, including atmel-flexcom/rk8xx-core, palmas, and

Browse Source 
tps65010, have undergone minor code improvements to enhance consistency and
   fix race conditions.
 
 - The syscon driver now utilizes the regmap max_register_is_0 capability
   for consistent register map configuration across syscons of all sizes.
 
 - New device support has been added for QCS8300, qcs615, SA8255p, and
   samsung,s2dos05, expanding the range of compatible hardware.
 
 - The cros_ec driver now supports loading cros_ec_ucsi on supported ECs
   and avoids loading the charger with UCSI, streamlining functionality.
 
 - The bd96801 driver now utilizes the more modern maple tree register
   cache, improving performance.
 
 - The da9052-spi driver has undergone a fix to change the read-mask to
   write-mask, preventing potential issues.
 
 - Unused declarations in max77693 have been removed, and support for
   samsung,s2dos05 has been added, enhancing code clarity and device compatibility.
 
 - Error handling in cs42l43 has been fixed to avoid unbalanced regulator
   put and ensure proper synchronization during driver removal.
 
 - The wcd934x driver now uses MODULE_DEVICE_TABLE() instead of
   MODULE_ALIAS(), improving code consistency.
 
 - Documentation for qcom,tcsr, syscon, and atmel-smc has been updated
   and reorganized for better clarity and maintainability.
 
 - The intel_soc_pmic_bxtwc driver has undergone significant improvements,
   including the use of IRQ domains for various devices, fixing IRQ domain names
   duplication, and code refactoring for better consistency and maintainability.
 
 - The ipaq-micro driver has received a fix for a missing break statement in
   the default case, enhancing code robustness.
 
 - Support for the AXP323 PMIC has been added to the axp20x driver, along
   with ensuring a clear relationship between IDs and model names, and allowing
   multiple regulators, broadening hardware compatibility.
 
 - The cs42l43 driver now disables IRQs during suspend for improved power
   management.
 
 - The adp5585 driver has reduced its dependencies by dropping the obsolete
   dependency on COMPILE_TEST.
 
 - Initial support for the MT6328 PMIC has been added to the mt6397 driver,
   expanding the range of supported hardware.
 
 - The rtc-bd70528 driver has been simplified by dropping the IC name from
   IRQ, improving code readability.
 
 - Documentation for qcom,spmi-pmic, ti,twl, and zii,rave-sp has been
   updated to enhance clarity and incorporate new features.
 
 - The rt5033 driver has received a fix for a missing regmap_del_irq_chip()
   in the error handling path.
 
 - New device support has been added for MSM8917, and the
   intel_soc_pmic_crc driver now supports non-ACPI instantiated i2c_client.
 
 - The 88pm886 driver has added support for the RTC cell, and the tqmx86
   driver has improved its GPIO IRQ setup and added I2C IRQ support,
   increasing functionality.
 
 - The sprd,sc2731 DT schema has been updated and converted to YAML format
   for better readability and maintainability.
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Merge tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:

 - Several drivers, including atmel-flexcom/rk8xx-core, palmas, and
   tps65010, have undergone minor code improvements to enhance
   consistency and fix race conditions.

 - The syscon driver now utilizes the regmap max_register_is_0
   capability for consistent register map configuration across syscons
   of all sizes.

 - New device support has been added for QCS8300, qcs615, SA8255p, and
   samsung,s2dos05, expanding the range of compatible hardware.

 - The cros_ec driver now supports loading cros_ec_ucsi on supported ECs
   and avoids loading the charger with UCSI, streamlining functionality.

 - The bd96801 driver now utilizes the more modern maple tree register
   cache, improving performance.

 - The da9052-spi driver has undergone a fix to change the read-mask to
   write-mask, preventing potential issues.

 - Unused declarations in max77693 have been removed, and support for
   samsung,s2dos05 has been added, enhancing code clarity and device
   compatibility.

 - Error handling in cs42l43 has been fixed to avoid unbalanced
   regulator put and ensure proper synchronization during driver
   removal.

 - The wcd934x driver now uses MODULE_DEVICE_TABLE() instead of
   MODULE_ALIAS(), improving code consistency.

 - Documentation for qcom,tcsr, syscon, and atmel-smc has been updated
   and reorganized for better clarity and maintainability.

 - The intel_soc_pmic_bxtwc driver has undergone significant
   improvements, including the use of IRQ domains for various devices,
   fixing IRQ domain names duplication, and code refactoring for better
   consistency and maintainability.

 - The ipaq-micro driver has received a fix for a missing break
   statement in the default case, enhancing code robustness.

 - Support for the AXP323 PMIC has been added to the axp20x driver,
   along with ensuring a clear relationship between IDs and model names,
   and allowing multiple regulators, broadening hardware compatibility.

 - The cs42l43 driver now disables IRQs during suspend for improved
   power management.

 - The adp5585 driver has reduced its dependencies by dropping the
   obsolete dependency on COMPILE_TEST.

 - Initial support for the MT6328 PMIC has been added to the mt6397
   driver, expanding the range of supported hardware.

 - The rtc-bd70528 driver has been simplified by dropping the IC name
   from IRQ, improving code readability.

 - Documentation for qcom,spmi-pmic, ti,twl, and zii,rave-sp has been
   updated to enhance clarity and incorporate new features.

 - The rt5033 driver has received a fix for a missing
   regmap_del_irq_chip() in the error handling path.

 - New device support has been added for MSM8917, and the
   intel_soc_pmic_crc driver now supports non-ACPI instantiated
   i2c_client.

 - The 88pm886 driver has added support for the RTC cell, and the tqmx86
   driver has improved its GPIO IRQ setup and added I2C IRQ support,
   increasing functionality.

 - The sprd,sc2731 DT schema has been updated and converted to YAML
   format for better readability and maintainability.

* tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (62 commits)
  dt-bindings: mfd: bd71828: Use charger resistor in mOhm instead of MOhm
  dt-bindings: mfd: sprd,sc2731: Convert to YAML
  mfd: tqmx86: Add I2C IRQ support
  mfd: tqmx86: Make IRQ setup errors non-fatal
  mfd: tqmx86: Refactor GPIO IRQ setup
  mfd: tqmx86: Improve gpio_irq module parameter description
  mfd: tqmx86: Add board definitions for TQMx120UC, TQMx130UC and TQMxE41S
  mfd: 88pm886: Add the RTC cell
  dt-bindings: mfd: Add Realtek RTL9300 switch peripherals
  mfd: intel_soc_pmic_crc: Add support for non ACPI instantiated i2c_client
  mfd: intel_soc_pmic_*: Consistently use filename as driver name
  dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8917
  mfd: rt5033: Fix missing regmap_del_irq_chip()
  mfd: cgbc-core: Fix error handling paths in cgbc_init_device()
  dt-bindings: mfd: aspeed: Support for AST2700
  mfd: Switch back to struct platform_driver::remove()
  dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
  mfd: rtc: bd7xxxx Drop IC name from IRQ
  mfd: mt6397: Add initial support for MT6328
  mfd: adp5585: Drop obsolete dependency on COMPILE_TEST
  ...
This commit is contained in:
Linus Torvalds 2024-11-22 16:19:47 -08:00
commit 80739fd00c
84 changed files with 3135 additions and 780 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml
View File

@ -80,23 +80,6 @@ required:
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
#address-cells = <1>;
#size-cells = <0>;
adc@480 {
compatible = "sprd,sc2731-adc";
reg = <0x480>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
hwlocks = <&hwlock 4>;
nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
nvmem-cell-names = "big_scale_calib", "small_scale_calib";
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
pmic {

2
Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml
View File

@ -19,7 +19,7 @@ description: |
by the PMIC that is defined as a Multi-Function Device (MFD).
For MediaTek MT6323/MT6397 PMIC bindings see
Documentation/devicetree/bindings/mfd/mt6397.txt
Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
properties:
compatible:

63
Documentation/devicetree/bindings/leds/leds-mt6323.txt
View File

@ -1,63 +0,0 @@
Device Tree Bindings for LED support on MT6323 PMIC
MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED
controllers are defined as the subnode of the function node provided by MT6323
PMIC controller that is being defined as one kind of Muti-Function Device (MFD)
using shared bus called PMIC wrapper for each subfunction to access remote
MT6323 PMIC hardware.
For MT6323 MFD bindings see:
Documentation/devicetree/bindings/mfd/mt6397.txt
For MediaTek PMIC wrapper bindings see:
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
Required properties:
- compatible : Must be one of
- "mediatek,mt6323-led"
- "mediatek,mt6331-led"
- "mediatek,mt6332-led"
- address-cells : Must be 1
- size-cells : Must be 0
Each led is represented as a child node of the mediatek,mt6323-led that
describes the initial behavior for each LED physically and currently only four
LED child nodes can be supported.
Required properties for the LED child node:
- reg : LED channel number (0..3)
Optional properties for the LED child node:
- label : See Documentation/devicetree/bindings/leds/common.txt
- linux,default-trigger : See Documentation/devicetree/bindings/leds/common.txt
- default-state: See Documentation/devicetree/bindings/leds/common.txt
Example:
mt6323: pmic {
compatible = "mediatek,mt6323";
...
mt6323led: leds {
compatible = "mediatek,mt6323-led";
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
label = "LED0";
linux,default-trigger = "timer";
default-state = "on";
};
led@1 {
reg = <1>;
label = "LED1";
default-state = "off";
};
led@2 {
reg = <2>;
label = "LED2";
default-state = "on";
};
};
};

31
Documentation/devicetree/bindings/leds/sprd,sc2731-bltc.yaml
View File

@ -50,35 +50,4 @@ required:
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/leds/common.h>
pmic {
#address-cells = <1>;
#size-cells = <0>;
led-controller@200 {
compatible = "sprd,sc2731-bltc";
reg = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0x0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <0x1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <0x2>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
...

8
Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
View File

@ -9,6 +9,8 @@ title: Aspeed System Control Unit
description:
The Aspeed System Control Unit manages the global behaviour of the SoC,
configuring elements such as clocks, pinmux, and reset.
In AST2700 SOC which has two soc connection, each soc have its own scu
register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
maintainers:
- Joel Stanley <joel@jms.id.au>
@ -21,6 +23,8 @@ properties:
- aspeed,ast2400-scu
- aspeed,ast2500-scu
- aspeed,ast2600-scu
- aspeed,ast2700-scu0
- aspeed,ast2700-scu1
- const: syscon
- const: simple-mfd
@ -30,7 +34,8 @@ properties:
ranges: true
'#address-cells':
const: 1
minimum: 1
maximum: 2
'#size-cells':
const: 1
@ -76,6 +81,7 @@ patternProperties:
- aspeed,ast2400-silicon-id
- aspeed,ast2500-silicon-id
- aspeed,ast2600-silicon-id
- aspeed,ast2700-silicon-id
- const: aspeed,silicon-id
reg:

598
Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml Normal file
View File

@ -0,0 +1,598 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/mediatek,mt6397.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT6397/MT6323 PMIC
maintainers:
- Sen Chu <sen.chu@mediatek.com>
- Macpaul Lin <macpaul.lin@mediatek.com>
description: |
MT6397/MT6323 is a power management system chip.
Please see the sub-modules below for supported features.
MT6397/MT6323 is a multifunction device with the following sub modules:
- Regulators
- RTC
- ADC
- Audio codec
- GPIO
- Clock
- LED
- Keys
- Power controller
It is interfaced to host controller using SPI interface by a proprietary hardware
called PMIC wrapper or pwrap. MT6397/MT6323 PMIC is a child device of pwrap.
See the following for pwrap node definitions:
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6323
- mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332.
- mediatek,mt6358
- mediatek,mt6359
- mediatek,mt6397
- items:
- enum:
- mediatek,mt6366
- const: mediatek,mt6358
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
rtc:
type: object
$ref: /schemas/rtc/rtc.yaml#
unevaluatedProperties: false
description:
MT6397 Real Time Clock.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6323-rtc
- mediatek,mt6331-rtc
- mediatek,mt6358-rtc
- mediatek,mt6397-rtc
- items:
- enum:
- mediatek,mt6366-rtc
- const: mediatek,mt6358-rtc
start-year: true
required:
- compatible
regulators:
type: object
description:
List of child nodes that specify the regulators.
additionalProperties: true
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6323-regulator
- mediatek,mt6358-regulator
- mediatek,mt6359-regulator
- mediatek,mt6397-regulator
- items:
- enum:
- mediatek,mt6366-regulator
- const: mediatek,mt6358-regulator
required:
- compatible
adc:
type: object
$ref: /schemas/iio/adc/mediatek,mt6359-auxadc.yaml#
unevaluatedProperties: false
audio-codec:
type: object
description:
Audio codec support with MT6358 and MT6397.
additionalProperties: true
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6358-sound
- mediatek,mt6359-codec
- mediatek,mt6397-codec
- items:
- enum:
- mediatek,mt6366-sound
- const: mediatek,mt6358-sound
required:
- compatible
clocks:
type: object
additionalProperties: false
description:
This is a clock buffer node for mt6397. However, there are no sub nodes
or any public document exposed in public.
properties:
compatible:
const: mediatek,mt6397-clk
'#clock-cells':
const: 1
required:
- compatible
leds:
type: object
additionalProperties: false
description: |
MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED
controllers are defined as the subnode of the function node provided by MT6323
PMIC controller that is being defined as one kind of Muti-Function Device (MFD)
using shared bus called PMIC wrapper for each subfunction to access remote
MT6323 PMIC hardware.
Each led is represented as a child node of the mediatek,mt6323-led that
describes the initial behavior for each LED physically and currently only four
LED child nodes can be supported.
properties:
compatible:
enum:
- mediatek,mt6323-led
- mediatek,mt6331-led
- mediatek,mt6332-led
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^led@[0-3]$":
type: object
$ref: /schemas/leds/common.yaml#
unevaluatedProperties: false
properties:
reg:
description:
LED channel number (0..3)
minimum: 0
maximum: 3
required:
- reg
required:
- compatible
- "#address-cells"
- "#size-cells"
keys:
type: object
$ref: /schemas/input/mediatek,pmic-keys.yaml
unevaluatedProperties: false
description:
Power and Home keys.
power-controller:
type: object
additionalProperties: false
description:
The power controller which could be found on PMIC is responsible for
externally powering off or on the remote MediaTek SoC through the
circuit BBPU (baseband power up).
properties:
compatible:
const: mediatek,mt6323-pwrc
'#power-domain-cells':
const: 0
pinctrl:
type: object
$ref: /schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml
unevaluatedProperties: false
description:
Pin controller
required:
- compatible
- regulators
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
pmic {
compatible = "mediatek,mt6323";
interrupt-parent = <&pio>;
interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
leds {
compatible = "mediatek,mt6323-led";
#address-cells = <1>;
#size-cells = <0>;
};
regulators {
compatible = "mediatek,mt6323-regulator";
buck_vproc {
regulator-name = "vproc";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
};
buck_vsys {
regulator-name = "vsys";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <2987500>;
regulator-ramp-delay = <25000>;
regulator-always-on;
regulator-boot-on;
};
buck_vpa {
regulator-name = "vpa";
regulator-min-microvolt = < 500000>;
regulator-max-microvolt = <3650000>;
};
ldo_vtcxo {
regulator-name = "vtcxo";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <90>;
regulator-always-on;
regulator-boot-on;
};
ldo_vcn28 {
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <185>;
};
ldo_vcn33_bt {
regulator-name = "vcn33_bt";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3600000>;
regulator-enable-ramp-delay = <185>;
};
ldo_vcn33_wifi {
regulator-name = "vcn33_wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3600000>;
regulator-enable-ramp-delay = <185>;
};
ldo_va {
regulator-name = "va";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
ldo_vcama {
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vio28 {
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
ldo_vusb {
regulator-name = "vusb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
regulator-boot-on;
};
ldo_vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
regulator-boot-on;
};
ldo_vmch {
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
regulator-boot-on;
};
ldo_vemc3v3 {
regulator-name = "vemc3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
regulator-boot-on;
};
ldo_vgp1 {
regulator-name = "vgp1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vgp2 {
regulator-name = "vgp2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vgp3 {
regulator-name = "vgp3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vcn18 {
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vrtc {
regulator-name = "vrtc";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
ldo_vcamaf {
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
};
ldo_vrf18 {
regulator-name = "vrf18";
regulator-min-microvolt = <1825000>;
regulator-max-microvolt = <1825000>;
regulator-enable-ramp-delay = <187>;
};
ldo_vm {
regulator-name = "vm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
ldo_vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
ldo_vcamd {
regulator-name = "vcamd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
ldo_vcamio {
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
};
keys {
compatible = "mediatek,mt6323-keys";
mediatek,long-press-mode = <1>;
power-off-time-sec = <0>;
power {
linux,keycodes = <116>;
wakeup-source;
};
home {
linux,keycodes = <114>;
};
};
power-controller {
compatible = "mediatek,mt6323-pwrc";
#power-domain-cells = <0>;
};
rtc {
compatible = "mediatek,mt6323-rtc";
};
};
- |
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pmic {
compatible = "mediatek,mt6358";
interrupt-controller;
#interrupt-cells = <2>;
audio-codec {
compatible = "mediatek,mt6358-sound";
Avdd-supply = <&mt6358_vaud28_reg>;
mediatek,dmic-mode = <0>;
};
regulators {
compatible = "mediatek,mt6358-regulator";
buck_vdram1 {
regulator-name = "vdram1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2087500>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
regulator-allowed-modes = <0 1>;
};
// ...
ldo_vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <540>;
};
};
rtc {
compatible = "mediatek,mt6358-rtc";
};
keys {
compatible = "mediatek,mt6358-keys";
power {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
home {
linux,keycodes = <KEY_HOME>;
};
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pmic {
compatible = "mediatek,mt6397";
interrupt-parent = <&pio>;
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
audio-codec {
compatible = "mediatek,mt6397-codec";
};
clocks {
compatible = "mediatek,mt6397-clk";
#clock-cells = <1>;
};
pinctrl {
compatible = "mediatek,mt6397-pinctrl";
gpio-controller;
#gpio-cells = <2>;
};
regulators {
compatible = "mediatek,mt6397-regulator";
buck_vpca15 {
regulator-name = "vpca15";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <200>;
};
// ...
ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
};
rtc {
compatible = "mediatek,mt6397-rtc";
};
};

110
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@ -1,110 +0,0 @@
MediaTek MT6397/MT6323 Multifunction Device Driver
MT6397/MT6323 is a multifunction device with the following sub modules:
- Regulator
- RTC
- Audio codec
- GPIO
- Clock
- LED
- Keys
- Power controller
It is interfaced to host controller using SPI interface by a proprietary hardware
called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
See the following for pwarp node definitions:
../soc/mediatek/mediatek,pwrap.yaml
This document describes the binding for MFD device and its sub module.
Required properties:
compatible:
"mediatek,mt6323" for PMIC MT6323
"mediatek,mt6331" for PMIC MT6331 and MT6332
"mediatek,mt6357" for PMIC MT6357
"mediatek,mt6358" for PMIC MT6358
"mediatek,mt6359" for PMIC MT6359
"mediatek,mt6366", "mediatek,mt6358" for PMIC MT6366
"mediatek,mt6397" for PMIC MT6397
Optional subnodes:
- rtc
Required properties: Should be one of follows
- compatible: "mediatek,mt6323-rtc"
- compatible: "mediatek,mt6331-rtc"
- compatible: "mediatek,mt6358-rtc"
- compatible: "mediatek,mt6397-rtc"
For details, see ../rtc/rtc-mt6397.txt
- regulators
Required properties:
- compatible: "mediatek,mt6323-regulator"
see ../regulator/mt6323-regulator.txt
- compatible: "mediatek,mt6358-regulator"
- compatible: "mediatek,mt6366-regulator", "mediatek-mt6358-regulator"
see ../regulator/mt6358-regulator.txt
- compatible: "mediatek,mt6397-regulator"
see ../regulator/mt6397-regulator.txt
- codec
Required properties:
- compatible: "mediatek,mt6397-codec" or "mediatek,mt6358-sound"
- clk
Required properties:
- compatible: "mediatek,mt6397-clk"
- led
Required properties:
- compatible: "mediatek,mt6323-led"
see ../leds/leds-mt6323.txt
- keys
Required properties: Should be one of the following
- compatible: "mediatek,mt6323-keys"
- compatible: "mediatek,mt6331-keys"
- compatible: "mediatek,mt6397-keys"
see ../input/mtk-pmic-keys.txt
- power-controller
Required properties:
- compatible: "mediatek,mt6323-pwrc"
For details, see ../power/reset/mt6323-poweroff.txt
- pin-controller
Required properties:
- compatible: "mediatek,mt6397-pinctrl"
For details, see ../pinctrl/pinctrl-mt65xx.txt
Example:
pwrap: pwrap@1000f000 {
compatible = "mediatek,mt8135-pwrap";
...
pmic {
compatible = "mediatek,mt6397";
codec: mt6397codec {
compatible = "mediatek,mt6397-codec";
};
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1400000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
};
};
};

2
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
View File

@ -76,12 +76,14 @@ properties:
- qcom,pmc8180
- qcom,pmc8180c
- qcom,pmc8380
- qcom,pmd8028
- qcom,pmd9635
- qcom,pmi632
- qcom,pmi8950
- qcom,pmi8962
- qcom,pmi8994
- qcom,pmi8998
- qcom,pmih0108
- qcom,pmk8002
- qcom,pmk8350
- qcom,pmk8550

4
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
View File

@ -21,6 +21,9 @@ properties:
- qcom,msm8998-tcsr
- qcom,qcm2290-tcsr
- qcom,qcs404-tcsr
- qcom,qcs615-tcsr
- qcom,qcs8300-tcsr
- qcom,sa8255p-tcsr
- qcom,sa8775p-tcsr
- qcom,sc7180-tcsr
- qcom,sc7280-tcsr
@ -47,6 +50,7 @@ properties:
- qcom,tcsr-msm8226
- qcom,tcsr-msm8660
- qcom,tcsr-msm8916
- qcom,tcsr-msm8917
- qcom,tcsr-msm8953
- qcom,tcsr-msm8960
- qcom,tcsr-msm8974

114
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@ -0,0 +1,114 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/realtek,rtl9301-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek Switch with Internal CPU
maintainers:
- Chris Packham <chris.packham@alliedtelesis.co.nz>
description:
The RTL9300 is a series of is an Ethernet switches with an integrated CPU. A
number of different peripherals are accessed through a common register block,
represented here as a syscon node.
properties:
compatible:
items:
- enum:
- realtek,rtl9301-switch
- realtek,rtl9302b-switch
- realtek,rtl9302c-switch
- realtek,rtl9303-switch
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
patternProperties:
'reboot@[0-9a-f]+$':
$ref: /schemas/power/reset/syscon-reboot.yaml#
'i2c@[0-9a-f]+$':
$ref: /schemas/i2c/realtek,rtl9301-i2c.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
ethernet-switch@1b000000 {
compatible = "realtek,rtl9301-switch", "syscon", "simple-mfd";
reg = <0x1b000000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
reboot@c {
compatible = "syscon-reboot";
reg = <0x0c 0x4>;
value = <0x01>;
};
i2c@36c {
compatible = "realtek,rtl9301-i2c";
reg = <0x36c 0x14>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
gpio@20 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
gpio@20 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
};
i2c@388 {
compatible = "realtek,rtl9301-i2c";
reg = <0x388 0x14>;
#address-cells = <1>;
#size-cells = <0>;
i2c@7 {
reg = <7>;
#address-cells = <1>;
#size-cells = <0>;
gpio@20 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
};
};

13
Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
View File

@ -55,14 +55,15 @@ properties:
minimum: 0
maximum: 1
rohm,charger-sense-resistor-ohms:
minimum: 10000000
maximum: 50000000
rohm,charger-sense-resistor-micro-ohms:
minimum: 10000
maximum: 50000
default: 30000
description: |
BD71827 and BD71828 have SAR ADC for measuring charging currents.
External sense resistor (RSENSE in data sheet) should be used. If some
other but 30MOhm resistor is used the resistance value should be given
here in Ohms.
other but 30mOhm resistor is used the resistance value should be given
here in microohms.
regulators:
$ref: /schemas/regulator/rohm,bd71828-regulator.yaml
@ -114,7 +115,7 @@ examples:
#gpio-cells = <2>;
gpio-reserved-ranges = <0 1>, <2 1>;
rohm,charger-sense-resistor-ohms = <10000000>;
rohm,charger-sense-resistor-micro-ohms = <10000>;
regulators {
buck1: BUCK1 {

99
Documentation/devicetree/bindings/mfd/samsung,s2dos05.yaml Normal file
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@ -0,0 +1,99 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/samsung,s2dos05.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S2DOS05 Power Management IC
maintainers:
- Dzmitry Sankouski <dsankouski@gmail.com>
description:
This is a device tree bindings for S2DOS family of Power Management IC (PMIC).
The S2DOS05 is a companion power management IC for the panel and touchscreen
in smart phones. Provides voltage regulators and
ADC for power/current measurements.
Regulator section has 4 LDO and 1 BUCK regulators and also
provides ELVDD, ELVSS, AVDD lines.
properties:
compatible:
const: samsung,s2dos05
reg:
maxItems: 1
regulators:
patternProperties:
"^buck|ldo[1-4]$":
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
required:
- regulator-name
additionalProperties: false
required:
- compatible
- reg
- regulators
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@60 {
compatible = "samsung,s2dos05";
reg = <0x60>;
regulators {
ldo1 {
regulator-active-discharge = <1>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2000000>;
regulator-name = "ldo1";
};
ldo2 {
regulator-active-discharge = <1>;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "ldo2";
};
ldo3 {
regulator-active-discharge = <1>;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "ldo3";
};
ldo4 {
regulator-active-discharge = <1>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3775000>;
regulator-name = "ldo4";
};
buck {
regulator-active-discharge = <1>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <2100000>;
regulator-name = "buck";
};
};
};
};
...

252
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@ -0,0 +1,252 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/sprd,sc2731.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Spreadtrum SC27xx PMIC
maintainers:
- Orson Zhai <orsonzhai@gmail.com>
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
description: |
Spreadtrum PMICs belonging to the SC27xx series integrate all mobile handset
power management, audio codec, battery management and user interface support
functions in a single chip. They have 6 major functional blocks:
- DCDCs to support CPU, memory
- LDOs to support both internal and external requirements
- Battery management system, such as charger, fuel gauge
- Audio codec
- User interface functions, such as indicator, flash LED and so on
- IC level interface, such as power on/off control, RTC, typec and so on
properties:
$nodename:
pattern: '^pmic@[0-9a-f]+$'
compatible:
enum:
- sprd,sc2720
- sprd,sc2721
- sprd,sc2723
- sprd,sc2730
- sprd,sc2731
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
spi-max-frequency: true
'#address-cells':
const: 1
'#interrupt-cells':
const: 1
'#size-cells':
const: 0
regulators:
type: object
$ref: /schemas/regulator/sprd,sc2731-regulator.yaml#
patternProperties:
"^adc@[0-9a-f]+$":
type: object
$ref: /schemas/iio/adc/sprd,sc2720-adc.yaml#
"^charger@[0-9a-f]+$":
type: object
$ref: /schemas/power/supply/sc2731-charger.yaml#
"^efuse@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
enum:
- sprd,sc2720-efuse
- sprd,sc2721-efuse
- sprd,sc2723-efuse
- sprd,sc2730-efuse
- sprd,sc2731-efuse
"^fuel-gauge@[0-9a-f]+$":
type: object
$ref: /schemas/power/supply/sc27xx-fg.yaml#
"^gpio@[0-9a-f]+$":
type: object
$ref: /schemas/gpio/sprd,gpio-eic.yaml#
"^led-controller@[0-9a-f]+$":
type: object
$ref: /schemas/leds/sprd,sc2731-bltc.yaml#
"^rtc@[0-9a-f]+$":
type: object
$ref: /schemas/rtc/sprd,sc2731-rtc.yaml#
"^vibrator@[0-9a-f]+$":
type: object
$ref: /schemas/input/sprd,sc27xx-vibrator.yaml#
required:
- compatible
- reg
- interrupts
- interrupt-controller
- spi-max-frequency
- '#address-cells'
- '#interrupt-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
sc2731_pmic: pmic@0 {
compatible = "sprd,sc2731";
reg = <0>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
spi-max-frequency = <26000000>;
#address-cells = <1>;
#interrupt-cells = <1>;
#size-cells = <0>;
charger@0 {
compatible = "sprd,sc2731-charger";
reg = <0x0>;
phys = <&ssphy>;
monitored-battery = <&bat>;
};
led-controller@200 {
compatible = "sprd,sc2731-bltc";
reg = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0x0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <0x1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <0x2>;
color = <LED_COLOR_ID_BLUE>;
};
};
rtc@280 {
compatible = "sprd,sc2731-rtc";
reg = <0x280>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <2>;
};
pmic_eic: gpio@300 {
compatible = "sprd,sc2731-eic";
reg = <0x300>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
efuse@380 {
compatible = "sprd,sc2731-efuse";
reg = <0x380>;
hwlocks = <&hwlock 12>;
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
fgu_calib: calib@6 {
reg = <0x6 0x2>;
bits = <0 9>;
};
adc_big_scale: calib@24 {
reg = <0x24 0x2>;
};
adc_small_scale: calib@26 {
reg = <0x26 0x2>;
};
};
adc@480 {
compatible = "sprd,sc2731-adc";
reg = <0x480>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <0>;
#io-channel-cells = <1>;
hwlocks = <&hwlock 4>;
nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
nvmem-cell-names = "big_scale_calib", "small_scale_calib";
};
fuel-gauge@a00 {
compatible = "sprd,sc2731-fgu";
reg = <0xa00>;
battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <4>;
io-channels = <&pmic_adc 5>, <&pmic_adc 14>;
io-channel-names = "bat-temp", "charge-vol";
nvmem-cells = <&fgu_calib>;
nvmem-cell-names = "fgu_calib";
monitored-battery = <&bat>;
sprd,calib-resistance-micro-ohms = <21500>;
};
vibrator@ec8 {
compatible = "sprd,sc2731-vibrator";
reg = <0xec8>;
};
regulators {
compatible = "sprd,sc2731-regulator";
BUCK_CPU0 {
regulator-name = "vddarm0";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1996875>;
regulator-ramp-delay = <25000>;
regulator-always-on;
};
LDO_CAMA0 {
regulator-name = "vddcama0";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
};
};
};
};
...

40
Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt
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@ -1,40 +0,0 @@
Spreadtrum SC27xx Power Management Integrated Circuit (PMIC)
The Spreadtrum SC27xx series PMICs contain SC2720, SC2721, SC2723, SC2730
and SC2731. The Spreadtrum PMIC belonging to SC27xx series integrates all
mobile handset power management, audio codec, battery management and user
interface support function in a single chip. It has 6 major functional
blocks:
- DCDCs to support CPU, memory.
- LDOs to support both internal and external requirement.
- Battery management system, such as charger, fuel gauge.
- Audio codec.
- User interface function, such as indicator, flash LED and so on.
- IC level interface, such as power on/off control, RTC and typec and so on.
Required properties:
- compatible: Should be one of the following:
"sprd,sc2720"
"sprd,sc2721"
"sprd,sc2723"
"sprd,sc2730"
"sprd,sc2731"
- reg: The address of the device chip select, should be 0.
- spi-max-frequency: Typically set to 26000000.
- interrupts: The interrupt line the device is connected to.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: The number of cells to describe an PMIC IRQ, must be 2.
- #address-cells: Child device offset number of cells, must be 1.
- #size-cells: Child device size number of cells, must be 0.
Example:
pmic@0 {
compatible = "sprd,sc2731";
reg = <0>;
spi-max-frequency = <26000000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
};

2
Documentation/devicetree/bindings/mfd/syscon.yaml
View File

@ -88,6 +88,7 @@ select:
- mediatek,mt8173-pctl-a-syscfg
- mediatek,mt8365-syscfg
- microchip,lan966x-cpu-syscon
- microchip,mpfs-sysreg-scb
- microchip,sam9x60-sfr
- microchip,sama7g5-ddr3phy
- mscc,ocelot-cpu-syscon
@ -185,6 +186,7 @@ properties:
- mediatek,mt8173-pctl-a-syscfg
- mediatek,mt8365-syscfg
- microchip,lan966x-cpu-syscon
- microchip,mpfs-sysreg-scb
- microchip,sam9x60-sfr
- microchip,sama7g5-ddr3phy
- mscc,ocelot-cpu-syscon

32
Documentation/devicetree/bindings/mfd/ti,twl.yaml
View File

@ -54,7 +54,7 @@ allOf:
$ref: /schemas/iio/adc/ti,twl4030-madc.yaml
unevaluatedProperties: false
bci:
charger:
type: object
$ref: /schemas/power/supply/twl4030-charger.yaml
unevaluatedProperties: false
@ -105,6 +105,11 @@ allOf:
regulator-initial-mode: false
properties:
charger:
type: object
properties:
compatible:
const: ti,twl6030-charger
gpadc:
type: object
properties:
@ -136,6 +141,13 @@ allOf:
regulator-initial-mode: false
properties:
charger:
type: object
properties:
compatible:
items:
- const: ti,twl6032-charger
- const: ti,twl6030-charger
gpadc:
type: object
properties:
@ -169,6 +181,14 @@ properties:
"#clock-cells":
const: 1
charger:
type: object
additionalProperties: true
properties:
compatible: true
required:
- compatible
rtc:
type: object
additionalProperties: false
@ -222,6 +242,14 @@ examples:
interrupt-controller;
#interrupt-cells = <1>;
charger {
compatible = "ti,twl6030-charger";
interrupts = <2>, <5>;
io-channels = <&gpadc 10>;
io-channel-names = "vusb";
monitored-battery = <&bat>;
};
gpadc {
compatible = "ti,twl6030-gpadc";
interrupts = <6>;
@ -259,7 +287,7 @@ examples:
interrupt-controller;
#interrupt-cells = <1>;
bci {
charger {
compatible = "ti,twl4030-bci";
interrupts = <9>, <2>;
bci3v1-supply = <&vusb3v1>;

3
Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
View File

@ -71,6 +71,7 @@ allOf:
- x-powers,axp15060
- x-powers,axp305
- x-powers,axp313a
- x-powers,axp323
then:
required:
@ -82,6 +83,7 @@ allOf:
contains:
enum:
- x-powers,axp313a
- x-powers,axp323
- x-powers,axp15060
- x-powers,axp717
@ -100,6 +102,7 @@ properties:
- x-powers,axp221
- x-powers,axp223
- x-powers,axp313a
- x-powers,axp323
- x-powers,axp717
- x-powers,axp803
- x-powers,axp806

39
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt
View File

@ -1,39 +0,0 @@
Zodiac Inflight Innovations RAVE Supervisory Processor
RAVE Supervisory Processor communicates with SoC over UART. It is
expected that its Device Tree node is specified as a child of a node
corresponding to UART controller used for communication.
Required parent device properties:
- compatible: Should be one of:
- "zii,rave-sp-niu"
- "zii,rave-sp-mezz"
- "zii,rave-sp-esb"
- "zii,rave-sp-rdu1"
- "zii,rave-sp-rdu2"
- current-speed: Should be set to baud rate SP device is using
RAVE SP consists of the following sub-devices:
Device Description
------ -----------
rave-sp-wdt : Watchdog
rave-sp-nvmem : Interface to onboard EEPROM
rave-sp-backlight : Display backlight
rave-sp-hwmon : Interface to onboard hardware sensors
rave-sp-leds : Interface to onboard LEDs
rave-sp-input : Interface to onboard power button
Example of usage:
rdu {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
watchdog {
compatible = "zii,rave-sp-watchdog";
};
};

63
Documentation/devicetree/bindings/mfd/zii,rave-sp.yaml Normal file
View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/zii,rave-sp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zodiac Inflight Innovations RAVE Supervisory Processor
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
RAVE Supervisory Processor communicates with SoC over UART. It is
expected that its Device Tree node is specified as a child of a node
corresponding to UART controller used for communication.
properties:
compatible:
enum:
- zii,rave-sp-niu
- zii,rave-sp-mezz
- zii,rave-sp-esb
- zii,rave-sp-rdu1
- zii,rave-sp-rdu2
"#address-cells":
const: 1
"#size-cells":
const: 1
watchdog:
$ref: /schemas/watchdog/zii,rave-sp-wdt.yaml
backlight:
$ref: /schemas/leds/backlight/zii,rave-sp-backlight.yaml
pwrbutton:
$ref: /schemas/input/zii,rave-sp-pwrbutton.yaml
patternProperties:
'^eeprom@[0-9a-f]+$':
$ref: /schemas/nvmem/zii,rave-sp-eeprom.yaml
required:
- compatible
allOf:
- $ref: /schemas/serial/serial-peripheral-props.yaml
unevaluatedProperties: false
examples:
- |
mfd {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
watchdog {
compatible = "zii,rave-sp-watchdog";
};
};

20
Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt
View File

@ -1,20 +0,0 @@
Device Tree Bindings for Power Controller on MediaTek PMIC
The power controller which could be found on PMIC is responsible for externally
powering off or on the remote MediaTek SoC through the circuit BBPU.
Required properties:
- compatible: Should be one of follows
"mediatek,mt6323-pwrc": for MT6323 PMIC
Example:
pmic {
compatible = "mediatek,mt6323";
...
power-controller {
compatible = "mediatek,mt6323-pwrc";
};
}

21
Documentation/devicetree/bindings/power/supply/sc2731-charger.yaml
View File

@ -30,23 +30,4 @@ properties:
- constant-charge-voltage-max-microvolt: maximum constant input voltage.
additionalProperties: false
examples:
- |
bat: battery {
compatible = "simple-battery";
charge-term-current-microamp = <120000>;
constant-charge-voltage-max-microvolt = <4350000>;
};
pmic {
#address-cells = <1>;
#size-cells = <0>;
battery@a00 {
compatible = "sprd,sc2731-charger";
reg = <0x0>;
phys = <&ssphy>;
monitored-battery = <&bat>;
};
};
...

38
Documentation/devicetree/bindings/power/supply/sc27xx-fg.yaml
View File

@ -65,40 +65,4 @@ required:
- monitored-battery
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
bat: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <1900000>;
constant-charge-voltage-max-microvolt = <4350000>;
ocv-capacity-celsius = <20>;
ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
<4022000 85>, <3983000 80>, <3949000 75>,
<3917000 70>, <3889000 65>, <3864000 60>,
<3835000 55>, <3805000 50>, <3787000 45>,
<3777000 40>, <3773000 35>, <3770000 30>,
<3765000 25>, <3752000 20>, <3724000 15>,
<3680000 10>, <3605000 5>, <3400000 0>;
// ...
};
pmic {
#address-cells = <1>;
#size-cells = <0>;
battery@a00 {
compatible = "sprd,sc2731-fgu";
reg = <0xa00>;
battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <4>;
io-channels = <&pmic_adc 5>, <&pmic_adc 14>;
io-channel-names = "bat-temp", "charge-vol";
nvmem-cells = <&fgu_calib>;
nvmem-cell-names = "fgu_calib";
monitored-battery = <&bat>;
sprd,calib-resistance-micro-ohms = <21500>;
};
};
...

21
Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.yaml
View File

@ -43,25 +43,4 @@ required:
- compatible
additionalProperties: false
examples:
- |
regulators {
compatible = "sprd,sc2731-regulator";
BUCK_CPU0 {
regulator-name = "vddarm0";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1996875>;
regulator-ramp-delay = <25000>;
regulator-always-on;
};
LDO_CAMA0 {
regulator-name = "vddcama0";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
};
};
...

31
Documentation/devicetree/bindings/rtc/rtc-mt6397.txt
View File

@ -1,31 +0,0 @@
Device-Tree bindings for MediaTek PMIC based RTC
MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
as a type of multi-function device (MFD). The RTC can be configured and set up
with PMIC wrapper bus which is a common resource shared with the other
functions found on the same PMIC.
For MediaTek PMIC MFD bindings, see:
../mfd/mt6397.txt
For MediaTek PMIC wrapper bus bindings, see:
../soc/mediatek/pwrap.txt
Required properties:
- compatible: Should be one of follows
"mediatek,mt6323-rtc": for MT6323 PMIC
"mediatek,mt6358-rtc": for MT6358 PMIC
"mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
"mediatek,mt6397-rtc": for MT6397 PMIC
Example:
pmic {
compatible = "mediatek,mt6323";
...
rtc {
compatible = "mediatek,mt6323-rtc";
};
};

16
Documentation/devicetree/bindings/rtc/sprd,sc2731-rtc.yaml
View File

@ -30,20 +30,4 @@ allOf:
- $ref: rtc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
#address-cells = <1>;
#size-cells = <0>;
rtc@280 {
compatible = "sprd,sc2731-rtc";
reg = <0x280>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
};
...

10
MAINTAINERS
View File

@ -14458,10 +14458,12 @@ F: Documentation/devicetree/bindings/net/bluetooth/mediatek,mt7921s-bluetooth.ya
F: drivers/bluetooth/btmtkuart.c
MEDIATEK BOARD LEVEL SHUTDOWN DRIVERS
M: Sen Chu <sen.chu@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
M: Macpaul Lin <macpaul.lin@mediatek.com>
L: linux-pm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt
F: Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
F: drivers/power/reset/mt6323-poweroff.c
MEDIATEK CIR DRIVER
@ -14624,9 +14626,11 @@ F: Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
F: drivers/mtd/nand/raw/mtk_*
MEDIATEK PMIC LED DRIVER
M: Sen Chu <sen.chu@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
M: Macpaul Lin <macpaul.lin@mediatek.com>
S: Maintained
F: Documentation/devicetree/bindings/leds/leds-mt6323.txt
F: Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
F: drivers/leds/leds-mt6323.c
MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
@ -20578,7 +20582,7 @@ L: linux-samsung-soc@vger.kernel.org
S: Maintained
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
F: Documentation/devicetree/bindings/mfd/samsung,s2m*.yaml
F: Documentation/devicetree/bindings/mfd/samsung,s2*.yaml
F: Documentation/devicetree/bindings/mfd/samsung,s5m*.yaml
F: Documentation/devicetree/bindings/regulator/samsung,s2m*.yaml
F: Documentation/devicetree/bindings/regulator/samsung,s5m*.yaml

1
drivers/mfd/88pm886.c
View File

@ -37,6 +37,7 @@ static struct resource pm886_onkey_resources[] = {
static struct mfd_cell pm886_devs[] = {
MFD_CELL_RES("88pm886-onkey", pm886_onkey_resources),
MFD_CELL_NAME("88pm886-regulator"),
MFD_CELL_NAME("88pm886-rtc"),
};
static int pm886_power_off_handler(struct sys_off_data *sys_off_data)

2
drivers/mfd/Kconfig
View File

@ -25,7 +25,7 @@ config MFD_ADP5585
select MFD_CORE
select REGMAP_I2C
depends on I2C
depends on OF || COMPILE_TEST
depends on OF
help
Say yes here to add support for the Analog Devices ADP5585 GPIO
expander, PWM and keypad controller. This includes the I2C driver and

2
drivers/mfd/ab8500-sysctrl.c
View File

@ -159,7 +159,7 @@ static struct platform_driver ab8500_sysctrl_driver = {
.of_match_table = ab8500_sysctrl_match,
},
.probe = ab8500_sysctrl_probe,
.remove_new = ab8500_sysctrl_remove,
.remove = ab8500_sysctrl_remove,
};
static int __init ab8500_sysctrl_init(void)

2
drivers/mfd/atmel-flexcom.c
View File

@ -95,7 +95,7 @@ static int __maybe_unused atmel_flexcom_resume_noirq(struct device *dev)
if (err)
return err;
val = FLEX_MR_OPMODE(ddata->opmode),
val = FLEX_MR_OPMODE(ddata->opmode);
writel(val, ddata->base + FLEX_MR);
clk_disable_unprepare(ddata->clk);

4
drivers/mfd/atmel-smc.c
View File

@ -255,8 +255,8 @@ EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
/**
* atmel_hsmc_cs_conf_apply - apply an SMC CS conf
* @regmap: the HSMC regmap
* @cs: the CS id
* @layout: the layout of registers
* @cs: the CS id
* @conf: the SMC CS conf to apply
*
* Applies an SMC CS configuration.
@ -296,8 +296,8 @@ EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
/**
* atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
* @regmap: the HSMC regmap
* @cs: the CS id
* @layout: the layout of registers
* @cs: the CS id
* @conf: the SMC CS conf object to store the current conf
*
* Retrieve the SMC CS configuration.

1
drivers/mfd/axp20x-i2c.c
View File

@ -65,6 +65,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = {
{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
{ .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID },
{ .compatible = "x-powers,axp323", .data = (void *)AXP323_ID },
{ .compatible = "x-powers,axp717", .data = (void *)AXP717_ID },
{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },

58
drivers/mfd/axp20x.c
View File

@ -34,20 +34,21 @@
#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
static const char * const axp20x_model_names[] = {
"AXP152",
"AXP192",
"AXP202",
"AXP209",
"AXP221",
"AXP223",
"AXP288",
"AXP313a",
"AXP717",
"AXP803",
"AXP806",
"AXP809",
"AXP813",
"AXP15060",
[AXP152_ID] = "AXP152",
[AXP192_ID] = "AXP192",
[AXP202_ID] = "AXP202",
[AXP209_ID] = "AXP209",
[AXP221_ID] = "AXP221",
[AXP223_ID] = "AXP223",
[AXP288_ID] = "AXP288",
[AXP313A_ID] = "AXP313a",
[AXP323_ID] = "AXP323",
[AXP717_ID] = "AXP717",
[AXP803_ID] = "AXP803",
[AXP806_ID] = "AXP806",
[AXP809_ID] = "AXP809",
[AXP813_ID] = "AXP813",
[AXP15060_ID] = "AXP15060",
};
static const struct regmap_range axp152_writeable_ranges[] = {
@ -193,6 +194,10 @@ static const struct regmap_range axp313a_writeable_ranges[] = {
regmap_reg_range(AXP313A_ON_INDICATE, AXP313A_IRQ_STATE),
};
static const struct regmap_range axp323_writeable_ranges[] = {
regmap_reg_range(AXP313A_ON_INDICATE, AXP323_DCDC_MODE_CTRL2),
};
static const struct regmap_range axp313a_volatile_ranges[] = {
regmap_reg_range(AXP313A_SHUTDOWN_CTRL, AXP313A_SHUTDOWN_CTRL),
regmap_reg_range(AXP313A_IRQ_STATE, AXP313A_IRQ_STATE),
@ -203,6 +208,11 @@ static const struct regmap_access_table axp313a_writeable_table = {
.n_yes_ranges = ARRAY_SIZE(axp313a_writeable_ranges),
};
static const struct regmap_access_table axp323_writeable_table = {
.yes_ranges = axp323_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp323_writeable_ranges),
};
static const struct regmap_access_table axp313a_volatile_table = {
.yes_ranges = axp313a_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges),
@ -433,6 +443,15 @@ static const struct regmap_config axp313a_regmap_config = {
.cache_type = REGCACHE_MAPLE,
};
static const struct regmap_config axp323_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp323_writeable_table,
.volatile_table = &axp313a_volatile_table,
.max_register = AXP323_DCDC_MODE_CTRL2,
.cache_type = REGCACHE_MAPLE,
};
static const struct regmap_config axp717_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@ -1221,6 +1240,7 @@ static int axp20x_power_off(struct sys_off_data *data)
unsigned int shutdown_reg;
switch (axp20x->variant) {
case AXP323_ID:
case AXP313A_ID:
shutdown_reg = AXP313A_SHUTDOWN_CTRL;
break;
@ -1289,6 +1309,12 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
axp20x->regmap_cfg = &axp313a_regmap_config;
axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
break;
case AXP323_ID:
axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
axp20x->cells = axp313a_cells;
axp20x->regmap_cfg = &axp323_regmap_config;
axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
break;
case AXP717_ID:
axp20x->nr_cells = ARRAY_SIZE(axp717_cells);
axp20x->cells = axp717_cells;
@ -1345,7 +1371,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
axp20x->regmap_irq_chip = &axp15060_regmap_irq_chip;
break;
default:
dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
dev_err(dev, "unsupported AXP20X ID %u\n", axp20x->variant);
return -EINVAL;
}
@ -1419,7 +1445,7 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
}
}
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
ret = mfd_add_devices(axp20x->dev, PLATFORM_DEVID_AUTO, axp20x->cells,
axp20x->nr_cells, NULL, 0, NULL);
if (ret) {

15
drivers/mfd/cgbc-core.c
View File

@ -321,9 +321,18 @@ static int cgbc_init_device(struct cgbc_device_data *cgbc)
ret = cgbc_get_version(cgbc);
if (ret)
return ret;
goto release_session;
return mfd_add_devices(cgbc->dev, -1, cgbc_devs, ARRAY_SIZE(cgbc_devs), NULL, 0, NULL);
ret = mfd_add_devices(cgbc->dev, -1, cgbc_devs, ARRAY_SIZE(cgbc_devs),
NULL, 0, NULL);
if (ret)
goto release_session;
return 0;
release_session:
cgbc_session_release(cgbc);
return ret;
}
static int cgbc_probe(struct platform_device *pdev)
@ -364,7 +373,7 @@ static struct platform_driver cgbc_driver = {
.dev_groups = cgbc_groups,
},
.probe = cgbc_probe,
.remove_new = cgbc_remove,
.remove = cgbc_remove,
};
static const struct dmi_system_id cgbc_dmi_table[] __initconst = {

27
drivers/mfd/cros_ec_dev.c
View File

@ -108,6 +108,10 @@ static const struct mfd_cell cros_ec_keyboard_leds_cells[] = {
{ .name = "cros-keyboard-leds", },
};
static const struct mfd_cell cros_ec_ucsi_cells[] = {
{ .name = "cros_ec_ucsi", },
};
static const struct cros_feature_to_cells cros_subdevices[] = {
{
.id = EC_FEATURE_CEC,
@ -125,9 +129,9 @@ static const struct cros_feature_to_cells cros_subdevices[] = {
.num_cells = ARRAY_SIZE(cros_ec_rtc_cells),
},
{
.id = EC_FEATURE_USB_PD,
.mfd_cells = cros_usbpd_charger_cells,
.num_cells = ARRAY_SIZE(cros_usbpd_charger_cells),
.id = EC_FEATURE_UCSI_PPM,
.mfd_cells = cros_ec_ucsi_cells,
.num_cells = ARRAY_SIZE(cros_ec_ucsi_cells),
},
{
.id = EC_FEATURE_HANG_DETECT,
@ -252,6 +256,21 @@ static int ec_device_probe(struct platform_device *pdev)
}
}
/*
* UCSI provides power supply information so we don't need to separately
* load the cros_usbpd_charger driver.
*/
if (cros_ec_check_features(ec, EC_FEATURE_USB_PD) &&
!cros_ec_check_features(ec, EC_FEATURE_UCSI_PPM)) {
retval = mfd_add_hotplug_devices(ec->dev,
cros_usbpd_charger_cells,
ARRAY_SIZE(cros_usbpd_charger_cells));
if (retval)
dev_warn(ec->dev, "failed to add usbpd-charger: %d\n",
retval);
}
/*
* Lightbar is a special case. Newer devices support autodetection,
* but older ones do not.
@ -346,7 +365,7 @@ static struct platform_driver cros_ec_dev_driver = {
},
.id_table = cros_ec_id,
.probe = ec_device_probe,
.remove_new = ec_device_remove,
.remove = ec_device_remove,
};
static int __init cros_ec_dev_init(void)

65
drivers/mfd/cs42l43.c
View File

@ -967,7 +967,6 @@ static void cs42l43_boot_work(struct work_struct *work)
err:
pm_runtime_put_sync(cs42l43->dev);
cs42l43_dev_remove(cs42l43);
}
static int cs42l43_power_up(struct cs42l43 *cs42l43)
@ -1101,6 +1100,8 @@ EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, MFD_CS42L43);
void cs42l43_dev_remove(struct cs42l43 *cs42l43)
{
cancel_work_sync(&cs42l43->boot_work);
cs42l43_power_down(cs42l43);
}
EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);
@ -1108,16 +1109,39 @@ EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);
static int cs42l43_suspend(struct device *dev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
static const struct reg_sequence mask_all[] = {
{ CS42L43_DECIM_MASK, 0xFFFFFFFF, },
{ CS42L43_EQ_MIX_MASK, 0xFFFFFFFF, },
{ CS42L43_ASP_MASK, 0xFFFFFFFF, },
{ CS42L43_PLL_MASK, 0xFFFFFFFF, },
{ CS42L43_SOFT_MASK, 0xFFFFFFFF, },
{ CS42L43_SWIRE_MASK, 0xFFFFFFFF, },
{ CS42L43_MSM_MASK, 0xFFFFFFFF, },
{ CS42L43_ACC_DET_MASK, 0xFFFFFFFF, },
{ CS42L43_I2C_TGT_MASK, 0xFFFFFFFF, },
{ CS42L43_SPI_MSTR_MASK, 0xFFFFFFFF, },
{ CS42L43_SW_TO_SPI_BRIDGE_MASK, 0xFFFFFFFF, },
{ CS42L43_OTP_MASK, 0xFFFFFFFF, },
{ CS42L43_CLASS_D_AMP_MASK, 0xFFFFFFFF, },
{ CS42L43_GPIO_INT_MASK, 0xFFFFFFFF, },
{ CS42L43_ASRC_MASK, 0xFFFFFFFF, },
{ CS42L43_HPOUT_MASK, 0xFFFFFFFF, },
};
int ret;
/*
* Don't care about being resumed here, but the driver does want
* force_resume to always trigger an actual resume, so that register
* state for the MCU/GPIOs is returned as soon as possible after system
* resume. force_resume will resume if the reference count is resumed on
* suspend hence the get_noresume.
*/
pm_runtime_get_noresume(dev);
ret = pm_runtime_resume_and_get(dev);
if (ret) {
dev_err(cs42l43->dev, "Failed to resume for suspend: %d\n", ret);
return ret;
}
/* The IRQs will be re-enabled on resume by the cache sync */
ret = regmap_multi_reg_write_bypassed(cs42l43->regmap,
mask_all, ARRAY_SIZE(mask_all));
if (ret) {
dev_err(cs42l43->dev, "Failed to mask IRQs: %d\n", ret);
return ret;
}
ret = pm_runtime_force_suspend(dev);
if (ret) {
@ -1132,6 +1156,26 @@ static int cs42l43_suspend(struct device *dev)
if (ret)
return ret;
disable_irq(cs42l43->irq);
return 0;
}
static int cs42l43_suspend_noirq(struct device *dev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
enable_irq(cs42l43->irq);
return 0;
}
static int cs42l43_resume_noirq(struct device *dev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
disable_irq(cs42l43->irq);
return 0;
}
@ -1144,6 +1188,8 @@ static int cs42l43_resume(struct device *dev)
if (ret)
return ret;
enable_irq(cs42l43->irq);
ret = pm_runtime_force_resume(dev);
if (ret) {
dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
@ -1211,6 +1257,7 @@ static int cs42l43_runtime_resume(struct device *dev)
EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_suspend_noirq, cs42l43_resume_noirq)
RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
};

2
drivers/mfd/da9052-spi.c
View File

@ -37,7 +37,7 @@ static int da9052_spi_probe(struct spi_device *spi)
spi_set_drvdata(spi, da9052);
config = da9052_regmap_config;
config.read_flag_mask = 1;
config.write_flag_mask = 1;
config.reg_bits = 7;
config.pad_bits = 1;
config.val_bits = 8;

4
drivers/mfd/exynos-lpass.c
View File

@ -179,13 +179,13 @@ static const struct of_device_id exynos_lpass_of_match[] = {
MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
static struct platform_driver exynos_lpass_driver = {
.driver = {
.driver = {
.name = "exynos-lpass",
.pm = &lpass_pm_ops,
.of_match_table = exynos_lpass_of_match,
},
.probe = exynos_lpass_probe,
.remove_new = exynos_lpass_remove,
.remove = exynos_lpass_remove,
};
module_platform_driver(exynos_lpass_driver);

2
drivers/mfd/fsl-imx25-tsadc.c
View File

@ -211,7 +211,7 @@ static struct platform_driver mx25_tsadc_driver = {
.of_match_table = mx25_tsadc_ids,
},
.probe = mx25_tsadc_probe,
.remove_new = mx25_tsadc_remove,
.remove = mx25_tsadc_remove,
};
module_platform_driver(mx25_tsadc_driver);

8
drivers/mfd/hi655x-pmic.c
View File

@ -159,12 +159,12 @@ static const struct of_device_id hi655x_pmic_match[] = {
MODULE_DEVICE_TABLE(of, hi655x_pmic_match);
static struct platform_driver hi655x_pmic_driver = {
.driver = {
.name = "hi655x-pmic",
.driver = {
.name = "hi655x-pmic",
.of_match_table = hi655x_pmic_match,
},
.probe = hi655x_pmic_probe,
.remove_new = hi655x_pmic_remove,
.probe = hi655x_pmic_probe,
.remove = hi655x_pmic_remove,
};
module_platform_driver(hi655x_pmic_driver);

2
drivers/mfd/intel-lpss-acpi.c
View File

@ -208,7 +208,7 @@ static void intel_lpss_acpi_remove(struct platform_device *pdev)
static struct platform_driver intel_lpss_acpi_driver = {
.probe = intel_lpss_acpi_probe,
.remove_new = intel_lpss_acpi_remove,
.remove = intel_lpss_acpi_remove,
.driver = {
.name = "intel-lpss",
.acpi_match_table = intel_lpss_acpi_ids,

189
drivers/mfd/intel_soc_pmic_bxtwc.c
View File

@ -6,16 +6,27 @@
*/
#include <linux/acpi.h>
#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/gfp_types.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/kstrtox.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/mfd/intel_soc_pmic_bxtwc.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_data/x86/intel_scu_ipc.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/types.h>
/* PMIC device registers */
#define REG_ADDR_MASK GENMASK(15, 8)
@ -148,6 +159,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip = {
static const struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
.name = "bxtwc_irq_chip_pwrbtn",
.domain_suffix = "PWRBTN",
.status_base = BXTWC_PWRBTNIRQ,
.mask_base = BXTWC_MPWRBTNIRQ,
.irqs = bxtwc_regmap_irqs_pwrbtn,
@ -157,6 +169,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
static const struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
.name = "bxtwc_irq_chip_tmu",
.domain_suffix = "TMU",
.status_base = BXTWC_TMUIRQ,
.mask_base = BXTWC_MTMUIRQ,
.irqs = bxtwc_regmap_irqs_tmu,
@ -166,6 +179,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
static const struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
.name = "bxtwc_irq_chip_bcu",
.domain_suffix = "BCU",
.status_base = BXTWC_BCUIRQ,
.mask_base = BXTWC_MBCUIRQ,
.irqs = bxtwc_regmap_irqs_bcu,
@ -175,6 +189,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
static const struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
.name = "bxtwc_irq_chip_adc",
.domain_suffix = "ADC",
.status_base = BXTWC_ADCIRQ,
.mask_base = BXTWC_MADCIRQ,
.irqs = bxtwc_regmap_irqs_adc,
@ -184,6 +199,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
static const struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
.name = "bxtwc_irq_chip_chgr",
.domain_suffix = "CHGR",
.status_base = BXTWC_CHGR0IRQ,
.mask_base = BXTWC_MCHGR0IRQ,
.irqs = bxtwc_regmap_irqs_chgr,
@ -193,6 +209,7 @@ static const struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
static const struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
.name = "bxtwc_irq_chip_crit",
.domain_suffix = "CRIT",
.status_base = BXTWC_CRITIRQ,
.mask_base = BXTWC_MCRITIRQ,
.irqs = bxtwc_regmap_irqs_crit,
@ -230,16 +247,46 @@ static const struct resource tmu_resources[] = {
};
static struct mfd_cell bxt_wc_dev[] = {
{
.name = "bxt_wcove_gpadc",
.num_resources = ARRAY_SIZE(adc_resources),
.resources = adc_resources,
},
{
.name = "bxt_wcove_thermal",
.num_resources = ARRAY_SIZE(thermal_resources),
.resources = thermal_resources,
},
{
.name = "bxt_wcove_gpio",
.num_resources = ARRAY_SIZE(gpio_resources),
.resources = gpio_resources,
},
{
.name = "bxt_wcove_region",
},
};
static const struct mfd_cell bxt_wc_tmu_dev[] = {
{
.name = "bxt_wcove_tmu",
.num_resources = ARRAY_SIZE(tmu_resources),
.resources = tmu_resources,
},
};
static const struct mfd_cell bxt_wc_bcu_dev[] = {
{
.name = "bxt_wcove_bcu",
.num_resources = ARRAY_SIZE(bcu_resources),
.resources = bcu_resources,
},
};
static const struct mfd_cell bxt_wc_adc_dev[] = {
{
.name = "bxt_wcove_gpadc",
.num_resources = ARRAY_SIZE(adc_resources),
.resources = adc_resources,
},
};
static struct mfd_cell bxt_wc_chgr_dev[] = {
{
.name = "bxt_wcove_usbc",
.num_resources = ARRAY_SIZE(usbc_resources),
@ -250,25 +297,6 @@ static struct mfd_cell bxt_wc_dev[] = {
.num_resources = ARRAY_SIZE(charger_resources),
.resources = charger_resources,
},
{
.name = "bxt_wcove_bcu",
.num_resources = ARRAY_SIZE(bcu_resources),
.resources = bcu_resources,
},
{
.name = "bxt_wcove_tmu",
.num_resources = ARRAY_SIZE(tmu_resources),
.resources = tmu_resources,
},
{
.name = "bxt_wcove_gpio",
.num_resources = ARRAY_SIZE(gpio_resources),
.resources = gpio_resources,
},
{
.name = "bxt_wcove_region",
},
};
static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
@ -347,6 +375,7 @@ static ssize_t addr_store(struct device *dev,
return count;
}
static DEVICE_ATTR_ADMIN_RW(addr);
static ssize_t val_show(struct device *dev,
struct device_attribute *attr, char *buf)
@ -383,23 +412,14 @@ static ssize_t val_store(struct device *dev,
}
return count;
}
static DEVICE_ATTR_ADMIN_RW(addr);
static DEVICE_ATTR_ADMIN_RW(val);
static struct attribute *bxtwc_attrs[] = {
&dev_attr_addr.attr,
&dev_attr_val.attr,
NULL
};
static const struct attribute_group bxtwc_group = {
.attrs = bxtwc_attrs,
};
static const struct attribute_group *bxtwc_groups[] = {
&bxtwc_group,
NULL
};
ATTRIBUTE_GROUPS(bxtwc);
static const struct regmap_config bxtwc_regmap_config = {
.reg_bits = 16,
@ -414,15 +434,39 @@ static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
const struct regmap_irq_chip *chip,
struct regmap_irq_chip_data **data)
{
int irq;
struct device *dev = pmic->dev;
int irq, ret;
irq = regmap_irq_get_virq(pdata, pirq);
if (irq < 0)
return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
return dev_err_probe(dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
pirq, chip->name);
return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
0, chip, data);
ret = devm_regmap_add_irq_chip(dev, pmic->regmap, irq, irq_flags, 0, chip, data);
if (ret)
return dev_err_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name);
return 0;
}
static int bxtwc_add_chained_devices(struct intel_soc_pmic *pmic,
const struct mfd_cell *cells, int n_devs,
struct regmap_irq_chip_data *pdata,
int pirq, int irq_flags,
const struct regmap_irq_chip *chip,
struct regmap_irq_chip_data **data)
{
struct device *dev = pmic->dev;
struct irq_domain *domain;
int ret;
ret = bxtwc_add_chained_irq_chip(pmic, pdata, pirq, irq_flags, chip, data);
if (ret)
return ret;
domain = regmap_irq_get_domain(*data);
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, cells, n_devs, NULL, 0, domain);
}
static int bxtwc_probe(struct platform_device *pdev)
@ -466,48 +510,49 @@ static int bxtwc_probe(struct platform_device *pdev)
if (ret)
return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
ret = bxtwc_add_chained_devices(pmic, bxt_wc_tmu_dev, ARRAY_SIZE(bxt_wc_tmu_dev),
pmic->irq_chip_data,
BXTWC_TMU_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_tmu,
&pmic->irq_chip_data_tmu);
if (ret)
return ret;
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_PWRBTN_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_pwrbtn,
&pmic->irq_chip_data_pwrbtn);
if (ret)
return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");
return ret;
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_TMU_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_tmu,
&pmic->irq_chip_data_tmu);
ret = bxtwc_add_chained_devices(pmic, bxt_wc_bcu_dev, ARRAY_SIZE(bxt_wc_bcu_dev),
pmic->irq_chip_data,
BXTWC_BCU_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_bcu,
&pmic->irq_chip_data_bcu);
if (ret)
return dev_err_probe(dev, ret, "Failed to add TMU IRQ chip\n");
return ret;
/* Add chained IRQ handler for BCU IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_BCU_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_bcu,
&pmic->irq_chip_data_bcu);
ret = bxtwc_add_chained_devices(pmic, bxt_wc_adc_dev, ARRAY_SIZE(bxt_wc_adc_dev),
pmic->irq_chip_data,
BXTWC_ADC_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_adc,
&pmic->irq_chip_data_adc);
if (ret)
return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n");
return ret;
/* Add chained IRQ handler for ADC IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_ADC_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_adc,
&pmic->irq_chip_data_adc);
ret = bxtwc_add_chained_devices(pmic, bxt_wc_chgr_dev, ARRAY_SIZE(bxt_wc_chgr_dev),
pmic->irq_chip_data,
BXTWC_CHGR_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_chgr,
&pmic->irq_chip_data_chgr);
if (ret)
return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n");
/* Add chained IRQ handler for CHGR IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_CHGR_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_chgr,
&pmic->irq_chip_data_chgr);
if (ret)
return dev_err_probe(dev, ret, "Failed to add CHGR IRQ chip\n");
return ret;
/* Add chained IRQ handler for CRIT IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@ -516,7 +561,7 @@ static int bxtwc_probe(struct platform_device *pdev)
&bxtwc_regmap_irq_chip_crit,
&pmic->irq_chip_data_crit);
if (ret)
return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");
return ret;
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
NULL, 0, NULL);
@ -571,7 +616,7 @@ static struct platform_driver bxtwc_driver = {
.probe = bxtwc_probe,
.shutdown = bxtwc_shutdown,
.driver = {
.name = "BXTWC PMIC",
.name = "intel_soc_pmic_bxtwc",
.pm = pm_sleep_ptr(&bxtwc_pm_ops),
.acpi_match_table = bxtwc_acpi_ids,
.dev_groups = bxtwc_groups,

2
drivers/mfd/intel_soc_pmic_chtwc.c
View File

@ -267,7 +267,7 @@ static const struct acpi_device_id cht_wc_acpi_ids[] = {
static struct i2c_driver cht_wc_driver = {
.driver = {
.name = "CHT Whiskey Cove PMIC",
.name = "intel_soc_pmic_chtwc",
.pm = pm_sleep_ptr(&cht_wc_pm_ops),
.acpi_match_table = cht_wc_acpi_ids,
},

9
drivers/mfd/intel_soc_pmic_crc.c
View File

@ -259,12 +259,19 @@ static const struct acpi_device_id crystal_cove_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, crystal_cove_acpi_match);
static const struct i2c_device_id crystal_cove_i2c_match[] = {
{ "intel_soc_pmic_crc" },
{ }
};
MODULE_DEVICE_TABLE(i2c, crystal_cove_i2c_match);
static struct i2c_driver crystal_cove_i2c_driver = {
.driver = {
.name = "crystal_cove_i2c",
.name = "intel_soc_pmic_crc",
.pm = pm_sleep_ptr(&crystal_cove_pm_ops),
.acpi_match_table = crystal_cove_acpi_match,
},
.id_table = crystal_cove_i2c_match,
.probe = crystal_cove_i2c_probe,
.remove = crystal_cove_i2c_remove,
.shutdown = crystal_cove_shutdown,

1
drivers/mfd/ipaq-micro.c
View File

@ -130,6 +130,7 @@ static void micro_rx_msg(struct ipaq_micro *micro, u8 id, int len, u8 *data)
default:
dev_err(micro->dev,
"unknown msg %d [%d] %*ph\n", id, len, len, data);
break;
}
spin_unlock(&micro->lock);
}

2
drivers/mfd/kempld-core.c
View File

@ -486,7 +486,7 @@ static struct platform_driver kempld_driver = {
.dev_groups = pld_groups,
},
.probe = kempld_probe,
.remove_new = kempld_remove,
.remove = kempld_remove,
};
static const struct dmi_system_id kempld_dmi_table[] __initconst = {

2
drivers/mfd/mcp-sa11x0.c
View File

@ -286,7 +286,7 @@ static const struct dev_pm_ops mcp_sa11x0_pm_ops = {
static struct platform_driver mcp_sa11x0_driver = {
.probe = mcp_sa11x0_probe,
.remove_new = mcp_sa11x0_remove,
.remove = mcp_sa11x0_remove,
.driver = {
.name = DRIVER_NAME,
.pm = pm_sleep_ptr(&mcp_sa11x0_pm_ops),

32
drivers/mfd/mt6397-core.c
View File

@ -13,12 +13,14 @@
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6328/core.h>
#include <linux/mfd/mt6331/core.h>
#include <linux/mfd/mt6357/core.h>
#include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6359/core.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6328/registers.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6357/registers.h>
#include <linux/mfd/mt6358/registers.h>
@ -87,6 +89,13 @@ static const struct resource mt6323_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"),
};
static const struct resource mt6328_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_HOMEKEY, "homekey"),
DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_PWRKEY_R, "powerkey_r"),
DEFINE_RES_IRQ_NAMED(MT6328_IRQ_STATUS_HOMEKEY_R, "homekey_r"),
};
static const struct resource mt6357_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY, "homekey"),
@ -133,6 +142,18 @@ static const struct mfd_cell mt6323_devs[] = {
},
};
static const struct mfd_cell mt6328_devs[] = {
{
.name = "mt6328-regulator",
.of_compatible = "mediatek,mt6328-regulator"
}, {
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6328_keys_resources),
.resources = mt6328_keys_resources,
.of_compatible = "mediatek,mt6328-keys"
},
};
static const struct mfd_cell mt6357_devs[] = {
{
.name = "mt6359-auxadc",
@ -262,6 +283,14 @@ static const struct chip_data mt6323_core = {
.irq_init = mt6397_irq_init,
};
static const struct chip_data mt6328_core = {
.cid_addr = MT6328_HWCID,
.cid_shift = 0,
.cells = mt6328_devs,
.cell_size = ARRAY_SIZE(mt6328_devs),
.irq_init = mt6397_irq_init,
};
static const struct chip_data mt6357_core = {
.cid_addr = MT6357_SWCID,
.cid_shift = 8,
@ -360,6 +389,9 @@ static const struct of_device_id mt6397_of_match[] = {
{
.compatible = "mediatek,mt6323",
.data = &mt6323_core,
}, {
.compatible = "mediatek,mt6328",
.data = &mt6328_core,
}, {
.compatible = "mediatek,mt6331",
.data = &mt6331_mt6332_core,

23
drivers/mfd/mt6397-irq.c
View File

@ -11,6 +11,8 @@
#include <linux/suspend.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6328/core.h>
#include <linux/mfd/mt6328/registers.h>
#include <linux/mfd/mt6331/core.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6397/core.h>
@ -31,6 +33,9 @@ static void mt6397_irq_sync_unlock(struct irq_data *data)
mt6397->irq_masks_cur[0]);
regmap_write(mt6397->regmap, mt6397->int_con[1],
mt6397->irq_masks_cur[1]);
if (mt6397->int_con[2])
regmap_write(mt6397->regmap, mt6397->int_con[2],
mt6397->irq_masks_cur[2]);
mutex_unlock(&mt6397->irqlock);
}
@ -105,6 +110,8 @@ static irqreturn_t mt6397_irq_thread(int irq, void *data)
mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
if (mt6397->int_status[2])
mt6397_irq_handle_reg(mt6397, mt6397->int_status[2], 32);
return IRQ_HANDLED;
}
@ -138,6 +145,9 @@ static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
chip->int_con[0], chip->wake_mask[0]);
regmap_write(chip->regmap,
chip->int_con[1], chip->wake_mask[1]);
if (chip->int_con[2])
regmap_write(chip->regmap,
chip->int_con[2], chip->wake_mask[2]);
enable_irq_wake(chip->irq);
break;
@ -146,6 +156,9 @@ static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
chip->int_con[0], chip->irq_masks_cur[0]);
regmap_write(chip->regmap,
chip->int_con[1], chip->irq_masks_cur[1]);
if (chip->int_con[2])
regmap_write(chip->regmap,
chip->int_con[2], chip->irq_masks_cur[2]);
disable_irq_wake(chip->irq);
break;
@ -169,6 +182,14 @@ int mt6397_irq_init(struct mt6397_chip *chip)
chip->int_status[0] = MT6323_INT_STATUS0;
chip->int_status[1] = MT6323_INT_STATUS1;
break;
case MT6328_CHIP_ID:
chip->int_con[0] = MT6328_INT_CON0;
chip->int_con[1] = MT6328_INT_CON1;
chip->int_con[2] = MT6328_INT_CON2;
chip->int_status[0] = MT6328_INT_STATUS0;
chip->int_status[1] = MT6328_INT_STATUS1;
chip->int_status[2] = MT6328_INT_STATUS2;
break;
case MT6331_CHIP_ID:
chip->int_con[0] = MT6331_INT_CON0;
chip->int_con[1] = MT6331_INT_CON1;
@ -191,6 +212,8 @@ int mt6397_irq_init(struct mt6397_chip *chip)
/* Mask all interrupt sources */
regmap_write(chip->regmap, chip->int_con[0], 0x0);
regmap_write(chip->regmap, chip->int_con[1], 0x0);
if (chip->int_con[2])
regmap_write(chip->regmap, chip->int_con[2], 0x0);
chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,

2
drivers/mfd/mxs-lradc.c
View File

@ -243,7 +243,7 @@ static struct platform_driver mxs_lradc_driver = {
.of_match_table = mxs_lradc_dt_ids,
},
.probe = mxs_lradc_probe,
.remove_new = mxs_lradc_remove,
.remove = mxs_lradc_remove,
};
module_platform_driver(mxs_lradc_driver);

2
drivers/mfd/omap-usb-host.c
View File

@ -843,7 +843,7 @@ static struct platform_driver usbhs_omap_driver = {
.of_match_table = usbhs_omap_dt_ids,
},
.probe = usbhs_omap_probe,
.remove_new = usbhs_omap_remove,
.remove = usbhs_omap_remove,
};
MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");

2
drivers/mfd/omap-usb-tll.c
View File

@ -301,7 +301,7 @@ static struct platform_driver usbtll_omap_driver = {
.of_match_table = usbtll_omap_dt_ids,
},
.probe = usbtll_omap_probe,
.remove_new = usbtll_omap_remove,
.remove = usbtll_omap_remove,
};
int omap_tll_init(struct usbhs_omap_platform_data *pdata)

2
drivers/mfd/pcf50633-adc.c
View File

@ -243,7 +243,7 @@ static struct platform_driver pcf50633_adc_driver = {
.name = "pcf50633-adc",
},
.probe = pcf50633_adc_probe,
.remove_new = pcf50633_adc_remove,
.remove = pcf50633_adc_remove,
};
module_platform_driver(pcf50633_adc_driver);

2
drivers/mfd/qcom-pm8xxx.c
View File

@ -595,7 +595,7 @@ static void pm8xxx_remove(struct platform_device *pdev)
static struct platform_driver pm8xxx_driver = {
.probe = pm8xxx_probe,
.remove_new = pm8xxx_remove,
.remove = pm8xxx_remove,
.driver = {
.name = "pm8xxx-core",
.of_match_table = pm8xxx_id_table,

6
drivers/mfd/rk8xx-core.c
View File

@ -618,7 +618,7 @@ static int rk808_power_off(struct sys_off_data *data)
bit = DEV_OFF;
break;
case RK808_ID:
reg = RK808_DEVCTRL_REG,
reg = RK808_DEVCTRL_REG;
bit = DEV_OFF_RST;
break;
case RK809_ID:
@ -785,8 +785,8 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap
if (ret)
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
if (device_property_read_bool(dev, "rockchip,system-power-controller") ||
device_property_read_bool(dev, "system-power-controller")) {
if (device_property_read_bool(dev, "system-power-controller") ||
device_property_read_bool(dev, "rockchip,system-power-controller")) {
ret = devm_register_sys_off_handler(dev,
SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
&rk808_power_off, rk808);

12
drivers/mfd/rohm-bd71828.c
View File

@ -32,15 +32,15 @@ static struct gpio_keys_platform_data bd71828_powerkey_data = {
};
static const struct resource bd71815_rtc_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd71815-rtc-alm-0"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd71815-rtc-alm-1"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd71815-rtc-alm-2"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"),
};
static const struct resource bd71828_rtc_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd71828-rtc-alm-0"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd71828-rtc-alm-1"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd71828-rtc-alm-2"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"),
};
static struct resource bd71815_power_irqs[] = {

277
drivers/mfd/rohm-bd96801.c
View File

@ -5,13 +5,9 @@
* ROHM BD96801 PMIC driver
*
* This version of the "BD86801 scalable PMIC"'s driver supports only very
* basic set of the PMIC features. Most notably, there is no support for
* the ERRB interrupt and the configurations which should be done when the
* PMIC is in STBY mode.
*
* Supporting the ERRB interrupt would require dropping the regmap-IRQ
* usage or working around (or accepting a presense of) a naming conflict
* in debugFS IRQs.
* basic set of the PMIC features.
* Most notably, there is no support for the configurations which should
* be done when the PMIC is in STBY mode.
*
* Being able to reliably do the configurations like changing the
* regulator safety limits (like limits for the over/under -voltages, over
@ -23,16 +19,14 @@
* be the need to configure these safety limits. Hence it's not simple to
* come up with a generic solution.
*
* Users who require the ERRB handling and STBY state configurations can
* have a look at the original RFC:
* Users who require the STBY state configurations can have a look at the
* original RFC:
* https://lore.kernel.org/all/cover.1712920132.git.mazziesaccount@gmail.com/
* which implements a workaround to debugFS naming conflict and some of
* the safety limit configurations - but leaves the state change handling
* and synchronization to be implemented.
* which implements some of the safety limit configurations - but leaves the
* state change handling and synchronization to be implemented.
*
* It would be great to hear (and receive a patch!) if you implement the
* STBY configuration support or a proper fix to the debugFS naming
* conflict in your downstream driver ;)
* STBY configuration support or a proper fix in your downstream driver ;)
*/
#include <linux/i2c.h>
@ -46,6 +40,64 @@
#include <linux/mfd/rohm-bd96801.h>
#include <linux/mfd/rohm-generic.h>
static const struct resource regulator_errb_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "bd96801-otp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "bd96801-dbist-err"),
DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "bd96801-eep-err"),
DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "bd96801-abist-err"),
DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "bd96801-prstb-err"),
DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "bd96801-drmoserr1"),
DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "bd96801-drmoserr2"),
DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "bd96801-slave-err"),
DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "bd96801-vref-err"),
DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "bd96801-tsd"),
DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "bd96801-uvlo-err"),
DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "bd96801-ovlo-err"),
DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "bd96801-osc-err"),
DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "bd96801-pon-err"),
DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "bd96801-poff-err"),
DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "bd96801-cmd-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_INT_PRSTB_WDT_ERR, "bd96801-prstb-wdt-err"),
DEFINE_RES_IRQ_NAMED(BD96801_INT_CHIP_IF_ERR, "bd96801-chip-if-err"),
DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "bd96801-int-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "bd96801-buck1-pvin-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "bd96801-buck1-ovp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "bd96801-buck1-uvp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "bd96801-buck1-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "bd96801-buck2-pvin-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "bd96801-buck2-ovp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "bd96801-buck2-uvp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "bd96801-buck2-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "bd96801-buck3-pvin-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "bd96801-buck3-ovp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "bd96801-buck3-uvp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "bd96801-buck3-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "bd96801-buck4-pvin-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "bd96801-buck4-ovp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "bd96801-buck4-uvp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "bd96801-buck4-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "bd96801-ldo5-pvin-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "bd96801-ldo5-ovp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "bd96801-ldo5-uvp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "bd96801-ldo5-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "bd96801-ldo6-pvin-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "bd96801-ldo6-ovp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "bd96801-ldo6-uvp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "bd96801-ldo6-shdn-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "bd96801-ldo7-pvin-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "bd96801-ldo7-ovp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "bd96801-ldo7-uvp-err"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "bd96801-ldo7-shdn-err"),
};
static const struct resource regulator_intb_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"),
@ -90,20 +142,14 @@ static const struct resource regulator_intb_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"),
};
static const struct resource wdg_intb_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD96801_WDT_ERR_STAT, "bd96801-wdg"),
enum {
WDG_CELL = 0,
REGULATOR_CELL,
};
static struct mfd_cell bd96801_cells[] = {
{
.name = "bd96801-wdt",
.resources = wdg_intb_irqs,
.num_resources = ARRAY_SIZE(wdg_intb_irqs),
}, {
.name = "bd96801-regulator",
.resources = regulator_intb_irqs,
.num_resources = ARRAY_SIZE(regulator_intb_irqs),
},
[WDG_CELL] = { .name = "bd96801-wdt", },
[REGULATOR_CELL] = { .name = "bd96801-regulator", },
};
static const struct regmap_range bd96801_volatile_ranges[] = {
@ -128,6 +174,91 @@ static const struct regmap_access_table volatile_regs = {
.n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges),
};
/*
* For ERRB we need main register bit mapping as bit(0) indicates active IRQ
* in one of the first 3 sub IRQ registers, For INTB we can use default 1 to 1
* mapping.
*/
static unsigned int bit0_offsets[] = {0, 1, 2}; /* System stat, 3 registers */
static unsigned int bit1_offsets[] = {3}; /* Buck 1 stat */
static unsigned int bit2_offsets[] = {4}; /* Buck 2 stat */
static unsigned int bit3_offsets[] = {5}; /* Buck 3 stat */
static unsigned int bit4_offsets[] = {6}; /* Buck 4 stat */
static unsigned int bit5_offsets[] = {7}; /* LDO 5 stat */
static unsigned int bit6_offsets[] = {8}; /* LDO 6 stat */
static unsigned int bit7_offsets[] = {9}; /* LDO 7 stat */
static const struct regmap_irq_sub_irq_map errb_sub_irq_offsets[] = {
REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
};
static const struct regmap_irq bd96801_errb_irqs[] = {
/* Reg 0x52 Fatal ERRB1 */
REGMAP_IRQ_REG(BD96801_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_DBIST_ERR_STAT, 0, BD96801_DBIST_ERR_MASK),
REGMAP_IRQ_REG(BD96801_EEP_ERR_STAT, 0, BD96801_EEP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_ABIST_ERR_STAT, 0, BD96801_ABIST_ERR_MASK),
REGMAP_IRQ_REG(BD96801_PRSTB_ERR_STAT, 0, BD96801_PRSTB_ERR_MASK),
REGMAP_IRQ_REG(BD96801_DRMOS1_ERR_STAT, 0, BD96801_DRMOS1_ERR_MASK),
REGMAP_IRQ_REG(BD96801_DRMOS2_ERR_STAT, 0, BD96801_DRMOS2_ERR_MASK),
REGMAP_IRQ_REG(BD96801_SLAVE_ERR_STAT, 0, BD96801_SLAVE_ERR_MASK),
/* 0x53 Fatal ERRB2 */
REGMAP_IRQ_REG(BD96801_VREF_ERR_STAT, 1, BD96801_VREF_ERR_MASK),
REGMAP_IRQ_REG(BD96801_TSD_ERR_STAT, 1, BD96801_TSD_ERR_MASK),
REGMAP_IRQ_REG(BD96801_UVLO_ERR_STAT, 1, BD96801_UVLO_ERR_MASK),
REGMAP_IRQ_REG(BD96801_OVLO_ERR_STAT, 1, BD96801_OVLO_ERR_MASK),
REGMAP_IRQ_REG(BD96801_OSC_ERR_STAT, 1, BD96801_OSC_ERR_MASK),
REGMAP_IRQ_REG(BD96801_PON_ERR_STAT, 1, BD96801_PON_ERR_MASK),
REGMAP_IRQ_REG(BD96801_POFF_ERR_STAT, 1, BD96801_POFF_ERR_MASK),
REGMAP_IRQ_REG(BD96801_CMD_SHDN_ERR_STAT, 1, BD96801_CMD_SHDN_ERR_MASK),
/* 0x54 Fatal INTB shadowed to ERRB */
REGMAP_IRQ_REG(BD96801_INT_PRSTB_WDT_ERR, 2, BD96801_INT_PRSTB_WDT_ERR_MASK),
REGMAP_IRQ_REG(BD96801_INT_CHIP_IF_ERR, 2, BD96801_INT_CHIP_IF_ERR_MASK),
REGMAP_IRQ_REG(BD96801_INT_SHDN_ERR_STAT, 2, BD96801_INT_SHDN_ERR_MASK),
/* Reg 0x55 BUCK1 ERR IRQs */
REGMAP_IRQ_REG(BD96801_BUCK1_PVIN_ERR_STAT, 3, BD96801_OUT_PVIN_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_OVP_ERR_STAT, 3, BD96801_OUT_OVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_UVP_ERR_STAT, 3, BD96801_OUT_UVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_SHDN_ERR_STAT, 3, BD96801_OUT_SHDN_ERR_MASK),
/* Reg 0x56 BUCK2 ERR IRQs */
REGMAP_IRQ_REG(BD96801_BUCK2_PVIN_ERR_STAT, 4, BD96801_OUT_PVIN_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_OVP_ERR_STAT, 4, BD96801_OUT_OVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_UVP_ERR_STAT, 4, BD96801_OUT_UVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_SHDN_ERR_STAT, 4, BD96801_OUT_SHDN_ERR_MASK),
/* Reg 0x57 BUCK3 ERR IRQs */
REGMAP_IRQ_REG(BD96801_BUCK3_PVIN_ERR_STAT, 5, BD96801_OUT_PVIN_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_OVP_ERR_STAT, 5, BD96801_OUT_OVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_UVP_ERR_STAT, 5, BD96801_OUT_UVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_SHDN_ERR_STAT, 5, BD96801_OUT_SHDN_ERR_MASK),
/* Reg 0x58 BUCK4 ERR IRQs */
REGMAP_IRQ_REG(BD96801_BUCK4_PVIN_ERR_STAT, 6, BD96801_OUT_PVIN_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_OVP_ERR_STAT, 6, BD96801_OUT_OVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_UVP_ERR_STAT, 6, BD96801_OUT_UVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_SHDN_ERR_STAT, 6, BD96801_OUT_SHDN_ERR_MASK),
/* Reg 0x59 LDO5 ERR IRQs */
REGMAP_IRQ_REG(BD96801_LDO5_PVIN_ERR_STAT, 7, BD96801_OUT_PVIN_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO5_OVP_ERR_STAT, 7, BD96801_OUT_OVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO5_UVP_ERR_STAT, 7, BD96801_OUT_UVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO5_SHDN_ERR_STAT, 7, BD96801_OUT_SHDN_ERR_MASK),
/* Reg 0x5a LDO6 ERR IRQs */
REGMAP_IRQ_REG(BD96801_LDO6_PVIN_ERR_STAT, 8, BD96801_OUT_PVIN_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO6_OVP_ERR_STAT, 8, BD96801_OUT_OVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO6_UVP_ERR_STAT, 8, BD96801_OUT_UVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO6_SHDN_ERR_STAT, 8, BD96801_OUT_SHDN_ERR_MASK),
/* Reg 0x5b LDO7 ERR IRQs */
REGMAP_IRQ_REG(BD96801_LDO7_PVIN_ERR_STAT, 9, BD96801_OUT_PVIN_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO7_OVP_ERR_STAT, 9, BD96801_OUT_OVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO7_UVP_ERR_STAT, 9, BD96801_OUT_UVP_ERR_MASK),
REGMAP_IRQ_REG(BD96801_LDO7_SHDN_ERR_STAT, 9, BD96801_OUT_SHDN_ERR_MASK),
};
static const struct regmap_irq bd96801_intb_irqs[] = {
/* STATUS SYSTEM INTB */
REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK),
@ -176,8 +307,25 @@ static const struct regmap_irq bd96801_intb_irqs[] = {
REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK),
};
static struct regmap_irq_chip bd96801_irq_chip_intb = {
static const struct regmap_irq_chip bd96801_irq_chip_errb = {
.name = "bd96801-irq-errb",
.domain_suffix = "errb",
.main_status = BD96801_REG_INT_MAIN,
.num_main_regs = 1,
.irqs = &bd96801_errb_irqs[0],
.num_irqs = ARRAY_SIZE(bd96801_errb_irqs),
.status_base = BD96801_REG_INT_SYS_ERRB1,
.mask_base = BD96801_REG_MASK_SYS_ERRB,
.ack_base = BD96801_REG_INT_SYS_ERRB1,
.init_ack_masked = true,
.num_regs = 10,
.irq_reg_stride = 1,
.sub_reg_offsets = &errb_sub_irq_offsets[0],
};
static const struct regmap_irq_chip bd96801_irq_chip_intb = {
.name = "bd96801-irq-intb",
.domain_suffix = "intb",
.main_status = BD96801_REG_INT_MAIN,
.num_main_regs = 1,
.irqs = &bd96801_intb_irqs[0],
@ -194,16 +342,20 @@ static const struct regmap_config bd96801_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &volatile_regs,
.cache_type = REGCACHE_RBTREE,
.cache_type = REGCACHE_MAPLE,
};
static int bd96801_i2c_probe(struct i2c_client *i2c)
{
struct regmap_irq_chip_data *intb_irq_data;
struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data;
struct irq_domain *intb_domain, *errb_domain;
const struct fwnode_handle *fwnode;
struct irq_domain *intb_domain;
struct resource *regulator_res;
struct resource wdg_irq;
struct regmap *regmap;
int ret, intb_irq;
int intb_irq, errb_irq, num_intb, num_errb = 0;
int num_regu_irqs, wdg_irq_no;
int i, ret;
fwnode = dev_fwnode(&i2c->dev);
if (!fwnode)
@ -213,6 +365,23 @@ static int bd96801_i2c_probe(struct i2c_client *i2c)
if (intb_irq < 0)
return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n");
num_intb = ARRAY_SIZE(regulator_intb_irqs);
/* ERRB may be omitted if processor is powered by the PMIC */
errb_irq = fwnode_irq_get_byname(fwnode, "errb");
if (errb_irq < 0)
errb_irq = 0;
if (errb_irq)
num_errb = ARRAY_SIZE(regulator_errb_irqs);
num_regu_irqs = num_intb + num_errb;
regulator_res = devm_kcalloc(&i2c->dev, num_regu_irqs,
sizeof(*regulator_res), GFP_KERNEL);
if (!regulator_res)
return -ENOMEM;
regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
@ -230,12 +399,50 @@ static int bd96801_i2c_probe(struct i2c_client *i2c)
intb_domain = regmap_irq_get_domain(intb_irq_data);
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
bd96801_cells,
ARRAY_SIZE(bd96801_cells), NULL, 0,
intb_domain);
/*
* MFD core code is built to handle only one IRQ domain. BD96801
* has two domains so we do IRQ mapping here and provide the
* already mapped IRQ numbers to sub-devices.
*/
for (i = 0; i < num_intb; i++) {
struct resource *res = &regulator_res[i];
*res = regulator_intb_irqs[i];
res->start = res->end = irq_create_mapping(intb_domain,
res->start);
}
wdg_irq_no = irq_create_mapping(intb_domain, BD96801_WDT_ERR_STAT);
wdg_irq = DEFINE_RES_IRQ_NAMED(wdg_irq_no, "bd96801-wdg");
bd96801_cells[WDG_CELL].resources = &wdg_irq;
bd96801_cells[WDG_CELL].num_resources = 1;
if (!num_errb)
goto skip_errb;
ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, errb_irq, IRQF_ONESHOT,
0, &bd96801_irq_chip_errb, &errb_irq_data);
if (ret)
dev_err(&i2c->dev, "Failed to create subdevices\n");
return dev_err_probe(&i2c->dev, ret,
"Failed to add ERRB IRQ chip\n");
errb_domain = regmap_irq_get_domain(errb_irq_data);
for (i = 0; i < num_errb; i++) {
struct resource *res = &regulator_res[num_intb + i];
*res = regulator_errb_irqs[i];
res->start = res->end = irq_create_mapping(errb_domain, res->start);
}
skip_errb:
bd96801_cells[REGULATOR_CELL].resources = regulator_res;
bd96801_cells[REGULATOR_CELL].num_resources = num_regu_irqs;
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, bd96801_cells,
ARRAY_SIZE(bd96801_cells), NULL, 0, NULL);
if (ret)
dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
return ret;
}

4
drivers/mfd/rt5033.c
View File

@ -81,8 +81,8 @@ static int rt5033_i2c_probe(struct i2c_client *i2c)
chip_rev = dev_id & RT5033_CHIP_REV_MASK;
dev_info(&i2c->dev, "Device found (rev. %d)\n", chip_rev);
ret = regmap_add_irq_chip(rt5033->regmap, rt5033->irq,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
ret = devm_regmap_add_irq_chip(rt5033->dev, rt5033->regmap,
rt5033->irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0, &rt5033_irq_chip, &rt5033->irq_data);
if (ret) {
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",

11
drivers/mfd/sec-core.c
View File

@ -34,6 +34,10 @@ static const struct mfd_cell s5m8767_devs[] = {
},
};
static const struct mfd_cell s2dos05_devs[] = {
{ .name = "s2dos05-regulator", },
};
static const struct mfd_cell s2mps11_devs[] = {
{ .name = "s2mps11-regulator", },
{ .name = "s2mps14-rtc", },
@ -83,6 +87,9 @@ static const struct of_device_id sec_dt_match[] = {
{
.compatible = "samsung,s5m8767-pmic",
.data = (void *)S5M8767X,
}, {
.compatible = "samsung,s2dos05",
.data = (void *)S2DOS05,
}, {
.compatible = "samsung,s2mps11-pmic",
.data = (void *)S2MPS11X,
@ -339,6 +346,10 @@ static int sec_pmic_probe(struct i2c_client *i2c)
sec_devs = s5m8767_devs;
num_sec_devs = ARRAY_SIZE(s5m8767_devs);
break;
case S2DOS05:
sec_devs = s2dos05_devs;
num_sec_devs = ARRAY_SIZE(s2dos05_devs);
break;
case S2MPA01:
sec_devs = s2mpa01_devs;
num_sec_devs = ARRAY_SIZE(s2mpa01_devs);

2
drivers/mfd/sm501.c
View File

@ -1705,7 +1705,7 @@ static struct platform_driver sm501_plat_driver = {
.of_match_table = of_sm501_match_tbl,
},
.probe = sm501_plat_probe,
.remove_new = sm501_plat_remove,
.remove = sm501_plat_remove,
.suspend = pm_sleep_ptr(sm501_plat_suspend),
.resume = pm_sleep_ptr(sm501_plat_resume),
};

2
drivers/mfd/stm32-timers.c
View File

@ -326,7 +326,7 @@ MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
static struct platform_driver stm32_timers_driver = {
.probe = stm32_timers_probe,
.remove_new = stm32_timers_remove,
.remove = stm32_timers_remove,
.driver = {
.name = "stm32-timers",
.of_match_table = stm32_timers_of_match,

5
drivers/mfd/syscon.c
View File

@ -108,6 +108,8 @@ static struct syscon *of_syscon_register(struct device_node *np, bool check_res)
syscon_config.reg_stride = reg_io_width;
syscon_config.val_bits = reg_io_width * 8;
syscon_config.max_register = resource_size(&res) - reg_io_width;
if (!syscon_config.max_register)
syscon_config.max_register_is_0 = true;
regmap = regmap_init_mmio(NULL, base, &syscon_config);
kfree(syscon_config.name);
@ -357,6 +359,9 @@ static int syscon_probe(struct platform_device *pdev)
return -ENOMEM;
syscon_config.max_register = resource_size(res) - 4;
if (!syscon_config.max_register)
syscon_config.max_register_is_0 = true;
if (pdata)
syscon_config.name = pdata->label;
syscon->regmap = devm_regmap_init_mmio(dev, base, &syscon_config);

2
drivers/mfd/ti_am335x_tscadc.c
View File

@ -377,7 +377,7 @@ static struct platform_driver ti_tscadc_driver = {
.of_match_table = ti_tscadc_dt_ids,
},
.probe = ti_tscadc_probe,
.remove_new = ti_tscadc_remove,
.remove = ti_tscadc_remove,
};

8
drivers/mfd/tps65010.c
View File

@ -544,17 +544,13 @@ static int tps65010_probe(struct i2c_client *client)
*/
if (client->irq > 0) {
status = request_irq(client->irq, tps65010_irq,
IRQF_TRIGGER_FALLING, DRIVER_NAME, tps);
IRQF_TRIGGER_FALLING | IRQF_NO_AUTOEN,
DRIVER_NAME, tps);
if (status < 0) {
dev_dbg(&client->dev, "can't get IRQ %d, err %d\n",
client->irq, status);
return status;
}
/* annoying race here, ideally we'd have an option
* to claim the irq now and enable it later.
* FIXME genirq IRQF_NOAUTOEN now solves that ...
*/
disable_irq(client->irq);
set_bit(FLAG_IRQ_ENABLE, &tps->flags);
} else
dev_warn(&client->dev, "IRQ not configured!\n");

2
drivers/mfd/tps65911-comparator.c
View File

@ -154,7 +154,7 @@ static struct platform_driver tps65911_comparator_driver = {
.name = "tps65911-comparator",
},
.probe = tps65911_comparator_probe,
.remove_new = tps65911_comparator_remove,
.remove = tps65911_comparator_remove,
};
static int __init tps65911_comparator_init(void)

129
drivers/mfd/tqmx86.c
View File

@ -35,11 +35,14 @@
#define TQMX86_REG_BOARD_ID_E39C2 7
#define TQMX86_REG_BOARD_ID_70EB 8
#define TQMX86_REG_BOARD_ID_80UC 9
#define TQMX86_REG_BOARD_ID_120UC 10
#define TQMX86_REG_BOARD_ID_110EB 11
#define TQMX86_REG_BOARD_ID_E40M 12
#define TQMX86_REG_BOARD_ID_E40S 13
#define TQMX86_REG_BOARD_ID_E40C1 14
#define TQMX86_REG_BOARD_ID_E40C2 15
#define TQMX86_REG_BOARD_ID_130UC 16
#define TQMX86_REG_BOARD_ID_E41S 19
#define TQMX86_REG_BOARD_REV 0x01
#define TQMX86_REG_IO_EXT_INT 0x06
#define TQMX86_REG_IO_EXT_INT_NONE 0
@ -47,6 +50,7 @@
#define TQMX86_REG_IO_EXT_INT_9 2
#define TQMX86_REG_IO_EXT_INT_12 3
#define TQMX86_REG_IO_EXT_INT_MASK 0x3
#define TQMX86_REG_IO_EXT_INT_I2C1_SHIFT 0
#define TQMX86_REG_IO_EXT_INT_GPIO_SHIFT 4
#define TQMX86_REG_SAUC 0x17
@ -55,23 +59,36 @@
static uint gpio_irq;
module_param(gpio_irq, uint, 0);
MODULE_PARM_DESC(gpio_irq, "GPIO IRQ number (7, 9, 12)");
MODULE_PARM_DESC(gpio_irq, "GPIO IRQ number (valid parameters: 7, 9, 12)");
static const struct resource tqmx_i2c_soft_resources[] = {
DEFINE_RES_IO(TQMX86_IOBASE_I2C, TQMX86_IOSIZE_I2C),
static uint i2c1_irq;
module_param(i2c1_irq, uint, 0);
MODULE_PARM_DESC(i2c1_irq, "I2C1 IRQ number (valid parameters: 7, 9, 12)");
enum tqmx86_i2c1_resource_type {
TQMX86_I2C1_IO,
TQMX86_I2C1_IRQ,
};
static struct resource tqmx_i2c_soft_resources[] = {
[TQMX86_I2C1_IO] = DEFINE_RES_IO(TQMX86_IOBASE_I2C, TQMX86_IOSIZE_I2C),
/* Placeholder for IRQ resource */
[TQMX86_I2C1_IRQ] = {},
};
static const struct resource tqmx_watchdog_resources[] = {
DEFINE_RES_IO(TQMX86_IOBASE_WATCHDOG, TQMX86_IOSIZE_WATCHDOG),
};
/*
* The IRQ resource must be first, since it is updated with the
* configured IRQ in the probe function.
*/
enum tqmx86_gpio_resource_type {
TQMX86_GPIO_IO,
TQMX86_GPIO_IRQ,
};
static struct resource tqmx_gpio_resources[] = {
DEFINE_RES_IRQ(0),
DEFINE_RES_IO(TQMX86_IOBASE_GPIO, TQMX86_IOSIZE_GPIO),
[TQMX86_GPIO_IO] = DEFINE_RES_IO(TQMX86_IOBASE_GPIO, TQMX86_IOSIZE_GPIO),
/* Placeholder for IRQ resource */
[TQMX86_GPIO_IRQ] = {},
};
static struct i2c_board_info tqmx86_i2c_devices[] = {
@ -132,6 +149,8 @@ static const char *tqmx86_board_id_to_name(u8 board_id, u8 sauc)
return "TQMx70EB";
case TQMX86_REG_BOARD_ID_80UC:
return "TQMx80UC";
case TQMX86_REG_BOARD_ID_120UC:
return "TQMx120UC";
case TQMX86_REG_BOARD_ID_110EB:
return "TQMx110EB";
case TQMX86_REG_BOARD_ID_E40M:
@ -142,6 +161,10 @@ static const char *tqmx86_board_id_to_name(u8 board_id, u8 sauc)
return "TQMxE40C1";
case TQMX86_REG_BOARD_ID_E40C2:
return "TQMxE40C2";
case TQMX86_REG_BOARD_ID_130UC:
return "TQMx130UC";
case TQMX86_REG_BOARD_ID_E41S:
return "TQMxE41S";
default:
return "Unknown";
}
@ -154,11 +177,14 @@ static int tqmx86_board_id_to_clk_rate(struct device *dev, u8 board_id)
case TQMX86_REG_BOARD_ID_60EB:
case TQMX86_REG_BOARD_ID_70EB:
case TQMX86_REG_BOARD_ID_80UC:
case TQMX86_REG_BOARD_ID_120UC:
case TQMX86_REG_BOARD_ID_110EB:
case TQMX86_REG_BOARD_ID_E40M:
case TQMX86_REG_BOARD_ID_E40S:
case TQMX86_REG_BOARD_ID_E40C1:
case TQMX86_REG_BOARD_ID_E40C2:
case TQMX86_REG_BOARD_ID_130UC:
case TQMX86_REG_BOARD_ID_E41S:
return 24000;
case TQMX86_REG_BOARD_ID_E39MS:
case TQMX86_REG_BOARD_ID_E39C1:
@ -174,33 +200,52 @@ static int tqmx86_board_id_to_clk_rate(struct device *dev, u8 board_id)
}
}
static int tqmx86_setup_irq(struct device *dev, const char *label, u8 irq,
void __iomem *io_base, u8 reg_shift)
{
u8 val, readback;
int irq_cfg;
switch (irq) {
case 0:
irq_cfg = TQMX86_REG_IO_EXT_INT_NONE;
break;
case 7:
irq_cfg = TQMX86_REG_IO_EXT_INT_7;
break;
case 9:
irq_cfg = TQMX86_REG_IO_EXT_INT_9;
break;
case 12:
irq_cfg = TQMX86_REG_IO_EXT_INT_12;
break;
default:
dev_err(dev, "invalid %s IRQ (%d)\n", label, irq);
return -EINVAL;
}
val = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
val &= ~(TQMX86_REG_IO_EXT_INT_MASK << reg_shift);
val |= (irq_cfg & TQMX86_REG_IO_EXT_INT_MASK) << reg_shift;
iowrite8(val, io_base + TQMX86_REG_IO_EXT_INT);
readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
if (readback != val) {
dev_warn(dev, "%s interrupts not supported\n", label);
return -EINVAL;
}
return 0;
}
static int tqmx86_probe(struct platform_device *pdev)
{
u8 board_id, sauc, rev, i2c_det, io_ext_int_val;
u8 board_id, sauc, rev, i2c_det;
struct device *dev = &pdev->dev;
u8 gpio_irq_cfg, readback;
const char *board_name;
void __iomem *io_base;
int err;
switch (gpio_irq) {
case 0:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_NONE;
break;
case 7:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_7;
break;
case 9:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_9;
break;
case 12:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_12;
break;
default:
pr_err("tqmx86: Invalid GPIO IRQ (%d)\n", gpio_irq);
return -EINVAL;
}
io_base = devm_ioport_map(dev, TQMX86_IOBASE, TQMX86_IOSIZE);
if (!io_base)
return -ENOMEM;
@ -221,25 +266,23 @@ static int tqmx86_probe(struct platform_device *pdev)
*/
i2c_det = inb(TQMX86_REG_I2C_DETECT);
if (gpio_irq_cfg) {
io_ext_int_val =
gpio_irq_cfg << TQMX86_REG_IO_EXT_INT_GPIO_SHIFT;
iowrite8(io_ext_int_val, io_base + TQMX86_REG_IO_EXT_INT);
readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
if (readback != io_ext_int_val) {
dev_warn(dev, "GPIO interrupts not supported.\n");
return -EINVAL;
}
/* Assumes the IRQ resource is first. */
tqmx_gpio_resources[0].start = gpio_irq;
} else {
tqmx_gpio_resources[0].flags = 0;
if (gpio_irq) {
err = tqmx86_setup_irq(dev, "GPIO", gpio_irq, io_base,
TQMX86_REG_IO_EXT_INT_GPIO_SHIFT);
if (!err)
tqmx_gpio_resources[TQMX86_GPIO_IRQ] = DEFINE_RES_IRQ(gpio_irq);
}
ocores_platform_data.clock_khz = tqmx86_board_id_to_clk_rate(dev, board_id);
if (i2c_det == TQMX86_REG_I2C_DETECT_SOFT) {
if (i2c1_irq) {
err = tqmx86_setup_irq(dev, "I2C1", i2c1_irq, io_base,
TQMX86_REG_IO_EXT_INT_I2C1_SHIFT);
if (!err)
tqmx_i2c_soft_resources[TQMX86_I2C1_IRQ] = DEFINE_RES_IRQ(i2c1_irq);
}
err = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
tqmx86_i2c_soft_dev,
ARRAY_SIZE(tqmx86_i2c_soft_dev),

26
drivers/mfd/twl-core.c
View File

@ -711,6 +711,10 @@ static struct of_dev_auxdata twl_auxdata_lookup[] = {
{ /* sentinel */ },
};
static const struct mfd_cell twl6030_cells[] = {
{ .name = "twl6030-clk" },
};
static const struct mfd_cell twl6032_cells[] = {
{ .name = "twl6032-clk" },
};
@ -861,17 +865,23 @@ twl_probe(struct i2c_client *client)
TWL4030_DCDC_GLOBAL_CFG);
}
if (id->driver_data == (TWL6030_CLASS | TWL6032_SUBCLASS)) {
status = devm_mfd_add_devices(&client->dev,
PLATFORM_DEVID_NONE,
twl6032_cells,
ARRAY_SIZE(twl6032_cells),
NULL, 0, NULL);
if (twl_class_is_6030()) {
const struct mfd_cell *cells;
int num_cells;
if (id->driver_data & TWL6032_SUBCLASS) {
cells = twl6032_cells;
num_cells = ARRAY_SIZE(twl6032_cells);
} else {
cells = twl6030_cells;
num_cells = ARRAY_SIZE(twl6030_cells);
}
status = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
cells, num_cells, NULL, 0, NULL);
if (status < 0)
goto free;
}
if (twl_class_is_6030()) {
if (of_device_is_system_power_controller(node)) {
if (!pm_power_off)
pm_power_off = twl6030_power_off;

2
drivers/mfd/twl4030-audio.c
View File

@ -276,7 +276,7 @@ static struct platform_driver twl4030_audio_driver = {
.of_match_table = twl4030_audio_of_match,
},
.probe = twl4030_audio_probe,
.remove_new = twl4030_audio_remove,
.remove = twl4030_audio_remove,
};
module_platform_driver(twl4030_audio_driver);

2
drivers/mfd/wcd934x.c
View File

@ -284,6 +284,7 @@ static const struct slim_device_id wcd934x_slim_id[] = {
SLIM_DEV_IDX_WCD9340, SLIM_DEV_INSTANCE_ID_WCD9340 },
{}
};
MODULE_DEVICE_TABLE(slim, wcd934x_slim_id);
static struct slim_driver wcd934x_slim_driver = {
.driver = {
@ -298,5 +299,4 @@ static struct slim_driver wcd934x_slim_driver = {
module_slim_driver(wcd934x_slim_driver);
MODULE_DESCRIPTION("WCD934X slim driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("slim:217:250:*");
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");

22
drivers/platform/x86/intel/bxtwc_tmu.c
View File

@ -48,9 +48,8 @@ static irqreturn_t bxt_wcove_tmu_irq_handler(int irq, void *data)
static int bxt_wcove_tmu_probe(struct platform_device *pdev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
struct regmap_irq_chip_data *regmap_irq_chip;
struct wcove_tmu *wctmu;
int ret, virq, irq;
int ret;
wctmu = devm_kzalloc(&pdev->dev, sizeof(*wctmu), GFP_KERNEL);
if (!wctmu)
@ -59,27 +58,18 @@ static int bxt_wcove_tmu_probe(struct platform_device *pdev)
wctmu->dev = &pdev->dev;
wctmu->regmap = pmic->regmap;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
wctmu->irq = platform_get_irq(pdev, 0);
if (wctmu->irq < 0)
return wctmu->irq;
regmap_irq_chip = pmic->irq_chip_data_tmu;
virq = regmap_irq_get_virq(regmap_irq_chip, irq);
if (virq < 0) {
dev_err(&pdev->dev,
"failed to get virtual interrupt=%d\n", irq);
return virq;
}
ret = devm_request_threaded_irq(&pdev->dev, virq,
ret = devm_request_threaded_irq(&pdev->dev, wctmu->irq,
NULL, bxt_wcove_tmu_irq_handler,
IRQF_ONESHOT, "bxt_wcove_tmu", wctmu);
if (ret) {
dev_err(&pdev->dev, "request irq failed: %d,virq: %d\n",
ret, virq);
ret, wctmu->irq);
return ret;
}
wctmu->irq = virq;
/* Unmask TMU second level Wake & System alarm */
regmap_update_bits(wctmu->regmap, BXTWC_MTMUIRQ_REG,

13
drivers/regulator/axp20x-regulator.c
View File

@ -1341,6 +1341,7 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
step = 150;
break;
case AXP313A_ID:
case AXP323_ID:
case AXP717_ID:
case AXP15060_ID:
/* The DCDC PWM frequency seems to be fixed to 3 MHz. */
@ -1527,6 +1528,15 @@ static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
}
break;
case AXP323_ID:
regmap_read(axp20x->regmap, AXP323_DCDC_MODE_CTRL2, &reg);
switch (id) {
case AXP313A_DCDC2:
return !!(reg & BIT(1));
}
break;
default:
return false;
}
@ -1565,6 +1575,7 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
"x-powers,drive-vbus-en");
break;
case AXP313A_ID:
case AXP323_ID:
regulators = axp313a_regulators;
nregulators = AXP313A_REG_ID_MAX;
break;
@ -1597,7 +1608,7 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
nregulators = AXP15060_REG_ID_MAX;
break;
default:
dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
dev_err(&pdev->dev, "Unsupported AXP variant: %d\n",
axp20x->variant);
return -EINVAL;
}

5
drivers/rtc/rtc-bd70528.c
View File

@ -236,7 +236,6 @@ static int bd70528_probe(struct platform_device *pdev)
{
struct bd70528_rtc *bd_rtc;
const struct rtc_class_ops *rtc_ops;
const char *irq_name;
int ret;
struct rtc_device *rtc;
int irq;
@ -259,7 +258,6 @@ static int bd70528_probe(struct platform_device *pdev)
switch (chip) {
case ROHM_CHIP_TYPE_BD71815:
irq_name = "bd71815-rtc-alm-0";
bd_rtc->reg_time_start = BD71815_REG_RTC_START;
/*
@ -276,7 +274,6 @@ static int bd70528_probe(struct platform_device *pdev)
hour_reg = BD71815_REG_HOUR;
break;
case ROHM_CHIP_TYPE_BD71828:
irq_name = "bd71828-rtc-alm-0";
bd_rtc->reg_time_start = BD71828_REG_RTC_START;
bd_rtc->bd718xx_alm_block_start = BD71828_REG_RTC_ALM_START;
hour_reg = BD71828_REG_RTC_HOUR;
@ -286,7 +283,7 @@ static int bd70528_probe(struct platform_device *pdev)
return -ENOENT;
}
irq = platform_get_irq_byname(pdev, irq_name);
irq = platform_get_irq_byname(pdev, "bd70528-rtc-alm-0");
if (irq < 0)
return irq;

4
drivers/usb/typec/tcpm/wcove.c
View File

@ -621,10 +621,6 @@ static int wcove_typec_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
irq = regmap_irq_get_virq(pmic->irq_chip_data_chgr, irq);
if (irq < 0)
return irq;
ret = guid_parse(WCOVE_DSM_UUID, &wcove->guid);
if (ret)
return ret;

163
include/dt-bindings/clock/aspeed,ast2700-scu.h Normal file
View File

@ -0,0 +1,163 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Device Tree binding constants for AST2700 clock controller.
*
* Copyright (c) 2024 Aspeed Technology Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_AST2700_H
#define __DT_BINDINGS_CLOCK_AST2700_H
/* SOC0 clk */
#define SCU0_CLKIN 0
#define SCU0_CLK_24M 1
#define SCU0_CLK_192M 2
#define SCU0_CLK_UART 3
#define SCU0_CLK_UART_DIV13 3
#define SCU0_CLK_PSP 4
#define SCU0_CLK_HPLL 5
#define SCU0_CLK_HPLL_DIV2 6
#define SCU0_CLK_HPLL_DIV4 7
#define SCU0_CLK_HPLL_DIV_AHB 8
#define SCU0_CLK_DPLL 9
#define SCU0_CLK_MPLL 10
#define SCU0_CLK_MPLL_DIV2 11
#define SCU0_CLK_MPLL_DIV4 12
#define SCU0_CLK_MPLL_DIV8 13
#define SCU0_CLK_MPLL_DIV_AHB 14
#define SCU0_CLK_D0 15
#define SCU0_CLK_D1 16
#define SCU0_CLK_CRT0 17
#define SCU0_CLK_CRT1 18
#define SCU0_CLK_MPHY 19
#define SCU0_CLK_AXI0 20
#define SCU0_CLK_AXI1 21
#define SCU0_CLK_AHB 22
#define SCU0_CLK_APB 23
#define SCU0_CLK_UART4 24
#define SCU0_CLK_EMMCMUX 25
#define SCU0_CLK_EMMC 26
#define SCU0_CLK_U2PHY_CLK12M 27
#define SCU0_CLK_U2PHY_REFCLK 28
/* SOC0 clk-gate */
#define SCU0_CLK_GATE_MCLK 29
#define SCU0_CLK_GATE_ECLK 30
#define SCU0_CLK_GATE_2DCLK 31
#define SCU0_CLK_GATE_VCLK 32
#define SCU0_CLK_GATE_BCLK 33
#define SCU0_CLK_GATE_VGA0CLK 34
#define SCU0_CLK_GATE_REFCLK 35
#define SCU0_CLK_GATE_PORTBUSB2CLK 36
#define SCU0_CLK_GATE_UHCICLK 37
#define SCU0_CLK_GATE_VGA1CLK 38
#define SCU0_CLK_GATE_DDRPHYCLK 39
#define SCU0_CLK_GATE_E2M0CLK 40
#define SCU0_CLK_GATE_HACCLK 41
#define SCU0_CLK_GATE_PORTAUSB2CLK 42
#define SCU0_CLK_GATE_UART4CLK 43
#define SCU0_CLK_GATE_SLICLK 44
#define SCU0_CLK_GATE_DACCLK 45
#define SCU0_CLK_GATE_DP 46
#define SCU0_CLK_GATE_E2M1CLK 47
#define SCU0_CLK_GATE_CRT0CLK 48
#define SCU0_CLK_GATE_CRT1CLK 49
#define SCU0_CLK_GATE_ECDSACLK 50
#define SCU0_CLK_GATE_RSACLK 51
#define SCU0_CLK_GATE_RVAS0CLK 52
#define SCU0_CLK_GATE_UFSCLK 53
#define SCU0_CLK_GATE_EMMCCLK 54
#define SCU0_CLK_GATE_RVAS1CLK 55
/* SOC1 clk */
#define SCU1_CLKIN 0
#define SCU1_CLK_HPLL 1
#define SCU1_CLK_APLL 2
#define SCU1_CLK_APLL_DIV2 3
#define SCU1_CLK_APLL_DIV4 4
#define SCU1_CLK_DPLL 5
#define SCU1_CLK_UXCLK 6
#define SCU1_CLK_HUXCLK 7
#define SCU1_CLK_UARTX 8
#define SCU1_CLK_HUARTX 9
#define SCU1_CLK_AHB 10
#define SCU1_CLK_APB 11
#define SCU1_CLK_UART0 12
#define SCU1_CLK_UART1 13
#define SCU1_CLK_UART2 14
#define SCU1_CLK_UART3 15
#define SCU1_CLK_UART5 16
#define SCU1_CLK_UART6 17
#define SCU1_CLK_UART7 18
#define SCU1_CLK_UART8 19
#define SCU1_CLK_UART9 20
#define SCU1_CLK_UART10 21
#define SCU1_CLK_UART11 22
#define SCU1_CLK_UART12 23
#define SCU1_CLK_UART13 24
#define SCU1_CLK_UART14 25
#define SCU1_CLK_APLL_DIVN 26
#define SCU1_CLK_SDMUX 27
#define SCU1_CLK_SDCLK 28
#define SCU1_CLK_RMII 29
#define SCU1_CLK_RGMII 30
#define SCU1_CLK_MACHCLK 31
#define SCU1_CLK_MAC0RCLK 32
#define SCU1_CLK_MAC1RCLK 33
#define SCU1_CLK_CAN 34
/* SOC1 clk gate */
#define SCU1_CLK_GATE_LCLK0 35
#define SCU1_CLK_GATE_LCLK1 36
#define SCU1_CLK_GATE_ESPI0CLK 37
#define SCU1_CLK_GATE_ESPI1CLK 38
#define SCU1_CLK_GATE_SDCLK 39
#define SCU1_CLK_GATE_IPEREFCLK 40
#define SCU1_CLK_GATE_REFCLK 41
#define SCU1_CLK_GATE_LPCHCLK 42
#define SCU1_CLK_GATE_MAC0CLK 43
#define SCU1_CLK_GATE_MAC1CLK 44
#define SCU1_CLK_GATE_MAC2CLK 45
#define SCU1_CLK_GATE_UART0CLK 46
#define SCU1_CLK_GATE_UART1CLK 47
#define SCU1_CLK_GATE_UART2CLK 48
#define SCU1_CLK_GATE_UART3CLK 49
#define SCU1_CLK_GATE_I2CCLK 50
#define SCU1_CLK_GATE_I3C0CLK 51
#define SCU1_CLK_GATE_I3C1CLK 52
#define SCU1_CLK_GATE_I3C2CLK 53
#define SCU1_CLK_GATE_I3C3CLK 54
#define SCU1_CLK_GATE_I3C4CLK 55
#define SCU1_CLK_GATE_I3C5CLK 56
#define SCU1_CLK_GATE_I3C6CLK 57
#define SCU1_CLK_GATE_I3C7CLK 58
#define SCU1_CLK_GATE_I3C8CLK 59
#define SCU1_CLK_GATE_I3C9CLK 60
#define SCU1_CLK_GATE_I3C10CLK 61
#define SCU1_CLK_GATE_I3C11CLK 62
#define SCU1_CLK_GATE_I3C12CLK 63
#define SCU1_CLK_GATE_I3C13CLK 64
#define SCU1_CLK_GATE_I3C14CLK 65
#define SCU1_CLK_GATE_I3C15CLK 66
#define SCU1_CLK_GATE_UART5CLK 67
#define SCU1_CLK_GATE_UART6CLK 68
#define SCU1_CLK_GATE_UART7CLK 69
#define SCU1_CLK_GATE_UART8CLK 70
#define SCU1_CLK_GATE_UART9CLK 71
#define SCU1_CLK_GATE_UART10CLK 72
#define SCU1_CLK_GATE_UART11CLK 73
#define SCU1_CLK_GATE_UART12CLK 74
#define SCU1_CLK_GATE_FSICLK 75
#define SCU1_CLK_GATE_LTPIPHYCLK 76
#define SCU1_CLK_GATE_LTPICLK 77
#define SCU1_CLK_GATE_VGALCLK 78
#define SCU1_CLK_GATE_UHCICLK 79
#define SCU1_CLK_GATE_CANCLK 80
#define SCU1_CLK_GATE_PCICLK 81
#define SCU1_CLK_GATE_SLICLK 82
#define SCU1_CLK_GATE_E2MCLK 83
#define SCU1_CLK_GATE_PORTCUSB2CLK 84
#define SCU1_CLK_GATE_PORTDUSB2CLK 85
#define SCU1_CLK_GATE_LTPI1TXCLK 86
#endif

124
include/dt-bindings/reset/aspeed,ast2700-scu.h Normal file
View File

@ -0,0 +1,124 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Device Tree binding constants for AST2700 reset controller.
*
* Copyright (c) 2024 Aspeed Technology Inc.
*/
#ifndef _MACH_ASPEED_AST2700_RESET_H_
#define _MACH_ASPEED_AST2700_RESET_H_
/* SOC0 */
#define SCU0_RESET_SDRAM 0
#define SCU0_RESET_DDRPHY 1
#define SCU0_RESET_RSA 2
#define SCU0_RESET_SHA3 3
#define SCU0_RESET_HACE 4
#define SCU0_RESET_SOC 5
#define SCU0_RESET_VIDEO 6
#define SCU0_RESET_2D 7
#define SCU0_RESET_PCIS 8
#define SCU0_RESET_RVAS0 9
#define SCU0_RESET_RVAS1 10
#define SCU0_RESET_SM3 11
#define SCU0_RESET_SM4 12
#define SCU0_RESET_CRT0 13
#define SCU0_RESET_ECC 14
#define SCU0_RESET_DP_PCI 15
#define SCU0_RESET_UFS 16
#define SCU0_RESET_EMMC 17
#define SCU0_RESET_PCIE1RST 18
#define SCU0_RESET_PCIE1RSTOE 19
#define SCU0_RESET_PCIE0RST 20
#define SCU0_RESET_PCIE0RSTOE 21
#define SCU0_RESET_JTAG 22
#define SCU0_RESET_MCTP0 23
#define SCU0_RESET_MCTP1 24
#define SCU0_RESET_XDMA0 25
#define SCU0_RESET_XDMA1 26
#define SCU0_RESET_H2X1 27
#define SCU0_RESET_DP 28
#define SCU0_RESET_DP_MCU 29
#define SCU0_RESET_SSP 30
#define SCU0_RESET_H2X0 31
#define SCU0_RESET_PORTA_VHUB 32
#define SCU0_RESET_PORTA_PHY3 33
#define SCU0_RESET_PORTA_XHCI 34
#define SCU0_RESET_PORTB_VHUB 35
#define SCU0_RESET_PORTB_PHY3 36
#define SCU0_RESET_PORTB_XHCI 37
#define SCU0_RESET_PORTA_VHUB_EHCI 38
#define SCU0_RESET_PORTB_VHUB_EHCI 39
#define SCU0_RESET_UHCI 40
#define SCU0_RESET_TSP 41
#define SCU0_RESET_E2M0 42
#define SCU0_RESET_E2M1 43
#define SCU0_RESET_VLINK 44
/* SOC1 */
#define SCU1_RESET_LPC0 0
#define SCU1_RESET_LPC1 1
#define SCU1_RESET_MII 2
#define SCU1_RESET_PECI 3
#define SCU1_RESET_PWM 4
#define SCU1_RESET_MAC0 5
#define SCU1_RESET_MAC1 6
#define SCU1_RESET_MAC2 7
#define SCU1_RESET_ADC 8
#define SCU1_RESET_SD 9
#define SCU1_RESET_ESPI0 10
#define SCU1_RESET_ESPI1 11
#define SCU1_RESET_JTAG1 12
#define SCU1_RESET_SPI0 13
#define SCU1_RESET_SPI1 14
#define SCU1_RESET_SPI2 15
#define SCU1_RESET_I3C0 16
#define SCU1_RESET_I3C1 17
#define SCU1_RESET_I3C2 18
#define SCU1_RESET_I3C3 19
#define SCU1_RESET_I3C4 20
#define SCU1_RESET_I3C5 21
#define SCU1_RESET_I3C6 22
#define SCU1_RESET_I3C7 23
#define SCU1_RESET_I3C8 24
#define SCU1_RESET_I3C9 25
#define SCU1_RESET_I3C10 26
#define SCU1_RESET_I3C11 27
#define SCU1_RESET_I3C12 28
#define SCU1_RESET_I3C13 29
#define SCU1_RESET_I3C14 30
#define SCU1_RESET_I3C15 31
#define SCU1_RESET_MCU0 32
#define SCU1_RESET_MCU1 33
#define SCU1_RESET_H2A_SPI1 34
#define SCU1_RESET_H2A_SPI2 35
#define SCU1_RESET_UART0 36
#define SCU1_RESET_UART1 37
#define SCU1_RESET_UART2 38
#define SCU1_RESET_UART3 39
#define SCU1_RESET_I2C_FILTER 40
#define SCU1_RESET_CALIPTRA 41
#define SCU1_RESET_XDMA 42
#define SCU1_RESET_FSI 43
#define SCU1_RESET_CAN 44
#define SCU1_RESET_MCTP 45
#define SCU1_RESET_I2C 46
#define SCU1_RESET_UART6 47
#define SCU1_RESET_UART7 48
#define SCU1_RESET_UART8 49
#define SCU1_RESET_UART9 50
#define SCU1_RESET_LTPI0 51
#define SCU1_RESET_VGAL 52
#define SCU1_RESET_LTPI1 53
#define SCU1_RESET_ACE 54
#define SCU1_RESET_E2M 55
#define SCU1_RESET_UHCI 56
#define SCU1_RESET_PORTC_USB2UART 57
#define SCU1_RESET_PORTC_VHUB_EHCI 58
#define SCU1_RESET_PORTD_USB2UART 59
#define SCU1_RESET_PORTD_VHUB_EHCI 60
#define SCU1_RESET_H2X 61
#define SCU1_RESET_I3CDMA 62
#define SCU1_RESET_PCIE2RST 63
#endif /* _MACH_ASPEED_AST2700_RESET_H_ */

4
include/linux/mfd/axp20x.h
View File

@ -19,6 +19,7 @@ enum axp20x_variants {
AXP223_ID,
AXP288_ID,
AXP313A_ID,
AXP323_ID,
AXP717_ID,
AXP803_ID,
AXP806_ID,
@ -113,6 +114,7 @@ enum axp20x_variants {
#define AXP313A_SHUTDOWN_CTRL 0x1a
#define AXP313A_IRQ_EN 0x20
#define AXP313A_IRQ_STATE 0x21
#define AXP323_DCDC_MODE_CTRL2 0x22
#define AXP717_ON_INDICATE 0x00
#define AXP717_PMU_STATUS_2 0x01
@ -959,7 +961,7 @@ struct axp20x_dev {
unsigned long irq_flags;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irqc;
long variant;
enum axp20x_variants variant;
int nr_cells;
const struct mfd_cell *cells;
const struct regmap_config *regmap_cfg;

11
include/linux/mfd/max77693-private.h
View File

@ -419,17 +419,6 @@ enum max77693_haptic_reg {
#define MAX77693_CONFIG2_MEN 6
#define MAX77693_CONFIG2_HTYP 5
enum max77693_irq_source {
LED_INT = 0,
TOPSYS_INT,
CHG_INT,
MUIC_INT1,
MUIC_INT2,
MUIC_INT3,
MAX77693_IRQ_GROUP_NR,
};
#define SRC_IRQ_CHARGER BIT(0)
#define SRC_IRQ_TOP BIT(1)
#define SRC_IRQ_FLASH BIT(2)

53
include/linux/mfd/mt6328/core.h Normal file
View File

@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015 MediaTek Inc.
* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
*/
#ifndef __MFD_MT6328_CORE_H__
#define __MFD_MT6328_CORE_H__
enum mt6328_irq_status_numbers {
MT6328_IRQ_STATUS_PWRKEY = 0,
MT6328_IRQ_STATUS_HOMEKEY,
MT6328_IRQ_STATUS_PWRKEY_R,
MT6328_IRQ_STATUS_HOMEKEY_R,
MT6328_IRQ_STATUS_THR_H,
MT6328_IRQ_STATUS_THR_L,
MT6328_IRQ_STATUS_BAT_H,
MT6328_IRQ_STATUS_BAT_L,
MT6328_IRQ_STATUS_RTC,
MT6328_IRQ_STATUS_AUDIO,
MT6328_IRQ_STATUS_ACCDET,
MT6328_IRQ_STATUS_ACCDET_EINT,
MT6328_IRQ_STATUS_ACCDET_NEGV,
MT6328_IRQ_STATUS_NI_LBAT_INT,
MT6328_IRQ_STATUS_VPROC_OC = 16,
MT6328_IRQ_STATUS_VSYS_OC,
MT6328_IRQ_STATUS_VLTE_OC,
MT6328_IRQ_STATUS_VCORE_OC,
MT6328_IRQ_STATUS_VPA_OC,
MT6328_IRQ_STATUS_LDO_OC,
MT6328_IRQ_STATUS_BAT2_H,
MT6328_IRQ_STATUS_BAT2_L,
MT6328_IRQ_STATUS_VISMPS0_H,
MT6328_IRQ_STATUS_VISMPS0_L,
MT6328_IRQ_STATUS_AUXADC_IMP,
MT6328_IRQ_STATUS_OV = 32,
MT6328_IRQ_STATUS_BVALID_DET,
MT6328_IRQ_STATUS_VBATON_HV,
MT6328_IRQ_STATUS_VBATON_UNDET,
MT6328_IRQ_STATUS_WATCHDOG,
MT6328_IRQ_STATUS_PCHR_CM_VDEC,
MT6328_IRQ_STATUS_CHRDET,
MT6328_IRQ_STATUS_PCHR_CM_VINC,
MT6328_IRQ_STATUS_FG_BAT_H,
MT6328_IRQ_STATUS_FG_BAT_L,
MT6328_IRQ_STATUS_FG_CUR_H,
MT6328_IRQ_STATUS_FG_CUR_L,
MT6328_IRQ_STATUS_FG_ZCV,
MT6328_IRQ_STATUS_SPKL_D,
MT6328_IRQ_STATUS_SPKL_AB,
};
#endif /* __MFD_MT6323_CORE_H__ */

822
include/linux/mfd/mt6328/registers.h Normal file
View File

@ -0,0 +1,822 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
*/
#ifndef __MFD_MT6328_REGISTERS_H__
#define __MFD_MT6328_REGISTERS_H__
/* PMIC Registers */
#define MT6328_STRUP_CON0 0x0000
#define MT6328_STRUP_CON2 0x0002
#define MT6328_STRUP_CON3 0x0004
#define MT6328_STRUP_CON4 0x0006
#define MT6328_STRUP_CON5 0x0008
#define MT6328_STRUP_CON6 0x000a
#define MT6328_STRUP_CON7 0x000c
#define MT6328_STRUP_CON8 0x000e
#define MT6328_STRUP_CON9 0x0010
#define MT6328_STRUP_CON10 0x0012
#define MT6328_STRUP_CON11 0x0014
#define MT6328_STRUP_CON12 0x0016
#define MT6328_STRUP_CON13 0x0018
#define MT6328_STRUP_CON14 0x001a
#define MT6328_STRUP_CON15 0x001c
#define MT6328_STRUP_CON16 0x001e
#define MT6328_STRUP_CON17 0x0020
#define MT6328_STRUP_CON18 0x0022
#define MT6328_STRUP_CON19 0x0024
#define MT6328_STRUP_CON20 0x0026
#define MT6328_STRUP_CON21 0x0028
#define MT6328_STRUP_CON22 0x002a
#define MT6328_STRUP_CON23 0x002c
#define MT6328_STRUP_CON24 0x002e
#define MT6328_STRUP_CON25 0x0030
#define MT6328_STRUP_CON26 0x0032
#define MT6328_STRUP_CON27 0x0034
#define MT6328_STRUP_CON28 0x0036
#define MT6328_STRUP_CON29 0x0038
#define MT6328_STRUP_CON30 0x003a
#define MT6328_STRUP_CON31 0x003c
#define MT6328_STRUP_CON32 0x003e
#define MT6328_STRUP_ANA_CON0 0x0040
#define MT6328_HWCID 0x0200
#define MT6328_SWCID 0x0202
#define MT6328_TOP_CON 0x0204
#define MT6328_TEST_OUT 0x0206
#define MT6328_TEST_CON0 0x0208
#define MT6328_TEST_CON1 0x020a
#define MT6328_TESTMODE_SW 0x020c
#define MT6328_EN_STATUS0 0x020e
#define MT6328_EN_STATUS1 0x0210
#define MT6328_EN_STATUS2 0x0212
#define MT6328_OCSTATUS0 0x0214
#define MT6328_OCSTATUS1 0x0216
#define MT6328_OCSTATUS2 0x0218
#define MT6328_PGDEBSTATUS 0x021a
#define MT6328_PGSTATUS 0x021c
#define MT6328_THERMALSTATUS 0x021e
#define MT6328_TOPSTATUS 0x0220
#define MT6328_TDSEL_CON 0x0222
#define MT6328_RDSEL_CON 0x0224
#define MT6328_SMT_CON0 0x0226
#define MT6328_SMT_CON1 0x0228
#define MT6328_SMT_CON2 0x022a
#define MT6328_DRV_CON0 0x022c
#define MT6328_DRV_CON1 0x022e
#define MT6328_DRV_CON2 0x0230
#define MT6328_DRV_CON3 0x0232
#define MT6328_TOP_STATUS 0x0234
#define MT6328_TOP_STATUS_SET 0x0236
#define MT6328_TOP_STATUS_CLR 0x0238
#define MT6328_RGS_ANA_MON 0x023a
#define MT6328_TOP_CKPDN_CON0 0x023c
#define MT6328_TOP_CKPDN_CON0_SET 0x023e
#define MT6328_TOP_CKPDN_CON0_CLR 0x0240
#define MT6328_TOP_CKPDN_CON1 0x0242
#define MT6328_TOP_CKPDN_CON1_SET 0x0244
#define MT6328_TOP_CKPDN_CON1_CLR 0x0246
#define MT6328_TOP_CKPDN_CON2 0x0248
#define MT6328_TOP_CKPDN_CON2_SET 0x024a
#define MT6328_TOP_CKPDN_CON2_CLR 0x024c
#define MT6328_TOP_CKPDN_CON3 0x024e
#define MT6328_TOP_CKPDN_CON3_SET 0x0250
#define MT6328_TOP_CKPDN_CON3_CLR 0x0252
#define MT6328_TOP_CKPDN_CON4 0x0254
#define MT6328_TOP_CKPDN_CON4_SET 0x0256
#define MT6328_TOP_CKPDN_CON4_CLR 0x0258
#define MT6328_TOP_CKSEL_CON0 0x025a
#define MT6328_TOP_CKSEL_CON0_SET 0x025c
#define MT6328_TOP_CKSEL_CON0_CLR 0x025e
#define MT6328_TOP_CKSEL_CON1 0x0260
#define MT6328_TOP_CKSEL_CON1_SET 0x0262
#define MT6328_TOP_CKSEL_CON1_CLR 0x0264
#define MT6328_TOP_CKSEL_CON2 0x0266
#define MT6328_TOP_CKSEL_CON2_SET 0x0268
#define MT6328_TOP_CKSEL_CON2_CLR 0x026a
#define MT6328_TOP_CKDIVSEL_CON0 0x026c
#define MT6328_TOP_CKDIVSEL_CON0_SET 0x026e
#define MT6328_TOP_CKDIVSEL_CON0_CLR 0x0270
#define MT6328_TOP_CKDIVSEL_CON1 0x0272
#define MT6328_TOP_CKDIVSEL_CON1_SET 0x0274
#define MT6328_TOP_CKDIVSEL_CON1_CLR 0x0276
#define MT6328_TOP_CKHWEN_CON0 0x0278
#define MT6328_TOP_CKHWEN_CON0_SET 0x027a
#define MT6328_TOP_CKHWEN_CON0_CLR 0x027c
#define MT6328_TOP_CKHWEN_CON1 0x027e
#define MT6328_TOP_CKHWEN_CON1_SET 0x0280
#define MT6328_TOP_CKHWEN_CON1_CLR 0x0282
#define MT6328_TOP_CKTST_CON0 0x0284
#define MT6328_TOP_CKTST_CON1 0x0286
#define MT6328_TOP_CKTST_CON2 0x0288
#define MT6328_TOP_CLKSQ 0x028a
#define MT6328_TOP_CLKSQ_SET 0x028c
#define MT6328_TOP_CLKSQ_CLR 0x028e
#define MT6328_TOP_CLKSQ_RTC 0x0290
#define MT6328_TOP_CLKSQ_RTC_SET 0x0292
#define MT6328_TOP_CLKSQ_RTC_CLR 0x0294
#define MT6328_TOP_CLK_TRIM 0x0296
#define MT6328_TOP_RST_CON0 0x0298
#define MT6328_TOP_RST_CON0_SET 0x029a
#define MT6328_TOP_RST_CON0_CLR 0x029c
#define MT6328_TOP_RST_CON1 0x029e
#define MT6328_TOP_RST_MISC 0x02a0
#define MT6328_TOP_RST_MISC_SET 0x02a2
#define MT6328_TOP_RST_MISC_CLR 0x02a4
#define MT6328_TOP_RST_STATUS 0x02a6
#define MT6328_TOP_RST_STATUS_SET 0x02a8
#define MT6328_TOP_RST_STATUS_CLR 0x02aa
#define MT6328_INT_CON0 0x02ac
#define MT6328_INT_CON0_SET 0x02ae
#define MT6328_INT_CON0_CLR 0x02b0
#define MT6328_INT_CON1 0x02b2
#define MT6328_INT_CON1_SET 0x02b4
#define MT6328_INT_CON1_CLR 0x02b6
#define MT6328_INT_CON2 0x02b8
#define MT6328_INT_CON2_SET 0x02ba
#define MT6328_INT_CON2_CLR 0x02bc
#define MT6328_INT_MISC_CON 0x02be
#define MT6328_INT_MISC_CON_SET 0x02c0
#define MT6328_INT_MISC_CON_CLR 0x02c2
#define MT6328_INT_STATUS0 0x02c4
#define MT6328_INT_STATUS1 0x02c6
#define MT6328_INT_STATUS2 0x02c8
#define MT6328_OC_GEAR_0 0x02ca
#define MT6328_FQMTR_CON0 0x02cc
#define MT6328_FQMTR_CON1 0x02ce
#define MT6328_FQMTR_CON2 0x02d0
#define MT6328_RG_SPI_CON 0x02d2
#define MT6328_DEW_DIO_EN 0x02d4
#define MT6328_DEW_READ_TEST 0x02d6
#define MT6328_DEW_WRITE_TEST 0x02d8
#define MT6328_DEW_CRC_SWRST 0x02da
#define MT6328_DEW_CRC_EN 0x02dc
#define MT6328_DEW_CRC_VAL 0x02de
#define MT6328_DEW_DBG_MON_SEL 0x02e0
#define MT6328_DEW_CIPHER_KEY_SEL 0x02e2
#define MT6328_DEW_CIPHER_IV_SEL 0x02e4
#define MT6328_DEW_CIPHER_EN 0x02e6
#define MT6328_DEW_CIPHER_RDY 0x02e8
#define MT6328_DEW_CIPHER_MODE 0x02ea
#define MT6328_DEW_CIPHER_SWRST 0x02ec
#define MT6328_DEW_RDDMY_NO 0x02ee
#define MT6328_INT_TYPE_CON0 0x02f0
#define MT6328_INT_TYPE_CON0_SET 0x02f2
#define MT6328_INT_TYPE_CON0_CLR 0x02f4
#define MT6328_INT_TYPE_CON1 0x02f6
#define MT6328_INT_TYPE_CON1_SET 0x02f8
#define MT6328_INT_TYPE_CON1_CLR 0x02fa
#define MT6328_INT_TYPE_CON2 0x02fc
#define MT6328_INT_TYPE_CON2_SET 0x02fe
#define MT6328_INT_TYPE_CON2_CLR 0x0300
#define MT6328_INT_STA 0x0302
#define MT6328_BUCK_ALL_CON0 0x0400
#define MT6328_BUCK_ALL_CON1 0x0402
#define MT6328_BUCK_ALL_CON2 0x0404
#define MT6328_BUCK_ALL_CON3 0x0406
#define MT6328_BUCK_ALL_CON4 0x0408
#define MT6328_BUCK_ALL_CON5 0x040a
#define MT6328_BUCK_ALL_CON6 0x040c
#define MT6328_BUCK_ALL_CON9 0x040e
#define MT6328_BUCK_ALL_CON12 0x0410
#define MT6328_BUCK_ALL_CON13 0x0412
#define MT6328_BUCK_ALL_CON14 0x0414
#define MT6328_BUCK_ALL_CON16 0x0416
#define MT6328_BUCK_ALL_CON18 0x0418
#define MT6328_BUCK_ALL_CON19 0x041a
#define MT6328_BUCK_ALL_CON20 0x041c
#define MT6328_BUCK_ALL_CON21 0x041e
#define MT6328_BUCK_ALL_CON22 0x0420
#define MT6328_BUCK_ALL_CON23 0x0422
#define MT6328_BUCK_ALL_CON24 0x0424
#define MT6328_BUCK_ALL_CON25 0x0426
#define MT6328_BUCK_ALL_CON26 0x0428
#define MT6328_BUCK_ALL_CON27 0x042a
#define MT6328_BUCK_ALL_CON28 0x042c
#define MT6328_SMPS_TOP_ANA_CON0 0x042e
#define MT6328_SMPS_TOP_ANA_CON1 0x0430
#define MT6328_SMPS_TOP_ANA_CON2 0x0432
#define MT6328_SMPS_TOP_ANA_CON3 0x0434
#define MT6328_SMPS_TOP_ANA_CON4 0x0436
#define MT6328_SMPS_TOP_ANA_CON5 0x0438
#define MT6328_SMPS_TOP_ANA_CON6 0x043a
#define MT6328_SMPS_TOP_ANA_CON7 0x043c
#define MT6328_SMPS_TOP_ANA_CON8 0x043e
#define MT6328_VCORE_ANA_CON0 0x0440
#define MT6328_VCORE_ANA_CON1 0x0442
#define MT6328_VCORE_ANA_CON2 0x0444
#define MT6328_VCORE_ANA_CON3 0x0446
#define MT6328_VCORE_ANA_CON4 0x0448
#define MT6328_VSYS22_ANA_CON0 0x044a
#define MT6328_VSYS22_ANA_CON1 0x044c
#define MT6328_VSYS22_ANA_CON2 0x044e
#define MT6328_VSYS22_ANA_CON3 0x0450
#define MT6328_VSYS22_ANA_CON4 0x0452
#define MT6328_VPROC_ANA_CON0 0x0454
#define MT6328_VPROC_ANA_CON1 0x0456
#define MT6328_VPROC_ANA_CON2 0x0458
#define MT6328_VPROC_ANA_CON3 0x045a
#define MT6328_VPROC_ANA_CON4 0x045c
#define MT6328_OSC32_ANA_CON0 0x045e
#define MT6328_OSC32_ANA_CON1 0x0460
#define MT6328_VPA_ANA_CON0 0x0462
#define MT6328_VPA_ANA_CON1 0x0464
#define MT6328_VPA_ANA_CON2 0x0466
#define MT6328_VPA_ANA_CON3 0x0468
#define MT6328_VLTE_ANA_CON0 0x046a
#define MT6328_VLTE_ANA_CON1 0x046c
#define MT6328_VLTE_ANA_CON2 0x046e
#define MT6328_VLTE_ANA_CON3 0x0470
#define MT6328_VLTE_ANA_CON4 0x0472
#define MT6328_VPROC_CON0 0x0474
#define MT6328_VPROC_CON1 0x0476
#define MT6328_VPROC_CON2 0x0478
#define MT6328_VPROC_CON3 0x047a
#define MT6328_VPROC_CON4 0x047c
#define MT6328_VPROC_CON5 0x047e
#define MT6328_VPROC_CON6 0x0480
#define MT6328_VPROC_CON7 0x0482
#define MT6328_VPROC_CON8 0x0484
#define MT6328_VPROC_CON9 0x0486
#define MT6328_VPROC_CON10 0x0488
#define MT6328_VPROC_CON11 0x048a
#define MT6328_VPROC_CON12 0x048c
#define MT6328_VPROC_CON13 0x048e
#define MT6328_VPROC_CON14 0x0490
#define MT6328_VPROC_CON15 0x0492
#define MT6328_VPROC_CON16 0x0494
#define MT6328_VPROC_CON17 0x0496
#define MT6328_VPROC_CON18 0x0498
#define MT6328_VPROC_CON19 0x049a
#define MT6328_VSRAM_CON0 0x049c
#define MT6328_VSRAM_CON1 0x049e
#define MT6328_VSRAM_CON2 0x04a0
#define MT6328_VSRAM_CON3 0x04a2
#define MT6328_VSRAM_CON4 0x04a4
#define MT6328_VSRAM_CON5 0x04a6
#define MT6328_VSRAM_CON6 0x04a8
#define MT6328_VSRAM_CON7 0x04aa
#define MT6328_VSRAM_CON8 0x04ac
#define MT6328_VSRAM_CON9 0x04ae
#define MT6328_VSRAM_CON10 0x04b0
#define MT6328_VSRAM_CON11 0x04b2
#define MT6328_VSRAM_CON12 0x04b4
#define MT6328_VSRAM_CON13 0x04b6
#define MT6328_VSRAM_CON14 0x04b8
#define MT6328_VSRAM_CON15 0x04ba
#define MT6328_VSRAM_CON16 0x04bc
#define MT6328_VSRAM_CON17 0x04be
#define MT6328_VSRAM_CON18 0x04c0
#define MT6328_VSRAM_CON19 0x04c2
#define MT6328_VLTE_CON0 0x04c4
#define MT6328_VLTE_CON1 0x04c6
#define MT6328_VLTE_CON2 0x04c8
#define MT6328_VLTE_CON3 0x04ca
#define MT6328_VLTE_CON4 0x04cc
#define MT6328_VLTE_CON5 0x04ce
#define MT6328_VLTE_CON6 0x04d0
#define MT6328_VLTE_CON7 0x04d2
#define MT6328_VLTE_CON8 0x04d4
#define MT6328_VLTE_CON9 0x04d6
#define MT6328_VLTE_CON10 0x04d8
#define MT6328_VLTE_CON11 0x04da
#define MT6328_VLTE_CON12 0x04dc
#define MT6328_VLTE_CON13 0x04de
#define MT6328_VLTE_CON14 0x04e0
#define MT6328_VLTE_CON15 0x04e2
#define MT6328_VLTE_CON16 0x04e4
#define MT6328_VLTE_CON17 0x04e6
#define MT6328_VLTE_CON18 0x04e8
#define MT6328_VLTE_CON19 0x04ea
#define MT6328_VCORE1_CON0 0x0600
#define MT6328_VCORE1_CON1 0x0602
#define MT6328_VCORE1_CON2 0x0604
#define MT6328_VCORE1_CON3 0x0606
#define MT6328_VCORE1_CON4 0x0608
#define MT6328_VCORE1_CON5 0x060a
#define MT6328_VCORE1_CON6 0x060c
#define MT6328_VCORE1_CON7 0x060e
#define MT6328_VCORE1_CON8 0x0610
#define MT6328_VCORE1_CON9 0x0612
#define MT6328_VCORE1_CON10 0x0614
#define MT6328_VCORE1_CON11 0x0616
#define MT6328_VCORE1_CON12 0x0618
#define MT6328_VCORE1_CON13 0x061a
#define MT6328_VCORE1_CON14 0x061c
#define MT6328_VCORE1_CON15 0x061e
#define MT6328_VCORE1_CON16 0x0620
#define MT6328_VCORE1_CON17 0x0622
#define MT6328_VCORE1_CON18 0x0624
#define MT6328_VCORE1_CON19 0x0626
#define MT6328_VSYS22_CON0 0x0628
#define MT6328_VSYS22_CON1 0x062a
#define MT6328_VSYS22_CON2 0x062c
#define MT6328_VSYS22_CON3 0x062e
#define MT6328_VSYS22_CON4 0x0630
#define MT6328_VSYS22_CON5 0x0632
#define MT6328_VSYS22_CON6 0x0634
#define MT6328_VSYS22_CON7 0x0636
#define MT6328_VSYS22_CON8 0x0638
#define MT6328_VSYS22_CON9 0x063a
#define MT6328_VSYS22_CON10 0x063c
#define MT6328_VSYS22_CON11 0x063e
#define MT6328_VSYS22_CON12 0x0640
#define MT6328_VSYS22_CON13 0x0642
#define MT6328_VSYS22_CON14 0x0644
#define MT6328_VSYS22_CON15 0x0646
#define MT6328_VSYS22_CON16 0x0648
#define MT6328_VSYS22_CON17 0x064a
#define MT6328_VSYS22_CON18 0x064c
#define MT6328_VSYS22_CON19 0x064e
#define MT6328_VPA_CON0 0x0650
#define MT6328_VPA_CON1 0x0652
#define MT6328_VPA_CON2 0x0654
#define MT6328_VPA_CON3 0x0656
#define MT6328_VPA_CON4 0x0658
#define MT6328_VPA_CON5 0x065a
#define MT6328_VPA_CON6 0x065c
#define MT6328_VPA_CON7 0x065e
#define MT6328_VPA_CON8 0x0660
#define MT6328_VPA_CON9 0x0662
#define MT6328_VPA_CON10 0x0664
#define MT6328_VPA_CON11 0x0666
#define MT6328_VPA_CON12 0x0668
#define MT6328_VPA_CON13 0x066a
#define MT6328_VPA_CON14 0x066c
#define MT6328_VPA_CON15 0x066e
#define MT6328_VPA_CON16 0x0670
#define MT6328_VPA_CON17 0x0672
#define MT6328_VPA_CON18 0x0674
#define MT6328_VPA_CON19 0x0676
#define MT6328_VPA_CON20 0x0678
#define MT6328_VPA_CON21 0x067a
#define MT6328_VPA_CON22 0x067c
#define MT6328_VPA_CON23 0x067e
#define MT6328_VPA_CON24 0x0680
#define MT6328_BUCK_K_CON0 0x0682
#define MT6328_BUCK_K_CON1 0x0684
#define MT6328_BUCK_K_CON2 0x0686
#define MT6328_BUCK_K_CON3 0x0688
#define MT6328_ZCD_CON0 0x0800
#define MT6328_ZCD_CON1 0x0802
#define MT6328_ZCD_CON2 0x0804
#define MT6328_ZCD_CON3 0x0806
#define MT6328_ZCD_CON4 0x0808
#define MT6328_ZCD_CON5 0x080a
#define MT6328_ISINK0_CON0 0x080c
#define MT6328_ISINK0_CON1 0x080e
#define MT6328_ISINK0_CON2 0x0810
#define MT6328_ISINK0_CON3 0x0812
#define MT6328_ISINK1_CON0 0x0814
#define MT6328_ISINK1_CON1 0x0816
#define MT6328_ISINK1_CON2 0x0818
#define MT6328_ISINK1_CON3 0x081a
#define MT6328_ISINK2_CON1 0x081c
#define MT6328_ISINK3_CON1 0x081e
#define MT6328_ISINK_ANA0 0x0820
#define MT6328_ISINK_ANA1 0x0822
#define MT6328_ISINK_PHASE_DLY 0x0824
#define MT6328_ISINK_SFSTR 0x0826
#define MT6328_ISINK_EN_CTRL 0x0828
#define MT6328_ISINK_MODE_CTRL 0x082a
#define MT6328_VTCXO_0_CON0 0x0a00
#define MT6328_VTCXO_1_CON0 0x0a02
#define MT6328_VAUD28_CON0 0x0a04
#define MT6328_VAUX18_CON0 0x0a06
#define MT6328_VRF18_0_CON0 0x0a08
#define MT6328_VRF18_0_CON1 0x0a0a
#define MT6328_VCAMA_CON0 0x0a0c
#define MT6328_VCN28_CON0 0x0a0e
#define MT6328_VCN33_CON0 0x0a10
#define MT6328_VCN33_CON1 0x0a12
#define MT6328_VCN33_CON2 0x0a14
#define MT6328_VRF18_1_CON0 0x0a16
#define MT6328_VRF18_1_CON1 0x0a18
#define MT6328_VUSB33_CON0 0x0a1a
#define MT6328_VMCH_CON0 0x0a1c
#define MT6328_VMCH_CON1 0x0a1e
#define MT6328_VMC_CON0 0x0a20
#define MT6328_VMC_CON1 0x0a22
#define MT6328_VEMC_3V3_CON0 0x0a24
#define MT6328_VEMC_3V3_CON1 0x0a26
#define MT6328_VIO28_CON0 0x0a28
#define MT6328_VCAMAF_CON0 0x0a2a
#define MT6328_VGP1_CON0 0x0a2c
#define MT6328_VGP1_CON1 0x0a2e
#define MT6328_VEFUSE_CON0 0x0a30
#define MT6328_VSIM1_CON0 0x0a32
#define MT6328_VSIM2_CON0 0x0a34
#define MT6328_VIO18_CON0 0x0a36
#define MT6328_VIBR_CON0 0x0a38
#define MT6328_VCN18_CON0 0x0a3a
#define MT6328_VCAM_CON0 0x0a3c
#define MT6328_VCAMIO_CON0 0x0a3e
#define MT6328_LDO_VSRAM_CON0 0x0a40
#define MT6328_LDO_VSRAM_CON1 0x0a42
#define MT6328_VTREF_CON0 0x0a44
#define MT6328_VM_CON0 0x0a46
#define MT6328_VM_CON1 0x0a48
#define MT6328_VRTC_CON0 0x0a4a
#define MT6328_LDO_OCFB0 0x0a4c
#define MT6328_ALDO_ANA_CON0 0x0a4e
#define MT6328_ADLDO_ANA_CON1 0x0a50
#define MT6328_ADLDO_ANA_CON2 0x0a52
#define MT6328_ADLDO_ANA_CON3 0x0a54
#define MT6328_ADLDO_ANA_CON4 0x0a56
#define MT6328_ADLDO_ANA_CON5 0x0a58
#define MT6328_ADLDO_ANA_CON6 0x0a5a
#define MT6328_ADLDO_ANA_CON7 0x0a5c
#define MT6328_ADLDO_ANA_CON8 0x0a5e
#define MT6328_ADLDO_ANA_CON9 0x0a60
#define MT6328_ADLDO_ANA_CON10 0x0a62
#define MT6328_ADLDO_ANA_CON11 0x0a64
#define MT6328_ADLDO_ANA_CON12 0x0a66
#define MT6328_ADLDO_ANA_CON13 0x0a68
#define MT6328_DLDO_ANA_CON0 0x0a6a
#define MT6328_DLDO_ANA_CON1 0x0a6c
#define MT6328_DLDO_ANA_CON2 0x0a6e
#define MT6328_DLDO_ANA_CON3 0x0a70
#define MT6328_DLDO_ANA_CON4 0x0a72
#define MT6328_DLDO_ANA_CON5 0x0a74
#define MT6328_SLDO_ANA_CON0 0x0a76
#define MT6328_SLDO_ANA_CON1 0x0a78
#define MT6328_SLDO_ANA_CON2 0x0a7a
#define MT6328_SLDO_ANA_CON3 0x0a7c
#define MT6328_SLDO_ANA_CON4 0x0a7e
#define MT6328_SLDO_ANA_CON5 0x0a80
#define MT6328_SLDO_ANA_CON6 0x0a82
#define MT6328_SLDO_ANA_CON7 0x0a84
#define MT6328_SLDO_ANA_CON8 0x0a86
#define MT6328_SLDO_ANA_CON9 0x0a88
#define MT6328_SLDO_ANA_CON10 0x0a8a
#define MT6328_LDO_RSV_CON0 0x0a8c
#define MT6328_LDO_RSV_CON1 0x0a8e
#define MT6328_SPK_CON0 0x0a90
#define MT6328_SPK_CON1 0x0a92
#define MT6328_SPK_CON2 0x0a94
#define MT6328_SPK_CON3 0x0a96
#define MT6328_SPK_CON4 0x0a98
#define MT6328_SPK_CON5 0x0a9a
#define MT6328_SPK_CON6 0x0a9c
#define MT6328_SPK_CON7 0x0a9e
#define MT6328_SPK_CON8 0x0aa0
#define MT6328_SPK_CON9 0x0aa2
#define MT6328_SPK_CON10 0x0aa4
#define MT6328_SPK_CON11 0x0aa6
#define MT6328_SPK_CON12 0x0aa8
#define MT6328_SPK_CON13 0x0aaa
#define MT6328_SPK_CON14 0x0aac
#define MT6328_SPK_CON15 0x0aae
#define MT6328_SPK_CON16 0x0ab0
#define MT6328_SPK_ANA_CON0 0x0ab2
#define MT6328_SPK_ANA_CON1 0x0ab4
#define MT6328_SPK_ANA_CON3 0x0ab6
#define MT6328_OTP_CON0 0x0c00
#define MT6328_OTP_CON1 0x0c02
#define MT6328_OTP_CON2 0x0c04
#define MT6328_OTP_CON3 0x0c06
#define MT6328_OTP_CON4 0x0c08
#define MT6328_OTP_CON5 0x0c0a
#define MT6328_OTP_CON6 0x0c0c
#define MT6328_OTP_CON7 0x0c0e
#define MT6328_OTP_CON8 0x0c10
#define MT6328_OTP_CON9 0x0c12
#define MT6328_OTP_CON10 0x0c14
#define MT6328_OTP_CON11 0x0c16
#define MT6328_OTP_CON12 0x0c18
#define MT6328_OTP_CON13 0x0c1a
#define MT6328_OTP_CON14 0x0c1c
#define MT6328_OTP_DOUT_0_15 0x0c1e
#define MT6328_OTP_DOUT_16_31 0x0c20
#define MT6328_OTP_DOUT_32_47 0x0c22
#define MT6328_OTP_DOUT_48_63 0x0c24
#define MT6328_OTP_DOUT_64_79 0x0c26
#define MT6328_OTP_DOUT_80_95 0x0c28
#define MT6328_OTP_DOUT_96_111 0x0c2a
#define MT6328_OTP_DOUT_112_127 0x0c2c
#define MT6328_OTP_DOUT_128_143 0x0c2e
#define MT6328_OTP_DOUT_144_159 0x0c30
#define MT6328_OTP_DOUT_160_175 0x0c32
#define MT6328_OTP_DOUT_176_191 0x0c34
#define MT6328_OTP_DOUT_192_207 0x0c36
#define MT6328_OTP_DOUT_208_223 0x0c38
#define MT6328_OTP_DOUT_224_239 0x0c3a
#define MT6328_OTP_DOUT_240_255 0x0c3c
#define MT6328_OTP_DOUT_256_271 0x0c3e
#define MT6328_OTP_DOUT_272_287 0x0c40
#define MT6328_OTP_DOUT_288_303 0x0c42
#define MT6328_OTP_DOUT_304_319 0x0c44
#define MT6328_OTP_DOUT_320_335 0x0c46
#define MT6328_OTP_DOUT_336_351 0x0c48
#define MT6328_OTP_DOUT_352_367 0x0c4a
#define MT6328_OTP_DOUT_368_383 0x0c4c
#define MT6328_OTP_DOUT_384_399 0x0c4e
#define MT6328_OTP_DOUT_400_415 0x0c50
#define MT6328_OTP_DOUT_416_431 0x0c52
#define MT6328_OTP_DOUT_432_447 0x0c54
#define MT6328_OTP_DOUT_448_463 0x0c56
#define MT6328_OTP_DOUT_464_479 0x0c58
#define MT6328_OTP_DOUT_480_495 0x0c5a
#define MT6328_OTP_DOUT_496_511 0x0c5c
#define MT6328_OTP_VAL_0_15 0x0c5e
#define MT6328_OTP_VAL_16_31 0x0c60
#define MT6328_OTP_VAL_32_47 0x0c62
#define MT6328_OTP_VAL_48_63 0x0c64
#define MT6328_OTP_VAL_64_79 0x0c66
#define MT6328_OTP_VAL_80_95 0x0c68
#define MT6328_OTP_VAL_96_111 0x0c6a
#define MT6328_OTP_VAL_112_127 0x0c6c
#define MT6328_OTP_VAL_128_143 0x0c6e
#define MT6328_OTP_VAL_144_159 0x0c70
#define MT6328_OTP_VAL_160_175 0x0c72
#define MT6328_OTP_VAL_176_191 0x0c74
#define MT6328_OTP_VAL_192_207 0x0c76
#define MT6328_OTP_VAL_208_223 0x0c78
#define MT6328_OTP_VAL_224_239 0x0c7a
#define MT6328_OTP_VAL_240_255 0x0c7c
#define MT6328_OTP_VAL_256_271 0x0c7e
#define MT6328_OTP_VAL_272_287 0x0c80
#define MT6328_OTP_VAL_288_303 0x0c82
#define MT6328_OTP_VAL_304_319 0x0c84
#define MT6328_OTP_VAL_320_335 0x0c86
#define MT6328_OTP_VAL_336_351 0x0c88
#define MT6328_OTP_VAL_352_367 0x0c8a
#define MT6328_OTP_VAL_368_383 0x0c8c
#define MT6328_OTP_VAL_384_399 0x0c8e
#define MT6328_OTP_VAL_400_415 0x0c90
#define MT6328_OTP_VAL_416_431 0x0c92
#define MT6328_OTP_VAL_432_447 0x0c94
#define MT6328_OTP_VAL_448_463 0x0c96
#define MT6328_OTP_VAL_464_479 0x0c98
#define MT6328_OTP_VAL_480_495 0x0c9a
#define MT6328_OTP_VAL_496_511 0x0c9c
#define MT6328_RTC_MIX_CON0 0x0c9e
#define MT6328_RTC_MIX_CON1 0x0ca0
#define MT6328_RTC_MIX_CON2 0x0ca2
#define MT6328_FGADC_CON0 0x0ca4
#define MT6328_FGADC_CON1 0x0ca6
#define MT6328_FGADC_CON2 0x0ca8
#define MT6328_FGADC_CON3 0x0caa
#define MT6328_FGADC_CON4 0x0cac
#define MT6328_FGADC_CON5 0x0cae
#define MT6328_FGADC_CON6 0x0cb0
#define MT6328_FGADC_CON7 0x0cb2
#define MT6328_FGADC_CON8 0x0cb4
#define MT6328_FGADC_CON9 0x0cb6
#define MT6328_FGADC_CON10 0x0cb8
#define MT6328_FGADC_CON11 0x0cba
#define MT6328_FGADC_CON12 0x0cbc
#define MT6328_FGADC_CON13 0x0cbe
#define MT6328_FGADC_CON14 0x0cc0
#define MT6328_FGADC_CON15 0x0cc2
#define MT6328_FGADC_CON16 0x0cc4
#define MT6328_FGADC_CON17 0x0cc6
#define MT6328_FGADC_CON18 0x0cc8
#define MT6328_FGADC_CON19 0x0cca
#define MT6328_FGADC_CON20 0x0ccc
#define MT6328_FGADC_CON21 0x0cce
#define MT6328_FGADC_CON22 0x0cd0
#define MT6328_FGADC_CON23 0x0cd2
#define MT6328_FGADC_CON24 0x0cd4
#define MT6328_FGADC_CON25 0x0cd6
#define MT6328_FGADC_CON26 0x0cd8
#define MT6328_FGADC_CON27 0x0cda
#define MT6328_AUDDEC_ANA_CON0 0x0cdc
#define MT6328_AUDDEC_ANA_CON1 0x0cde
#define MT6328_AUDDEC_ANA_CON2 0x0ce0
#define MT6328_AUDDEC_ANA_CON3 0x0ce2
#define MT6328_AUDDEC_ANA_CON4 0x0ce4
#define MT6328_AUDDEC_ANA_CON5 0x0ce6
#define MT6328_AUDDEC_ANA_CON6 0x0ce8
#define MT6328_AUDDEC_ANA_CON7 0x0cea
#define MT6328_AUDDEC_ANA_CON8 0x0cec
#define MT6328_AUDENC_ANA_CON0 0x0cee
#define MT6328_AUDENC_ANA_CON1 0x0cf0
#define MT6328_AUDENC_ANA_CON2 0x0cf2
#define MT6328_AUDENC_ANA_CON3 0x0cf4
#define MT6328_AUDENC_ANA_CON4 0x0cf6
#define MT6328_AUDENC_ANA_CON5 0x0cf8
#define MT6328_AUDENC_ANA_CON6 0x0cfa
#define MT6328_AUDENC_ANA_CON7 0x0cfc
#define MT6328_AUDENC_ANA_CON8 0x0cfe
#define MT6328_AUDENC_ANA_CON9 0x0d00
#define MT6328_AUDENC_ANA_CON10 0x0d02
#define MT6328_AUDNCP_CLKDIV_CON0 0x0d04
#define MT6328_AUDNCP_CLKDIV_CON1 0x0d06
#define MT6328_AUDNCP_CLKDIV_CON2 0x0d08
#define MT6328_AUDNCP_CLKDIV_CON3 0x0d0a
#define MT6328_AUDNCP_CLKDIV_CON4 0x0d0c
#define MT6328_AUXADC_ADC0 0x0e00
#define MT6328_AUXADC_ADC1 0x0e02
#define MT6328_AUXADC_ADC2 0x0e04
#define MT6328_AUXADC_ADC3 0x0e06
#define MT6328_AUXADC_ADC4 0x0e08
#define MT6328_AUXADC_ADC5 0x0e0a
#define MT6328_AUXADC_ADC6 0x0e0c
#define MT6328_AUXADC_ADC7 0x0e0e
#define MT6328_AUXADC_ADC8 0x0e10
#define MT6328_AUXADC_ADC9 0x0e12
#define MT6328_AUXADC_ADC10 0x0e14
#define MT6328_AUXADC_ADC11 0x0e16
#define MT6328_AUXADC_ADC12 0x0e18
#define MT6328_AUXADC_ADC13 0x0e1a
#define MT6328_AUXADC_ADC14 0x0e1c
#define MT6328_AUXADC_ADC15 0x0e1e
#define MT6328_AUXADC_ADC16 0x0e20
#define MT6328_AUXADC_ADC17 0x0e22
#define MT6328_AUXADC_ADC18 0x0e24
#define MT6328_AUXADC_ADC19 0x0e26
#define MT6328_AUXADC_ADC20 0x0e28
#define MT6328_AUXADC_ADC21 0x0e2a
#define MT6328_AUXADC_ADC22 0x0e2c
#define MT6328_AUXADC_ADC23 0x0e2e
#define MT6328_AUXADC_ADC24 0x0e30
#define MT6328_AUXADC_ADC25 0x0e32
#define MT6328_AUXADC_ADC26 0x0e34
#define MT6328_AUXADC_ADC27 0x0e36
#define MT6328_AUXADC_ADC28 0x0e38
#define MT6328_AUXADC_ADC29 0x0e3a
#define MT6328_AUXADC_ADC30 0x0e3c
#define MT6328_AUXADC_ADC31 0x0e3e
#define MT6328_AUXADC_ADC32 0x0e40
#define MT6328_AUXADC_ADC33 0x0e42
#define MT6328_AUXADC_BUF0 0x0e44
#define MT6328_AUXADC_BUF1 0x0e46
#define MT6328_AUXADC_BUF2 0x0e48
#define MT6328_AUXADC_BUF3 0x0e4a
#define MT6328_AUXADC_BUF4 0x0e4c
#define MT6328_AUXADC_BUF5 0x0e4e
#define MT6328_AUXADC_BUF6 0x0e50
#define MT6328_AUXADC_BUF7 0x0e52
#define MT6328_AUXADC_BUF8 0x0e54
#define MT6328_AUXADC_BUF9 0x0e56
#define MT6328_AUXADC_BUF10 0x0e58
#define MT6328_AUXADC_BUF11 0x0e5a
#define MT6328_AUXADC_BUF12 0x0e5c
#define MT6328_AUXADC_BUF13 0x0e5e
#define MT6328_AUXADC_BUF14 0x0e60
#define MT6328_AUXADC_BUF15 0x0e62
#define MT6328_AUXADC_BUF16 0x0e64
#define MT6328_AUXADC_BUF17 0x0e66
#define MT6328_AUXADC_BUF18 0x0e68
#define MT6328_AUXADC_BUF19 0x0e6a
#define MT6328_AUXADC_BUF20 0x0e6c
#define MT6328_AUXADC_BUF21 0x0e6e
#define MT6328_AUXADC_BUF22 0x0e70
#define MT6328_AUXADC_BUF23 0x0e72
#define MT6328_AUXADC_BUF24 0x0e74
#define MT6328_AUXADC_BUF25 0x0e76
#define MT6328_AUXADC_BUF26 0x0e78
#define MT6328_AUXADC_BUF27 0x0e7a
#define MT6328_AUXADC_BUF28 0x0e7c
#define MT6328_AUXADC_BUF29 0x0e7e
#define MT6328_AUXADC_BUF30 0x0e80
#define MT6328_AUXADC_BUF31 0x0e82
#define MT6328_AUXADC_STA0 0x0e84
#define MT6328_AUXADC_STA1 0x0e86
#define MT6328_AUXADC_RQST0 0x0e88
#define MT6328_AUXADC_RQST0_SET 0x0e8a
#define MT6328_AUXADC_RQST0_CLR 0x0e8c
#define MT6328_AUXADC_RQST1 0x0e8e
#define MT6328_AUXADC_RQST1_SET 0x0e90
#define MT6328_AUXADC_RQST1_CLR 0x0e92
#define MT6328_AUXADC_CON0 0x0e94
#define MT6328_AUXADC_CON0_SET 0x0e96
#define MT6328_AUXADC_CON0_CLR 0x0e98
#define MT6328_AUXADC_CON1 0x0e9a
#define MT6328_AUXADC_CON2 0x0e9c
#define MT6328_AUXADC_CON3 0x0e9e
#define MT6328_AUXADC_CON4 0x0ea0
#define MT6328_AUXADC_CON5 0x0ea2
#define MT6328_AUXADC_CON6 0x0ea4
#define MT6328_AUXADC_CON7 0x0ea6
#define MT6328_AUXADC_CON8 0x0ea8
#define MT6328_AUXADC_CON9 0x0eaa
#define MT6328_AUXADC_CON10 0x0eac
#define MT6328_AUXADC_CON11 0x0eae
#define MT6328_AUXADC_CON12 0x0eb0
#define MT6328_AUXADC_CON13 0x0eb2
#define MT6328_AUXADC_CON14 0x0eb4
#define MT6328_AUXADC_CON15 0x0eb6
#define MT6328_AUXADC_CON16 0x0eb8
#define MT6328_AUXADC_AUTORPT0 0x0eba
#define MT6328_AUXADC_LBAT0 0x0ebc
#define MT6328_AUXADC_LBAT1 0x0ebe
#define MT6328_AUXADC_LBAT2 0x0ec0
#define MT6328_AUXADC_LBAT3 0x0ec2
#define MT6328_AUXADC_LBAT4 0x0ec4
#define MT6328_AUXADC_LBAT5 0x0ec6
#define MT6328_AUXADC_LBAT6 0x0ec8
#define MT6328_AUXADC_ACCDET 0x0eca
#define MT6328_AUXADC_THR0 0x0ecc
#define MT6328_AUXADC_THR1 0x0ece
#define MT6328_AUXADC_THR2 0x0ed0
#define MT6328_AUXADC_THR3 0x0ed2
#define MT6328_AUXADC_THR4 0x0ed4
#define MT6328_AUXADC_THR5 0x0ed6
#define MT6328_AUXADC_THR6 0x0ed8
#define MT6328_AUXADC_EFUSE0 0x0eda
#define MT6328_AUXADC_EFUSE1 0x0edc
#define MT6328_AUXADC_EFUSE2 0x0ede
#define MT6328_AUXADC_EFUSE3 0x0ee0
#define MT6328_AUXADC_EFUSE4 0x0ee2
#define MT6328_AUXADC_EFUSE5 0x0ee4
#define MT6328_AUXADC_DBG0 0x0ee6
#define MT6328_AUXADC_IMP0 0x0ee8
#define MT6328_AUXADC_IMP1 0x0eea
#define MT6328_AUXADC_VISMPS0_1 0x0eec
#define MT6328_AUXADC_VISMPS0_2 0x0eee
#define MT6328_AUXADC_VISMPS0_3 0x0ef0
#define MT6328_AUXADC_VISMPS0_4 0x0ef2
#define MT6328_AUXADC_VISMPS0_5 0x0ef4
#define MT6328_AUXADC_VISMPS0_6 0x0ef6
#define MT6328_AUXADC_VISMPS0_7 0x0ef8
#define MT6328_AUXADC_LBAT2_1 0x0efa
#define MT6328_AUXADC_LBAT2_2 0x0efc
#define MT6328_AUXADC_LBAT2_3 0x0efe
#define MT6328_AUXADC_LBAT2_4 0x0f00
#define MT6328_AUXADC_LBAT2_5 0x0f02
#define MT6328_AUXADC_LBAT2_6 0x0f04
#define MT6328_AUXADC_LBAT2_7 0x0f06
#define MT6328_AUXADC_MDBG_0 0x0f08
#define MT6328_AUXADC_MDBG_1 0x0f0a
#define MT6328_AUXADC_MDBG_2 0x0f0c
#define MT6328_AUXADC_MDRT_0 0x0f0e
#define MT6328_AUXADC_MDRT_1 0x0f10
#define MT6328_AUXADC_MDRT_2 0x0f12
#define MT6328_ACCDET_CON0 0x0f14
#define MT6328_ACCDET_CON1 0x0f16
#define MT6328_ACCDET_CON2 0x0f18
#define MT6328_ACCDET_CON3 0x0f1a
#define MT6328_ACCDET_CON4 0x0f1c
#define MT6328_ACCDET_CON5 0x0f1e
#define MT6328_ACCDET_CON6 0x0f20
#define MT6328_ACCDET_CON7 0x0f22
#define MT6328_ACCDET_CON8 0x0f24
#define MT6328_ACCDET_CON9 0x0f26
#define MT6328_ACCDET_CON10 0x0f28
#define MT6328_ACCDET_CON11 0x0f2a
#define MT6328_ACCDET_CON12 0x0f2c
#define MT6328_ACCDET_CON13 0x0f2e
#define MT6328_ACCDET_CON14 0x0f30
#define MT6328_ACCDET_CON15 0x0f32
#define MT6328_ACCDET_CON16 0x0f34
#define MT6328_ACCDET_CON17 0x0f36
#define MT6328_ACCDET_CON18 0x0f38
#define MT6328_ACCDET_CON19 0x0f3a
#define MT6328_ACCDET_CON20 0x0f3c
#define MT6328_ACCDET_CON21 0x0f3e
#define MT6328_ACCDET_CON22 0x0f40
#define MT6328_ACCDET_CON23 0x0f42
#define MT6328_ACCDET_CON24 0x0f44
#define MT6328_ACCDET_CON25 0x0f46
#define MT6328_CHR_CON0 0x0f48
#define MT6328_CHR_CON1 0x0f4a
#define MT6328_CHR_CON2 0x0f4c
#define MT6328_CHR_CON3 0x0f4e
#define MT6328_CHR_CON4 0x0f50
#define MT6328_CHR_CON5 0x0f52
#define MT6328_CHR_CON6 0x0f54
#define MT6328_CHR_CON7 0x0f56
#define MT6328_CHR_CON8 0x0f58
#define MT6328_CHR_CON9 0x0f5a
#define MT6328_CHR_CON10 0x0f5c
#define MT6328_CHR_CON11 0x0f5e
#define MT6328_CHR_CON12 0x0f60
#define MT6328_CHR_CON13 0x0f62
#define MT6328_CHR_CON14 0x0f64
#define MT6328_CHR_CON15 0x0f66
#define MT6328_CHR_CON16 0x0f68
#define MT6328_CHR_CON17 0x0f6a
#define MT6328_CHR_CON18 0x0f6c
#define MT6328_CHR_CON19 0x0f6e
#define MT6328_CHR_CON20 0x0f70
#define MT6328_CHR_CON21 0x0f72
#define MT6328_CHR_CON22 0x0f74
#define MT6328_CHR_CON23 0x0f76
#define MT6328_CHR_CON24 0x0f78
#define MT6328_CHR_CON25 0x0f7a
#define MT6328_CHR_CON26 0x0f7c
#define MT6328_CHR_CON27 0x0f7e
#define MT6328_CHR_CON28 0x0f80
#define MT6328_CHR_CON29 0x0f82
#define MT6328_CHR_CON30 0x0f84
#define MT6328_CHR_CON31 0x0f86
#define MT6328_CHR_CON32 0x0f88
#define MT6328_CHR_CON33 0x0f8a
#define MT6328_CHR_CON34 0x0f8c
#define MT6328_CHR_CON35 0x0f8e
#define MT6328_CHR_CON36 0x0f90
#define MT6328_CHR_CON37 0x0f92
#define MT6328_CHR_CON38 0x0f94
#define MT6328_CHR_CON39 0x0f96
#define MT6328_CHR_CON40 0x0f98
#define MT6328_CHR_CON41 0x0f9a
#define MT6328_CHR_CON42 0x0f9c
#define MT6328_BATON_CON0 0x0f9e
#define MT6328_CHR_CON43 0x0fa0
#define MT6328_EOSC_CALI_CON0 0x0faa
#define MT6328_EOSC_CALI_CON1 0x0fac
#define MT6328_VRTC_PWM_CON0 0x0fae
#endif /* __MFD_MT6328_REGISTERS_H__ */

11
include/linux/mfd/mt6397/core.h
View File

@ -12,6 +12,7 @@
enum chip_id {
MT6323_CHIP_ID = 0x23,
MT6328_CHIP_ID = 0x30,
MT6331_CHIP_ID = 0x20,
MT6332_CHIP_ID = 0x20,
MT6357_CHIP_ID = 0x57,
@ -65,11 +66,11 @@ struct mt6397_chip {
int irq;
struct irq_domain *irq_domain;
struct mutex irqlock;
u16 wake_mask[2];
u16 irq_masks_cur[2];
u16 irq_masks_cache[2];
u16 int_con[2];
u16 int_status[2];
u16 wake_mask[3];
u16 irq_masks_cur[3];
u16 irq_masks_cache[3];
u16 int_con[3];
u16 int_status[3];
u16 chip_id;
void *irq_data;
};

4
include/linux/mfd/palmas.h
View File

@ -98,8 +98,8 @@ struct palmas_sleep_requestor_info {
};
struct palmas_regs_info {
char *name;
char *sname;
const char *name;
const char *sname;
u8 vsel_addr;
u8 ctrl_addr;
u8 tstep_addr;

1
include/linux/mfd/samsung/core.h
View File

@ -37,6 +37,7 @@ struct gpio_desc;
enum sec_device_type {
S5M8767X,
S2DOS05,
S2MPA01,
S2MPS11X,
S2MPS13X,

32
include/linux/platform_data/cros_ec_commands.h
View File

@ -1312,6 +1312,38 @@ enum ec_feature_code {
* The EC supports the AP composing VDMs for us to send.
*/
EC_FEATURE_TYPEC_AP_VDM_SEND = 46,
/*
* The EC supports system safe mode panic recovery.
*/
EC_FEATURE_SYSTEM_SAFE_MODE = 47,
/*
* The EC will reboot on runtime assertion failures.
*/
EC_FEATURE_ASSERT_REBOOTS = 48,
/*
* The EC image is built with tokenized logging enabled.
*/
EC_FEATURE_TOKENIZED_LOGGING = 49,
/*
* The EC supports triggering an STB dump.
*/
EC_FEATURE_AMD_STB_DUMP = 50,
/*
* The EC supports memory dump commands.
*/
EC_FEATURE_MEMORY_DUMP = 51,
/*
* The EC supports DP2.1 capability
*/
EC_FEATURE_TYPEC_DP2_1 = 52,
/*
* The MCU is System Companion Processor Core 1
*/
EC_FEATURE_SCP_C1 = 53,
/*
* The EC supports UCSI PPM.
*/
EC_FEATURE_UCSI_PPM = 54,
};
#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)

42
sound/soc/codecs/cs42l43.c
View File

@ -2402,49 +2402,7 @@ static int cs42l43_codec_runtime_resume(struct device *dev)
return 0;
}
static int cs42l43_codec_suspend(struct device *dev)
{
struct cs42l43_codec *priv = dev_get_drvdata(dev);
struct cs42l43 *cs42l43 = priv->core;
disable_irq(cs42l43->irq);
return 0;
}
static int cs42l43_codec_suspend_noirq(struct device *dev)
{
struct cs42l43_codec *priv = dev_get_drvdata(dev);
struct cs42l43 *cs42l43 = priv->core;
enable_irq(cs42l43->irq);
return 0;
}
static int cs42l43_codec_resume(struct device *dev)
{
struct cs42l43_codec *priv = dev_get_drvdata(dev);
struct cs42l43 *cs42l43 = priv->core;
enable_irq(cs42l43->irq);
return 0;
}
static int cs42l43_codec_resume_noirq(struct device *dev)
{
struct cs42l43_codec *priv = dev_get_drvdata(dev);
struct cs42l43 *cs42l43 = priv->core;
disable_irq(cs42l43->irq);
return 0;
}
static const struct dev_pm_ops cs42l43_codec_pm_ops = {
SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume)
NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend_noirq, cs42l43_codec_resume_noirq)
RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL)
};