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x86/amd-iommu: Use 2-level page tables for dma_ops domains

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The driver now supports a dynamic number of levels for IO
page tables. This allows to reduce the number of levels for
dma_ops domains by one because a dma_ops domain has usually
an address space size between 128MB and 4G.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Joerg Roedel 2009-09-02 16:55:24 +02:00
parent bad1cac28a
commit 8f7a017ce0
1 changed files with 1 additions and 1 deletions
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2
arch/x86/kernel/amd_iommu.c
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@ -1010,7 +1010,7 @@ static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
dma_dom->domain.id = domain_id_alloc(); dma_dom->domain.id = domain_id_alloc();
if (dma_dom->domain.id == 0) if (dma_dom->domain.id == 0)
goto free_dma_dom; goto free_dma_dom;
dma_dom->domain.mode = PAGE_MODE_3_LEVEL; dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
dma_dom->domain.flags = PD_DMA_OPS_MASK; dma_dom->domain.flags = PD_DMA_OPS_MASK;
dma_dom->domain.priv = dma_dom; dma_dom->domain.priv = dma_dom;