Kernel/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2025-01-01 02:36:02 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Pin control bulk changes for the v5.19 series:

Browse Source 
Core changes:
 
 - New helpers from Andy such as for_each_gpiochip_node() affecting both
   GPIO and pin control, improving a bunch of drivers in the process.
 
 - Pulled in Marc Zyngiers work to make IRQ chips immutable, and started
   to apply fixups on top.
 
 New drivers:
 
 - New driver for Marvell MVEBU 98DX2530.
 
 - New driver for Mediatek MT8195.
 
 - Support Qualcomm PMX65 and PM6125.
 
 - New driver for Qualcomm SC7280 LPASS pin control.
 
 - New driver for Rockchip RK3588.
 
 - New driver for NXP Freescale i.MXRT1170.
 
 - New driver for Mediatek MT6795 Helio X10.
 
 Improvements:
 
 - Several Aspeed G6 cleanups and non-critical fixes.
 
 - Thorought refactoring of some of the ever improving Renesas drivers.
 
 - Clean up Mediatek MT8192 bindings a bit.
 
 - PWM output and clock monitoring in the Ocelot LAN966x driver.
 
 - Thorough refactoring and cleanup of the Ralink drivers such as
   RT2880, RT3883, RT305X, MT7620, MT7621, MT7628 splitting these into proper
   sub-drivers.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmKR6skACgkQQRCzN7AZ
 XXMpAg/+JXKTooNIuxsfXO2SSQouGJP3xIa0iLdhEKahN8vM7Rp4ND3vuqOI7eqp
 pQrGVqY2BiRDhFTz6cku5dBK9tQUlHB9fqr0XHZ65W5pVjz2FCMIE5RemlyNhPMf
 OMv4BfJA3Mk71nqmcWjTAc+l7Iw1HAdGrQ4QJpfCHT/eGZCGZXS6q7/iNKyNlnpK
 iN7CuJn4YxB8EyAxySEFIi1R/CP1nA1Hmeq1ICxLbFrG/NFZoFjKX1a4xJi4ns7/
 3Sn3Vq9t5hJLbU3VZsQymNlCNqzKTtLcSugUlNzkXzvLKebbh27ZVrjWs7pye/s5
 Bqbg0e9oDJkAnw8+/tgXKh88hz6ZdUWRVWJElkfp+LyFBuIitGWcaHOEhhaEEHIZ
 Utrvba8hjq2r7ASw3gvMWFVHhrQYGBONDkAQGXLtKKFHoNfXf6O5BOmyc0gsYdBo
 Sx6X/lAahZkvV17dDop9AlOquf3+jExUHZNftLouazzxqJ1xoDVkbiRz3iKf29n0
 +F7hpt0M01jQxUS6whOv9jdR+jAplds35ess99Wput8R5X8ICZRhEtdj4ON10lM/
 pI9biaoNXtglCHc2J+nm9EXzD0DePjs/ULCs/0C6FLZ4I5BfZ8dkwe7QNW/cM2vA
 V1YTeLVujQASmJo+pfWACoE1nbOg/no1sY1foUKeYnjfhS+OuZg=
 =e5GM
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Pretty big this time. Mostly due to (nice) Renesas refactorings.

  Core changes:

   - New helpers from Andy such as for_each_gpiochip_node() affecting
     both GPIO and pin control, improving a bunch of drivers in the
     process.

   - Pulled in Marc Zyngiers work to make IRQ chips immutable, and
     started to apply fixups on top.

  New drivers:

   - New driver for Marvell MVEBU 98DX2530.

   - New driver for Mediatek MT8195.

   - Support Qualcomm PMX65 and PM6125.

   - New driver for Qualcomm SC7280 LPASS pin control.

   - New driver for Rockchip RK3588.

   - New driver for NXP Freescale i.MXRT1170.

   - New driver for Mediatek MT6795 Helio X10.

  Improvements:

   - Several Aspeed G6 cleanups and non-critical fixes.

   - Thorought refactoring of some of the ever improving Renesas
     drivers.

   - Clean up Mediatek MT8192 bindings a bit.

   - PWM output and clock monitoring in the Ocelot LAN966x driver.

   - Thorough refactoring and cleanup of the Ralink drivers such as
     RT2880, RT3883, RT305X, MT7620, MT7621, MT7628 splitting these into
     proper sub-drivers"

* tag 'pinctrl-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (161 commits)
  pinctrl: apple: Use a raw spinlock for the regmap
  pinctrl: berlin: bg4ct: Use devm_platform_*ioremap_resource() APIs
  pinctrl: intel: Fix kernel doc format, i.e. add return sections
  dt-bindings: pinctrl: qcom: Drop 'maxItems' on 'wakeup-parent'
  pinctrl: starfive: Make the irqchip immutable
  pinctrl: mediatek: Add pinctrl driver for MT6795 Helio X10
  dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings
  pinctrl: freescale: Add i.MXRT1170 pinctrl driver support
  dt-bindings: pinctrl: add i.MXRT1170 pinctrl Documentation
  dt-bindings: pinctrl: rockchip: increase max amount of device functions
  dt-bindings: pinctrl: qcom,pmic-gpio: add 'gpio-reserved-ranges'
  dt-bindings: pinctrl: qcom,pmic-gpio: add 'input-disable'
  dt-bindings: pinctrl: qcom,pmic-gpio: describe gpio-line-names
  dt-bindings: pinctrl: qcom,pmic-gpio: fix matching pin config
  dt-bindings: pinctrl: qcom,pmic-gpio: document PM8150L and PMM8155AU
  pinctrl: qcom: spmi-gpio: Add pm6125 compatible
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm6125 compatible
  pinctrl: intel: Drop unused irqchip member in struct intel_pinctrl
  pinctrl: intel: make irq_chip immutable
  pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask()
  ...
This commit is contained in:
Linus Torvalds 2022-05-28 11:15:54 -07:00
commit 907bb57aa7
129 changed files with 9107 additions and 4203 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
View File

@ -22,6 +22,7 @@ Properties:
- "qcom,sc7280-pdc": For SC7280
- "qcom,sdm845-pdc": For SDM845
- "qcom,sm6350-pdc": For SM6350
- "qcom,sm8150-pdc": For SM8150
- "qcom,sm8250-pdc": For SM8250
- "qcom,sm8350-pdc": For SM8350

77
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View File

@ -76,73 +76,24 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
scu@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#clock-cells = <1>;
#reset-cells = <1>;
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx>, <&lhc>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx>, <&lhc>;
pinctrl_i2c3_default: i2c3_default {
function = "I2C3";
groups = "I2C3";
};
pinctrl_gpioh0_unbiased_default: gpioh0 {
pins = "A18";
bias-disable;
};
pinctrl_i2c3_default: i2c3_default {
function = "I2C3";
groups = "I2C3";
};
};
gfx: display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
reg-io-width = <4>;
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
resets = <&syscon ASPEED_RESET_CRT1>;
interrupts = <0x19>;
syscon = <&syscon>;
memory-region = <&gfx_memory>;
};
};
lpc: lpc@1e789000 {
compatible = "aspeed,ast2500-lpc", "simple-mfd";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
lpc_host: lpc-host@80 {
compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
reg = <0x80 0x1e0>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24>, <0x48 0x8>;
pinctrl_gpioh0_unbiased_default: gpioh0 {
pins = "A18";
bias-disable;
};
};
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};

87
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
View File

@ -1,87 +0,0 @@
* Freescale i.MX7 Dual IOMUX Controller
iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
power state retention capabilities on gpios that are part of iomuxc-lpsr
(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
mux and pad control settings, it shares the input select register from main
iomuxc controller for daisy chain settings, the fsl,input-sel property extends
fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
};
Peripherals using pads from iomuxc-lpsr support low state retention power
state, under LPSR mode GPIO's state of pads are retain.
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
"fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
Reference Manual for detailed CONFIG settings.
- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
a phandle for main iomuxc controller which shares the input select register for
daisy chain settings.
CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
PAD_CTL_PUS_5K_UP (1 << 5)
PAD_CTL_PUS_47K_UP (2 << 5)
PAD_CTL_PUS_100K_UP (3 << 5)
PAD_CTL_PUE (1 << 4)
PAD_CTL_HYS (1 << 3)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_FAST (0 << 2)
PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X4 (1 << 0)
PAD_CTL_DSE_X2 (2 << 0)
PAD_CTL_DSE_X6 (3 << 0)
Examples:
While iomuxc-lpsr is intended to be used by dedicated peripherals to take
advantages of LPSR power mode, is also possible that an IP to use pads from
any of the iomux controllers. For example the I2C1 IP can use SCL pad from
iomuxc-lpsr controller and SDA pad from iomuxc controller as:
i2c1: i2c@30a20000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>, <&pinctrl_i2c1_2>;
};
iomuxc-lpsr@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
>;
};
};
iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
>;
};
};

113
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml Normal file
View File

@ -0,0 +1,113 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX7D IOMUX Controller
maintainers:
- Dong Aisheng <aisheng.dong@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
oneOf:
- enum:
- fsl,imx7d-iomuxc
- fsl,imx7d-iomuxc-lpsr
reg:
maxItems: 1
fsl,input-sel:
description:
phandle for main iomuxc controller which shares the input select
register for daisy chain settings.
$ref: /schemas/types.yaml#/definitions/phandle
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm/boot/dts/imx7d-pinfunc.h>. The last integer
CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX7D Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_reg" indicates the offset of mux register.
- description: |
"conf_reg" indicates the offset of pad configuration register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_val" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
if:
properties:
compatible:
contains:
enum:
- fsl,imx7d-iomuxc-lpsr
then:
required:
- fsl,input-sel
additionalProperties: false
examples:
- |
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
pinctrl_uart5: uart5grp {
fsl,pins =
<0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
<0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
};
};
- |
iomuxc_lpsr: pinctrl@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
pinctrl_gpio_lpsr: gpio1-grp {
fsl,pins =
<0x0008 0x0038 0x0000 0x0 0x0 0x59>,
<0x000C 0x003C 0x0000 0x0 0x0 0x59>;
};
};

77
Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml Normal file
View File

@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MXRT1170 IOMUX Controller
maintainers:
- Giulio Benetti <giulio.benetti@benettiengineering.com>
- Jesse Taube <Mr.Bossman075@gmail.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
const: fsl,imxrt1170-iomuxc
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MXRT1170 Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_reg" indicates the offset of mux register.
- description: |
"conf_reg" indicates the offset of pad configuration register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_val" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
iomuxc: iomuxc@400e8000 {
compatible = "fsl,imxrt1170-iomuxc";
reg = <0x400e8000 0x4000>;
pinctrl_lpuart1: lpuart1grp {
fsl,pins =
<0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
<0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
};
};

72
Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/marvell,ac5-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell AC5 pin controller
maintainers:
- Chris Packham <chris.packham@alliedtelesis.co.nz>
description:
Bindings for Marvell's AC5 memory-mapped pin controller.
properties:
compatible:
items:
- const: marvell,ac5-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
marvell,function:
$ref: "/schemas/types.yaml#/definitions/string"
description:
Indicates the function to select.
enum: [ dev_init_done, ge, gpio, i2c0, i2c1, int_out, led, nand, pcie, ptp, sdio,
spi0, spi1, synce, tsen_int, uart0, uart1, uart2, uart3, uartsd, wd_int, xg ]
marvell,pins:
$ref: /schemas/types.yaml#/definitions/string-array
description:
Array of MPP pins to be used for the given function.
minItems: 1
items:
enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9,
mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19,
mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, mpp28, mpp29,
mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, mpp37, mpp38, mpp39,
mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ]
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@80020100 {
compatible = "marvell,ac5-pinctrl";
reg = <0x80020100 0x20>;
i2c0_pins: i2c0-pins {
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c0";
};
i2c0_gpio: i2c0-gpio-pins {
marvell,pins = "mpp26", "mpp27";
marvell,function = "gpio";
};
};

224
Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml Normal file
View File

@ -0,0 +1,224 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT6795 Pin Controller
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Sean Wang <sean.wang@kernel.org>
description: |
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt6795-pinctrl
gpio-controller: true
'#gpio-cells':
description: |
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
const: 2
gpio-ranges:
description: GPIO valid number range.
maxItems: 1
reg:
description:
Physical address base for gpio base and eint registers.
minItems: 2
reg-names:
items:
- const: base
- const: eint
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
An example of using macro:
pincontroller {
/* GPIO0 set as multifunction GPIO0 */
gpio-pins {
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
}
};
/* GPIO45 set as multifunction SDA0 */
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
}
};
};
$ref: "pinmux-node.yaml"
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
directly.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt6795 pull down PUPD/R0/R1 type define value.
description: |
For normal pull down type, it is not necessary to specify R1R0
values; When pull down type is PUPD/R0/R1, adding R1R0 defines
will set different resistance values.
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt6795 pull up PUPD/R0/R1 type define value.
description: |
For normal pull up type, it is not necessary to specify R1R0
values; When pull up type is PUPD/R0/R1, adding R1R0 defines
will set different resistance values.
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
required:
- pinmux
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt6795-pinctrl";
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
reg-names = "base", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 196>;
interrupt-controller;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0-pins {
pins-sda-scl {
pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
<PINMUX_GPIO46__FUNC_SCL0>;
};
};
mmc0-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
};
};
};

42
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
View File

@ -1,42 +0,0 @@
Microsemi Ocelot pin controller Device Tree Bindings
----------------------------------------------------
Required properties:
- compatible : Should be "mscc,ocelot-pinctrl",
"mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
"mscc,luton-pinctrl", "mscc,serval-pinctrl",
"microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
- reg : Address and length of the register set for the device
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Must be 2.
The first cell is the pin number and the
second cell specifies GPIO flags, as defined in
<dt-bindings/gpio/gpio.h>.
- gpio-ranges : Range of pins managed by the GPIO controller.
The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
configuration documented in pinctrl-bindings.txt.
The following generic properties are supported:
- function
- pins
Example:
gpio: pinctrl@71070034 {
compatible = "mscc,ocelot-pinctrl";
reg = <0x71070034 0x28>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
};

116
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml Normal file
View File

@ -0,0 +1,116 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microsemi Ocelot pin controller
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- Lars Povlsen <lars.povlsen@microchip.com>
properties:
compatible:
enum:
- microchip,lan966x-pinctrl
- microchip,sparx5-pinctrl
- mscc,jaguar2-pinctrl
- mscc,luton-pinctrl
- mscc,ocelot-pinctrl
- mscc,serval-pinctrl
- mscc,servalt-pinctrl
reg:
items:
- description: Base address
- description: Extended pin configuration registers
minItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
resets:
maxItems: 1
reset-names:
description: Optional shared switch reset.
items:
- const: switch
patternProperties:
'-pins$':
type: object
allOf:
- $ref: "pinmux-node.yaml"
- $ref: "pincfg-node.yaml"
properties:
function: true
pins: true
output-high: true
output-low: true
drive-strength: true
required:
- function
- pins
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
allOf:
- $ref: "pinctrl.yaml#"
- if:
properties:
compatible:
contains:
enum:
- microchip,lan966x-pinctrl
- microchip,sparx5-pinctrl
then:
properties:
reg:
minItems: 2
additionalProperties: false
examples:
- |
gpio: pinctrl@71070034 {
compatible = "mscc,ocelot-pinctrl";
reg = <0x71070034 0x28>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
};
...

155
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
View File

@ -29,6 +29,8 @@ properties:
description: gpio valid number range.
maxItems: 1
gpio-line-names: true
reg:
description: |
Physical address base for gpio base registers. There are 11 GPIO
@ -51,62 +53,92 @@ properties:
#PIN CONFIGURATION NODES
patternProperties:
'^pins':
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
An example of using macro:
pincontroller {
/* GPIO0 set as multifunction GPIO0 */
state_0_node_a {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
};
/* GPIO1 set as multifunction PWM */
state_0_node_b {
pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
};
};
$ref: "pinmux-node.yaml"
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
description: |
It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
patternProperties:
'^pins':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
$ref: "pinmux-node.yaml"
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
description: |
It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
mediatek,pull-up-adv:
description: |
Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
@ -151,8 +183,17 @@ examples:
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
output-low;
spi1-default-pins {
pins-cs-mosi-clk {
pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
bias-disable;
};
pins-miso {
pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
bias-pull-down;
};
};
};

287
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -20,6 +20,7 @@ properties:
- qcom,pm2250-gpio
- qcom,pm660-gpio
- qcom,pm660l-gpio
- qcom,pm6125-gpio
- qcom,pm6150-gpio
- qcom,pm6150l-gpio
- qcom,pm6350-gpio
@ -32,6 +33,7 @@ properties:
- qcom,pm8058-gpio
- qcom,pm8150-gpio
- qcom,pm8150b-gpio
- qcom,pm8150l-gpio
- qcom,pm8226-gpio
- qcom,pm8350-gpio
- qcom,pm8350b-gpio
@ -49,10 +51,12 @@ properties:
- qcom,pmi8994-gpio
- qcom,pmi8998-gpio
- qcom,pmk8350-gpio
- qcom,pmm8155au-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
- qcom,pms405-gpio
- qcom,pmx55-gpio
- qcom,pmx65-gpio
- enum:
- qcom,spmi-gpio
@ -71,6 +75,16 @@ properties:
gpio-ranges:
maxItems: 1
gpio-line-names:
minItems: 2
maxItems: 44
gpio-reserved-ranges:
minItems: 1
# maxItems as half of total number of GPIOs, as there has to be at
# least one usable GPIO between each reserved range.
maxItems: 22
'#gpio-cells':
const: 2
description:
@ -87,13 +101,278 @@ required:
- gpio-ranges
- interrupt-controller
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8008-gpio
- qcom,pmi8950-gpio
then:
properties:
gpio-line-names:
minItems: 2
maxItems: 2
gpio-reserved-ranges:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8005-gpio
- qcom,pm8450-gpio
- qcom,pm8916-gpio
- qcom,pmk8350-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
then:
properties:
gpio-line-names:
minItems: 4
maxItems: 4
gpio-reserved-ranges:
minItems: 1
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8018-gpio
- qcom,pm8019-gpio
then:
properties:
gpio-line-names:
minItems: 6
maxItems: 6
gpio-reserved-ranges:
minItems: 1
maxItems: 3
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8350b-gpio
- qcom,pm8950-gpio
then:
properties:
gpio-line-names:
minItems: 8
maxItems: 8
gpio-reserved-ranges:
minItems: 1
maxItems: 4
- if:
properties:
compatible:
contains:
enum:
- qcom,pm6350-gpio
- qcom,pm8350c-gpio
then:
properties:
gpio-line-names:
minItems: 9
maxItems: 9
gpio-reserved-ranges:
minItems: 1
maxItems: 5
- if:
properties:
compatible:
contains:
enum:
- qcom,pm2250-gpio
- qcom,pm6150-gpio
- qcom,pm7325-gpio
- qcom,pm8150-gpio
- qcom,pm8350-gpio
- qcom,pmc8180-gpio
- qcom,pmi8994-gpio
- qcom,pmm8155au-gpio
then:
properties:
gpio-line-names:
minItems: 10
maxItems: 10
gpio-reserved-ranges:
minItems: 1
maxItems: 5
- if:
properties:
compatible:
contains:
enum:
- qcom,pmx55-gpio
then:
properties:
gpio-line-names:
minItems: 11
maxItems: 11
gpio-reserved-ranges:
minItems: 1
maxItems: 6
- if:
properties:
compatible:
contains:
enum:
- qcom,pm660l-gpio
- qcom,pm6150l-gpio
- qcom,pm8038-gpio
- qcom,pm8150b-gpio
- qcom,pm8150l-gpio
- qcom,pmc8180c-gpio
- qcom,pms405-gpio
then:
properties:
gpio-line-names:
minItems: 12
maxItems: 12
gpio-reserved-ranges:
minItems: 1
maxItems: 6
- if:
properties:
compatible:
contains:
enum:
- qcom,pm660-gpio
then:
properties:
gpio-line-names:
minItems: 13
maxItems: 13
gpio-reserved-ranges:
minItems: 1
maxItems: 7
- if:
properties:
compatible:
contains:
enum:
- qcom,pmi8998-gpio
then:
properties:
gpio-line-names:
minItems: 14
maxItems: 14
gpio-reserved-ranges:
minItems: 1
maxItems: 7
- if:
properties:
compatible:
contains:
enum:
- qcom,pmx65-gpio
then:
properties:
gpio-line-names:
minItems: 16
maxItems: 16
gpio-reserved-ranges:
minItems: 1
maxItems: 8
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8994-gpio
- qcom,pma8084-gpio
then:
properties:
gpio-line-names:
minItems: 22
maxItems: 22
gpio-reserved-ranges:
minItems: 1
maxItems: 11
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8998-gpio
then:
properties:
gpio-line-names:
minItems: 26
maxItems: 26
gpio-reserved-ranges:
minItems: 1
maxItems: 13
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8941-gpio
then:
properties:
gpio-line-names:
minItems: 36
maxItems: 36
gpio-reserved-ranges:
minItems: 1
maxItems: 18
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8917-gpio
then:
properties:
gpio-line-names:
minItems: 38
maxItems: 38
gpio-reserved-ranges:
minItems: 1
maxItems: 19
- if:
properties:
compatible:
contains:
enum:
- qcom,pm8058-gpio
- qcom,pm8921-gpio
then:
properties:
gpio-line-names:
minItems: 44
maxItems: 44
gpio-reserved-ranges:
minItems: 1
maxItems: 22
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-pmic-gpio-state"
- patternProperties:
".*":
"(pinconf|-pins)$":
$ref: "#/$defs/qcom-pmic-gpio-state"
additionalProperties: false
$defs:
qcom-pmic-gpio-state:
@ -106,6 +385,7 @@ $defs:
description:
List of gpio pins affected by the properties specified in
this subnode. Valid pins are
- gpio1-gpio9 for pm6125
- gpio1-gpio10 for pm6150
- gpio1-gpio12 for pm6150l
- gpio1-gpio9 for pm6350
@ -134,12 +414,14 @@ $defs:
- gpio1-gpio2 for pmi8950
- gpio1-gpio10 for pmi8994
- gpio1-gpio4 for pmk8350
- gpio1-gpio10 for pmm8155au
- gpio1-gpio4 for pmr735a
- gpio1-gpio4 for pmr735b
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9
and gpio10)
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)
- gpio1-gpio16 for pmx65
items:
pattern: "^gpio([0-9]+)$"
@ -174,6 +456,7 @@ $defs:
bias-high-impedance: true
input-enable: true
input-disable: true
output-high: true
output-low: true
output-enable: true
@ -232,7 +515,7 @@ examples:
#gpio-cells = <2>;
pm8921_gpio_keys: gpio-keys-state {
volume-keys {
volume-keys-pins {
pins = "gpio20", "gpio21";
function = "normal";

3
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
View File

@ -42,8 +42,7 @@ properties:
gpio-ranges:
maxItems: 1
wakeup-parent:
maxItems: 1
wakeup-parent: true
#PIN CONFIGURATION NODES
patternProperties:

115
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml Normal file
View File

@ -0,0 +1,115 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
Low Power Island (LPI) TLMM block
maintainers:
- Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
LPASS LPI IP on most Qualcomm SoCs
properties:
compatible:
const: qcom,sc7280-lpass-lpi-pinctrl
reg:
minItems: 2
maxItems: 2
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9])$"
minItems: 1
maxItems: 15
function:
enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
dmic3_data, i2s2_data ]
description:
Specify the alternative function to be configured for the specified
pins.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
slew-rate:
enum: [0, 1, 2, 3]
default: 0
description: |
0: No adjustments
1: Higher Slew rate (faster edges)
2: Lower Slew rate (slower edges)
3: Reserved (No adjustments)
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
lpass_tlmm: pinctrl@33c0000 {
compatible = "qcom,sc7280-lpass-lpi-pinctrl";
reg = <0x33c0000 0x20000>,
<0x3550000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;
};

3
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
View File

@ -42,8 +42,7 @@ properties:
gpio-ranges:
maxItems: 1
wakeup-parent:
maxItems: 1
wakeup-parent: true
#PIN CONFIGURATION NODES
patternProperties:

3
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml
View File

@ -49,8 +49,7 @@ properties:
gpio-ranges:
maxItems: 1
wakeup-parent:
maxItems: 1
wakeup-parent: true
#PIN CONFIGURATION NODES
patternProperties:

2
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml → Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)

3
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
View File

@ -49,8 +49,7 @@ properties:
gpio-ranges:
maxItems: 1
wakeup-parent:
maxItems: 1
wakeup-parent: true
#PIN CONFIGURATION NODES
patternProperties:

1
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
View File

@ -42,7 +42,6 @@ properties:
description:
Specifying the interrupt-controller used to wake up the system when the
TLMM block has been powered down.
maxItems: 1
gpio-reserved-ranges:
description:

91
Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml Normal file
View File

@ -0,0 +1,91 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink MT7620 Pin Controller
maintainers:
- Arınç ÜNAL <arinc.unal@arinc9.com>
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description:
Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs.
The pin controller can only set the muxing of pin groups. Muxing individual
pins is not supported. There is no pinconf support.
properties:
compatible:
const: ralink,mt7620-pinctrl
patternProperties:
'-pins$':
type: object
patternProperties:
'^(.*-)?pinmux$':
type: object
description: node for pinctrl.
$ref: pinmux-node.yaml#
properties:
groups:
description: The pin group to select.
enum: [
# For MT7620 SoC
ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, spi refclk,
uartf, uartlite, wdt, wled,
# For MT7628 and MT7688 SoCs
gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an,
p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0,
pwm1, refclk, sdmode, spi, spi cs1, spis, uart0, uart1, uart2,
wdt, wled_an, wled_kn,
]
function:
description: The mux function to select.
enum: [
# For MT7620 SoC
ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa,
pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk,
rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk,
wdt rst, wled,
# For MT7628 and MT7688 SoCs
antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn,
p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn,
p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2,
refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1,
spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -,
]
required:
- groups
- function
additionalProperties: false
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
additionalProperties: false
examples:
# Pinmux controller node
- |
pinctrl {
compatible = "ralink,mt7620-pinctrl";
i2c_pins: i2c0-pins {
pinmux {
groups = "i2c";
function = "i2c";
};
};
};

27
Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml → Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml
View File

@ -1,21 +1,23 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml#
$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink rt2880 pinmux controller
title: Ralink MT7621 Pin Controller
maintainers:
- Arınç ÜNAL <arinc.unal@arinc9.com>
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description:
The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
is not supported. There is no pinconf support.
Ralink MT7621 pin controller for MT7621 SoC.
The pin controller can only set the muxing of pin groups. Muxing individual
pins is not supported. There is no pinconf support.
properties:
compatible:
const: ralink,rt2880-pinmux
const: ralink,mt7621-pinctrl
patternProperties:
'-pins$':
@ -28,14 +30,15 @@ patternProperties:
properties:
groups:
description: Name of the pin group to use for the functions.
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
uart1, uart2, uart3, wdt]
description: The pin group to select.
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1,
uart2, uart3, wdt]
function:
description: The mux function to select
description: The mux function to select.
enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3,
spi, uart1, uart2, uart3, wdt refclk, wdt rst]
pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi,
uart1, uart2, uart3, wdt refclk, wdt rst]
required:
- groups
@ -57,7 +60,7 @@ examples:
# Pinmux controller node
- |
pinctrl {
compatible = "ralink,rt2880-pinmux";
compatible = "ralink,mt7621-pinctrl";
i2c_pins: i2c0-pins {
pinmux {

68
Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml Normal file
View File

@ -0,0 +1,68 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink RT2880 Pin Controller
maintainers:
- Arınç ÜNAL <arinc.unal@arinc9.com>
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description:
Ralink RT2880 pin controller for RT2880 SoC.
The pin controller can only set the muxing of pin groups. Muxing individual
pins is not supported. There is no pinconf support.
properties:
compatible:
const: ralink,rt2880-pinctrl
patternProperties:
'-pins$':
type: object
patternProperties:
'^(.*-)?pinmux$':
type: object
description: node for pinctrl.
$ref: pinmux-node.yaml#
properties:
groups:
description: The pin group to select.
enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
function:
description: The mux function to select.
enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
required:
- groups
- function
additionalProperties: false
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
additionalProperties: false
examples:
# Pinmux controller node
- |
pinctrl {
compatible = "ralink,rt2880-pinctrl";
i2c_pins: i2c0-pins {
pinmux {
groups = "i2c";
function = "i2c";
};
};
};

92
Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml Normal file
View File

@ -0,0 +1,92 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink RT305X Pin Controller
maintainers:
- Arınç ÜNAL <arinc.unal@arinc9.com>
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description:
Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350
SoCs.
The pin controller can only set the muxing of pin groups. Muxing individual
pins is not supported. There is no pinconf support.
properties:
compatible:
const: ralink,rt305x-pinctrl
patternProperties:
'-pins$':
type: object
patternProperties:
'^(.*-)?pinmux$':
type: object
description: node for pinctrl.
$ref: pinmux-node.yaml#
properties:
groups:
description: The pin group to select.
enum: [
# For RT3050, RT3052 and RT3350 SoCs
i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite,
# For RT3352 SoC
i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, uartf,
uartlite,
# For RT5350 SoC
i2c, jtag, led, spi, spi_cs1, uartf, uartlite,
]
function:
description: The mux function to select.
enum: [
# For RT3050, RT3052 and RT3350 SoCs
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, pcm gpio,
pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, uartlite,
# For RT3352 SoC
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, mdio,
pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf,
uartlite, wdg_cs1,
# For RT5350 SoC
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, pcm gpio,
pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, wdg_cs1,
]
required:
- groups
- function
additionalProperties: false
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
additionalProperties: false
examples:
# Pinmux controller node
- |
pinctrl {
compatible = "ralink,rt305x-pinctrl";
i2c_pins: i2c0-pins {
pinmux {
groups = "i2c";
function = "i2c";
};
};
};

71
Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml Normal file
View File

@ -0,0 +1,71 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink RT3883 Pin Controller
maintainers:
- Arınç ÜNAL <arinc.unal@arinc9.com>
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description:
Ralink RT3883 pin controller for RT3883 SoC.
The pin controller can only set the muxing of pin groups. Muxing individual
pins is not supported. There is no pinconf support.
properties:
compatible:
const: ralink,rt3883-pinctrl
patternProperties:
'-pins$':
type: object
patternProperties:
'^(.*-)?pinmux$':
type: object
description: node for pinctrl.
$ref: pinmux-node.yaml#
properties:
groups:
description: The pin group to select.
enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf,
uartlite]
function:
description: The mux function to select.
enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag,
lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2,
pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite]
required:
- groups
- function
additionalProperties: false
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
additionalProperties: false
examples:
# Pinmux controller node
- |
pinctrl {
compatible = "ralink,rt3883-pinctrl";
i2c_pins: i2c0-pins {
pinmux {
groups = "i2c";
function = "i2c";
};
};
};

5
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View File

@ -11,8 +11,8 @@ maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
controller.
The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
@ -23,6 +23,7 @@ properties:
oneOf:
- items:
- enum:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- items:

4
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
View File

@ -33,6 +33,7 @@ properties:
enum:
- rockchip,px30-pinctrl
- rockchip,rk2928-pinctrl
- rockchip,rk3036-pinctrl
- rockchip,rk3066a-pinctrl
- rockchip,rk3066b-pinctrl
- rockchip,rk3128-pinctrl
@ -44,6 +45,7 @@ properties:
- rockchip,rk3368-pinctrl
- rockchip,rk3399-pinctrl
- rockchip,rk3568-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
rockchip,grf:
@ -129,7 +131,7 @@ additionalProperties:
description:
Pin bank index.
- minimum: 0
maximum: 6
maximum: 10
description:
Mux 0 means GPIO and mux 1 to N means
the specific device function.

30
Documentation/driver-api/gpio/driver.rst
View File

@ -429,7 +429,8 @@ call into the core gpiolib code:
static void my_gpio_mask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_desc_get_handler_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
/*
* Perform any necessary action to mask the interrupt,
@ -437,14 +438,15 @@ call into the core gpiolib code:
* state.
*/
gpiochip_disable_irq(gc, d->hwirq);
gpiochip_disable_irq(gc, hwirq);
}
static void my_gpio_unmask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_desc_get_handler_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, d->hwirq);
gpiochip_enable_irq(gc, hwirq);
/*
* Perform any necessary action to unmask the interrupt,
@ -501,7 +503,8 @@ the interrupt separately and go with it:
static void my_gpio_mask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_desc_get_handler_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
/*
* Perform any necessary action to mask the interrupt,
@ -509,14 +512,15 @@ the interrupt separately and go with it:
* state.
*/
gpiochip_disable_irq(gc, d->hwirq);
gpiochip_disable_irq(gc, hwirq);
}
static void my_gpio_unmask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_desc_get_handler_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, d->hwirq);
gpiochip_enable_irq(gc, hwirq);
/*
* Perform any necessary action to unmask the interrupt,
@ -576,7 +580,8 @@ In this case the typical set-up will look like this:
static void my_gpio_mask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_desc_get_handler_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
/*
* Perform any necessary action to mask the interrupt,
@ -584,15 +589,16 @@ In this case the typical set-up will look like this:
* state.
*/
gpiochip_disable_irq(gc, d->hwirq);
gpiochip_disable_irq(gc, hwirq);
irq_mask_mask_parent(d);
}
static void my_gpio_unmask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_desc_get_handler_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, d->hwirq);
gpiochip_enable_irq(gc, hwirq);
/*
* Perform any necessary action to unmask the interrupt,

7
MAINTAINERS
View File

@ -16647,6 +16647,13 @@ L: linux-mips@vger.kernel.org
S: Maintained
F: arch/mips/boot/dts/ralink/mt7621*
RALINK PINCTRL DRIVER
M: Arınç ÜNAL <arinc.unal@arinc9.com>
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
L: linux-mips@vger.kernel.org
S: Maintained
F: drivers/pinctrl/ralink/
RALINK RT2X00 WIRELESS LAN DRIVER
M: Stanislaw Gruszka <stf_xl@wp.pl>
M: Helmut Schaa <helmut.schaa@googlemail.com>

2
arch/mips/boot/dts/ralink/mt7621.dtsi
View File

@ -151,7 +151,7 @@ spi0: spi@b00 {
};
pinctrl: pinctrl {
compatible = "ralink,rt2880-pinmux";
compatible = "ralink,mt7621-pinctrl";
i2c_pins: i2c0-pins {
pinmux {

29
drivers/gpio/gpio-rockchip.c
View File

@ -19,6 +19,7 @@
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regmap.h>
#include "../pinctrl/core.h"
@ -706,7 +707,7 @@ static int rockchip_gpio_probe(struct platform_device *pdev)
struct device_node *pctlnp = of_get_parent(np);
struct pinctrl_dev *pctldev = NULL;
struct rockchip_pin_bank *bank = NULL;
struct rockchip_pin_output_deferred *cfg;
struct rockchip_pin_deferred *cfg;
static int gpio;
int id, ret;
@ -747,15 +748,27 @@ static int rockchip_gpio_probe(struct platform_device *pdev)
return ret;
}
while (!list_empty(&bank->deferred_output)) {
cfg = list_first_entry(&bank->deferred_output,
struct rockchip_pin_output_deferred, head);
while (!list_empty(&bank->deferred_pins)) {
cfg = list_first_entry(&bank->deferred_pins,
struct rockchip_pin_deferred, head);
list_del(&cfg->head);
ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
if (ret)
dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, cfg->arg);
switch (cfg->param) {
case PIN_CONFIG_OUTPUT:
ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
if (ret)
dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
cfg->arg);
break;
case PIN_CONFIG_INPUT_ENABLE:
ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin);
if (ret)
dev_warn(dev, "setting input pin %u failed\n", cfg->pin);
break;
default:
dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
break;
}
kfree(cfg);
}

5
drivers/gpio/gpiolib-of.c
View File

@ -930,6 +930,11 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip)
if (!np)
return 0;
if (!of_property_read_bool(np, "gpio-ranges") &&
chip->of_gpio_ranges_fallback) {
return chip->of_gpio_ranges_fallback(chip, np);
}
group_names = of_find_property(np, group_names_propname, NULL);
for (;; index++) {

18
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -358,6 +358,22 @@ static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
return 0;
}
static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
struct device_node *np)
{
struct pinctrl_dev *pctldev = of_pinctrl_get(np);
of_node_put(np);
if (!pctldev)
return 0;
gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
gc->ngpio);
return 0;
}
static const struct gpio_chip bcm2835_gpio_chip = {
.label = MODULE_NAME,
.owner = THIS_MODULE,
@ -372,6 +388,7 @@ static const struct gpio_chip bcm2835_gpio_chip = {
.base = -1,
.ngpio = BCM2835_NUM_GPIOS,
.can_sleep = false,
.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
};
static const struct gpio_chip bcm2711_gpio_chip = {
@ -388,6 +405,7 @@ static const struct gpio_chip bcm2711_gpio_chip = {
.base = -1,
.ngpio = BCM2711_NUM_GPIOS,
.can_sleep = false,
.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
};
static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,

3
drivers/pinctrl/berlin/berlin-bg4ct.c
View File

@ -460,8 +460,7 @@ static int berlin4ct_pinctrl_probe(struct platform_device *pdev)
if (!rmconfig)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);

7
drivers/pinctrl/freescale/Kconfig
View File

@ -206,3 +206,10 @@ config PINCTRL_IMX23
config PINCTRL_IMX28
bool
select PINCTRL_MXS
config PINCTRL_IMXRT1170
bool "IMXRT1170 pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imxrt1170 pinctrl driver

1
drivers/pinctrl/freescale/Makefile
View File

@ -32,3 +32,4 @@ obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o
obj-$(CONFIG_PINCTRL_IMXRT1170) += pinctrl-imxrt1170.o

349
drivers/pinctrl/freescale/pinctrl-imxrt1170.c Normal file
View File

@ -0,0 +1,349 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022
* Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imxrt1170_pads {
IMXRT1170_PAD_RESERVE0,
IMXRT1170_PAD_RESERVE1,
IMXRT1170_PAD_RESERVE2,
IMXRT1170_PAD_RESERVE3,
IMXRT1170_PAD_EMC_B1_00,
IMXRT1170_PAD_EMC_B1_01,
IMXRT1170_PAD_EMC_B1_02,
IMXRT1170_PAD_EMC_B1_03,
IMXRT1170_PAD_EMC_B1_04,
IMXRT1170_PAD_EMC_B1_05,
IMXRT1170_PAD_EMC_B1_06,
IMXRT1170_PAD_EMC_B1_07,
IMXRT1170_PAD_EMC_B1_08,
IMXRT1170_PAD_EMC_B1_09,
IMXRT1170_PAD_EMC_B1_10,
IMXRT1170_PAD_EMC_B1_11,
IMXRT1170_PAD_EMC_B1_12,
IMXRT1170_PAD_EMC_B1_13,
IMXRT1170_PAD_EMC_B1_14,
IMXRT1170_PAD_EMC_B1_15,
IMXRT1170_PAD_EMC_B1_16,
IMXRT1170_PAD_EMC_B1_17,
IMXRT1170_PAD_EMC_B1_18,
IMXRT1170_PAD_EMC_B1_19,
IMXRT1170_PAD_EMC_B1_20,
IMXRT1170_PAD_EMC_B1_21,
IMXRT1170_PAD_EMC_B1_22,
IMXRT1170_PAD_EMC_B1_23,
IMXRT1170_PAD_EMC_B1_24,
IMXRT1170_PAD_EMC_B1_25,
IMXRT1170_PAD_EMC_B1_26,
IMXRT1170_PAD_EMC_B1_27,
IMXRT1170_PAD_EMC_B1_28,
IMXRT1170_PAD_EMC_B1_29,
IMXRT1170_PAD_EMC_B1_30,
IMXRT1170_PAD_EMC_B1_31,
IMXRT1170_PAD_EMC_B1_32,
IMXRT1170_PAD_EMC_B1_33,
IMXRT1170_PAD_EMC_B1_34,
IMXRT1170_PAD_EMC_B1_35,
IMXRT1170_PAD_EMC_B1_36,
IMXRT1170_PAD_EMC_B1_37,
IMXRT1170_PAD_EMC_B1_38,
IMXRT1170_PAD_EMC_B1_39,
IMXRT1170_PAD_EMC_B1_40,
IMXRT1170_PAD_EMC_B1_41,
IMXRT1170_PAD_EMC_B2_00,
IMXRT1170_PAD_EMC_B2_01,
IMXRT1170_PAD_EMC_B2_02,
IMXRT1170_PAD_EMC_B2_03,
IMXRT1170_PAD_EMC_B2_04,
IMXRT1170_PAD_EMC_B2_05,
IMXRT1170_PAD_EMC_B2_06,
IMXRT1170_PAD_EMC_B2_07,
IMXRT1170_PAD_EMC_B2_08,
IMXRT1170_PAD_EMC_B2_09,
IMXRT1170_PAD_EMC_B2_10,
IMXRT1170_PAD_EMC_B2_11,
IMXRT1170_PAD_EMC_B2_12,
IMXRT1170_PAD_EMC_B2_13,
IMXRT1170_PAD_EMC_B2_14,
IMXRT1170_PAD_EMC_B2_15,
IMXRT1170_PAD_EMC_B2_16,
IMXRT1170_PAD_EMC_B2_17,
IMXRT1170_PAD_EMC_B2_18,
IMXRT1170_PAD_EMC_B2_19,
IMXRT1170_PAD_EMC_B2_20,
IMXRT1170_PAD_AD_00,
IMXRT1170_PAD_AD_01,
IMXRT1170_PAD_AD_02,
IMXRT1170_PAD_AD_03,
IMXRT1170_PAD_AD_04,
IMXRT1170_PAD_AD_05,
IMXRT1170_PAD_AD_06,
IMXRT1170_PAD_AD_07,
IMXRT1170_PAD_AD_08,
IMXRT1170_PAD_AD_09,
IMXRT1170_PAD_AD_10,
IMXRT1170_PAD_AD_11,
IMXRT1170_PAD_AD_12,
IMXRT1170_PAD_AD_13,
IMXRT1170_PAD_AD_14,
IMXRT1170_PAD_AD_15,
IMXRT1170_PAD_AD_16,
IMXRT1170_PAD_AD_17,
IMXRT1170_PAD_AD_18,
IMXRT1170_PAD_AD_19,
IMXRT1170_PAD_AD_20,
IMXRT1170_PAD_AD_21,
IMXRT1170_PAD_AD_22,
IMXRT1170_PAD_AD_23,
IMXRT1170_PAD_AD_24,
IMXRT1170_PAD_AD_25,
IMXRT1170_PAD_AD_26,
IMXRT1170_PAD_AD_27,
IMXRT1170_PAD_AD_28,
IMXRT1170_PAD_AD_29,
IMXRT1170_PAD_AD_30,
IMXRT1170_PAD_AD_31,
IMXRT1170_PAD_AD_32,
IMXRT1170_PAD_AD_33,
IMXRT1170_PAD_AD_34,
IMXRT1170_PAD_AD_35,
IMXRT1170_PAD_SD_B1_00,
IMXRT1170_PAD_SD_B1_01,
IMXRT1170_PAD_SD_B1_02,
IMXRT1170_PAD_SD_B1_03,
IMXRT1170_PAD_SD_B1_04,
IMXRT1170_PAD_SD_B1_05,
IMXRT1170_PAD_SD_B2_00,
IMXRT1170_PAD_SD_B2_01,
IMXRT1170_PAD_SD_B2_02,
IMXRT1170_PAD_SD_B2_03,
IMXRT1170_PAD_SD_B2_04,
IMXRT1170_PAD_SD_B2_05,
IMXRT1170_PAD_SD_B2_06,
IMXRT1170_PAD_SD_B2_07,
IMXRT1170_PAD_SD_B2_08,
IMXRT1170_PAD_SD_B2_09,
IMXRT1170_PAD_SD_B2_10,
IMXRT1170_PAD_SD_B2_11,
IMXRT1170_PAD_DISP_B1_00,
IMXRT1170_PAD_DISP_B1_01,
IMXRT1170_PAD_DISP_B1_02,
IMXRT1170_PAD_DISP_B1_03,
IMXRT1170_PAD_DISP_B1_04,
IMXRT1170_PAD_DISP_B1_05,
IMXRT1170_PAD_DISP_B1_06,
IMXRT1170_PAD_DISP_B1_07,
IMXRT1170_PAD_DISP_B1_08,
IMXRT1170_PAD_DISP_B1_09,
IMXRT1170_PAD_DISP_B1_10,
IMXRT1170_PAD_DISP_B1_11,
IMXRT1170_PAD_DISP_B2_00,
IMXRT1170_PAD_DISP_B2_01,
IMXRT1170_PAD_DISP_B2_02,
IMXRT1170_PAD_DISP_B2_03,
IMXRT1170_PAD_DISP_B2_04,
IMXRT1170_PAD_DISP_B2_05,
IMXRT1170_PAD_DISP_B2_06,
IMXRT1170_PAD_DISP_B2_07,
IMXRT1170_PAD_DISP_B2_08,
IMXRT1170_PAD_DISP_B2_09,
IMXRT1170_PAD_DISP_B2_10,
IMXRT1170_PAD_DISP_B2_11,
IMXRT1170_PAD_DISP_B2_12,
IMXRT1170_PAD_DISP_B2_13,
IMXRT1170_PAD_DISP_B2_14,
IMXRT1170_PAD_DISP_B2_15,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imxrt1170_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_15),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_16),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_17),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_18),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_19),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_20),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_21),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_22),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_23),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_24),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_25),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_26),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_27),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_28),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_29),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_30),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_31),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_32),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_33),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_34),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_35),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_36),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_37),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_38),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_39),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_40),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_41),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_15),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_16),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_17),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_18),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_19),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_20),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_15),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_16),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_17),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_18),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_19),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_20),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_21),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_22),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_23),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_24),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_25),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_26),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_27),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_28),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_29),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_30),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_31),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_32),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_33),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_34),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_35),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_15),
};
static const struct imx_pinctrl_soc_info imxrt1170_pinctrl_info = {
.pins = imxrt1170_pinctrl_pads,
.npins = ARRAY_SIZE(imxrt1170_pinctrl_pads),
.gpr_compatible = "fsl,imxrt1170-iomuxc-gpr",
};
static const struct of_device_id imxrt1170_pinctrl_of_match[] = {
{ .compatible = "fsl,imxrt1170-iomuxc", .data = &imxrt1170_pinctrl_info, },
{ /* sentinel */ }
};
static int imxrt1170_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imxrt1170_pinctrl_info);
}
static struct platform_driver imxrt1170_pinctrl_driver = {
.driver = {
.name = "imxrt1170-pinctrl",
.of_match_table = of_match_ptr(imxrt1170_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imxrt1170_pinctrl_probe,
};
static int __init imxrt1170_pinctrl_init(void)
{
return platform_driver_register(&imxrt1170_pinctrl_driver);
}
arch_initcall(imxrt1170_pinctrl_init);

42
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -1350,15 +1350,15 @@ static void byt_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *vg = gpiochip_get_data(gc);
unsigned int offset = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg;
reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
if (!reg)
return;
raw_spin_lock(&byt_lock);
writel(BIT(offset % 32), reg);
writel(BIT(hwirq % 32), reg);
raw_spin_unlock(&byt_lock);
}
@ -1366,20 +1366,24 @@ static void byt_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *vg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
byt_gpio_clear_triggering(vg, hwirq);
gpiochip_disable_irq(gc, hwirq);
}
static void byt_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *vg = gpiochip_get_data(gc);
unsigned int offset = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
void __iomem *reg;
u32 value;
reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
gpiochip_enable_irq(gc, hwirq);
reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
if (!reg)
return;
@ -1412,12 +1416,13 @@ static void byt_irq_unmask(struct irq_data *d)
static int byt_irq_type(struct irq_data *d, unsigned int type)
{
struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
u32 offset = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 value;
unsigned long flags;
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *reg;
if (!reg || offset >= vg->chip.ngpio)
reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
if (!reg)
return -EINVAL;
raw_spin_lock_irqsave(&byt_lock, flags);
@ -1447,6 +1452,16 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
return 0;
}
static const struct irq_chip byt_gpio_irq_chip = {
.name = "BYT-GPIO",
.irq_ack = byt_irq_ack,
.irq_mask = byt_irq_mask,
.irq_unmask = byt_irq_unmask,
.irq_set_type = byt_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void byt_gpio_irq_handler(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
@ -1633,15 +1648,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
if (irq > 0) {
struct gpio_irq_chip *girq;
vg->irqchip.name = "BYT-GPIO",
vg->irqchip.irq_ack = byt_irq_ack,
vg->irqchip.irq_mask = byt_irq_mask,
vg->irqchip.irq_unmask = byt_irq_unmask,
vg->irqchip.irq_set_type = byt_irq_type,
vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED,
girq = &gc->irq;
girq->chip = &vg->irqchip;
gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
girq->init_hw = byt_gpio_irq_init_hw;
girq->init_valid_mask = byt_init_irq_valid_mask;
girq->parent_handler = byt_gpio_irq_handler;

1
drivers/pinctrl/intel/pinctrl-broxton.c
View File

@ -1035,4 +1035,5 @@ module_exit(bxt_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:apollolake-pinctrl");
MODULE_ALIAS("platform:broxton-pinctrl");

64
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1242,12 +1242,12 @@ static void chv_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 intr_line;
raw_spin_lock(&chv_lock);
intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
@ -1255,17 +1255,15 @@ static void chv_gpio_irq_ack(struct irq_data *d)
raw_spin_unlock(&chv_lock);
}
static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(d);
u32 value, intr_line;
unsigned long flags;
raw_spin_lock_irqsave(&chv_lock, flags);
intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
@ -1281,12 +1279,20 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
static void chv_gpio_irq_mask(struct irq_data *d)
{
chv_gpio_irq_mask_unmask(d, true);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
chv_gpio_irq_mask_unmask(gc, hwirq, true);
gpiochip_disable_irq(gc, hwirq);
}
static void chv_gpio_irq_unmask(struct irq_data *d)
{
chv_gpio_irq_mask_unmask(d, false);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, hwirq);
chv_gpio_irq_mask_unmask(gc, hwirq, false);
}
static unsigned chv_gpio_irq_startup(struct irq_data *d)
@ -1306,17 +1312,17 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
struct device *dev = pctrl->dev;
struct intel_community_context *cctx = &pctrl->context.communities[0];
unsigned int pin = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
irq_flow_handler_t handler;
unsigned long flags;
u32 intsel, value;
raw_spin_lock_irqsave(&chv_lock, flags);
intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
value = chv_readl(pctrl, pin, CHV_PADCTRL1);
value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
handler = handle_level_irq;
else
@ -1324,9 +1330,9 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
irq_set_handler_locked(d, handler);
dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n",
intsel, pin);
cctx->intr_lines[intsel] = pin;
dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n",
intsel, hwirq);
cctx->intr_lines[intsel] = hwirq;
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
@ -1392,14 +1398,14 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
unsigned int pin = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
u32 value;
int ret;
raw_spin_lock_irqsave(&chv_lock, flags);
ret = chv_gpio_set_intr_line(pctrl, pin);
ret = chv_gpio_set_intr_line(pctrl, hwirq);
if (ret)
goto out_unlock;
@ -1416,8 +1422,8 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
* 2. If the pin cfg is not locked in BIOS:
* Driver programs the IntWakeCfg bits and save the mapping.
*/
if (!chv_pad_locked(pctrl, pin)) {
value = chv_readl(pctrl, pin, CHV_PADCTRL1);
if (!chv_pad_locked(pctrl, hwirq)) {
value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
@ -1434,7 +1440,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
value |= CHV_PADCTRL1_INVRXTX_RXDATA;
}
chv_writel(pctrl, pin, CHV_PADCTRL1, value);
chv_writel(pctrl, hwirq, CHV_PADCTRL1, value);
}
if (type & IRQ_TYPE_EDGE_BOTH)
@ -1448,6 +1454,17 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
return ret;
}
static const struct irq_chip chv_gpio_irq_chip = {
.name = "chv-gpio",
.irq_startup = chv_gpio_irq_startup,
.irq_ack = chv_gpio_irq_ack,
.irq_mask = chv_gpio_irq_mask,
.irq_unmask = chv_gpio_irq_unmask,
.irq_set_type = chv_gpio_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void chv_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
@ -1611,15 +1628,8 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
chip->base = -1;
pctrl->irq = irq;
pctrl->irqchip.name = "chv-gpio";
pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
chip->irq.chip = &pctrl->irqchip;
gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip);
chip->irq.init_hw = chv_gpio_irq_init_hw;
chip->irq.parent_handler = chv_gpio_irq_handler;
chip->irq.num_parents = 1;

45
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -858,6 +858,9 @@ static const struct pinctrl_desc intel_pinctrl_desc = {
* When coming through gpiolib irqchip, the GPIO offset is not
* automatically translated to pinctrl pin number. This function can be
* used to find out the corresponding pinctrl pin.
*
* Return: a pin number and pointers to the community and pad group, which
* the pin belongs to, or negative error code if translation can't be done.
*/
static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
const struct intel_community **community,
@ -899,6 +902,8 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
* @pin: pin number
*
* Translate the pin number of pinctrl to GPIO offset
*
* Return: a GPIO offset, or negative error code if translation can't be done.
*/
static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
{
@ -1039,15 +1044,14 @@ static void intel_gpio_irq_ack(struct irq_data *d)
}
}
static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
const struct intel_community *community;
const struct intel_padgroup *padgrp;
int pin;
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
if (pin >= 0) {
unsigned int gpp, gpp_offset;
unsigned long flags;
@ -1077,12 +1081,20 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
static void intel_gpio_irq_mask(struct irq_data *d)
{
intel_gpio_irq_mask_unmask(d, true);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
intel_gpio_irq_mask_unmask(gc, hwirq, true);
gpiochip_disable_irq(gc, hwirq);
}
static void intel_gpio_irq_unmask(struct irq_data *d)
{
intel_gpio_irq_mask_unmask(d, false);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, hwirq);
intel_gpio_irq_mask_unmask(gc, hwirq, false);
}
static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
@ -1157,6 +1169,17 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
return 0;
}
static const struct irq_chip intel_gpio_irq_chip = {
.name = "intel-gpio",
.irq_ack = intel_gpio_irq_ack,
.irq_mask = intel_gpio_irq_mask,
.irq_unmask = intel_gpio_irq_unmask,
.irq_set_type = intel_gpio_irq_type,
.irq_set_wake = intel_gpio_irq_wake,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
const struct intel_community *community)
{
@ -1319,15 +1342,6 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
pctrl->irq = irq;
/* Setup IRQ chip */
pctrl->irqchip.name = dev_name(pctrl->dev);
pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
/*
* On some platforms several GPIO controllers share the same interrupt
* line.
@ -1340,8 +1354,9 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
return ret;
}
/* Setup IRQ chip */
girq = &pctrl->chip.irq;
girq->chip = &pctrl->irqchip;
gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
/* This will let us handle the IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;

2
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -223,7 +223,6 @@ struct intel_pinctrl_context {
* @pctldesc: Pin controller description
* @pctldev: Pointer to the pin controller device
* @chip: GPIO chip in this pin controller
* @irqchip: IRQ chip in this pin controller
* @soc: SoC/PCH specific pin configuration data
* @communities: All communities in this pin controller
* @ncommunities: Number of communities in this pin controller
@ -236,7 +235,6 @@ struct intel_pinctrl {
struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev;
struct gpio_chip chip;
struct irq_chip irqchip;
const struct intel_pinctrl_soc_data *soc;
struct intel_community *communities;
size_t ncommunities;

26
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@ -663,7 +663,7 @@ static void lp_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
u32 hwirq = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
unsigned long flags;
@ -684,10 +684,12 @@ static void lp_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
u32 hwirq = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
gpiochip_enable_irq(gc, hwirq);
raw_spin_lock_irqsave(&lg->lock, flags);
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
@ -697,30 +699,33 @@ static void lp_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
u32 hwirq = irqd_to_hwirq(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
gpiochip_disable_irq(gc, hwirq);
}
static int lp_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
u32 hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
void __iomem *reg;
u32 value;
if (hwirq >= lg->chip.ngpio)
reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
if (!reg)
return -EINVAL;
/* Fail if BIOS reserved pin for ACPI use */
if (lp_gpio_acpi_use(lg, hwirq)) {
dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq);
dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq);
return -EBUSY;
}
@ -755,7 +760,7 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
return 0;
}
static struct irq_chip lp_irqchip = {
static const struct irq_chip lp_irqchip = {
.name = "LP-GPIO",
.irq_ack = lp_irq_ack,
.irq_mask = lp_irq_mask,
@ -763,7 +768,8 @@ static struct irq_chip lp_irqchip = {
.irq_enable = lp_irq_enable,
.irq_disable = lp_irq_disable,
.irq_set_type = lp_irq_set_type,
.flags = IRQCHIP_SKIP_SET_WAKE,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
@ -884,7 +890,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
struct gpio_irq_chip *girq;
girq = &gc->irq;
girq->chip = &lp_irqchip;
gpio_irq_chip_set_chip(girq, &lp_irqchip);
girq->init_hw = lp_gpio_irq_init_hw;
girq->parent_handler = lp_gpio_irq_handler;
girq->num_parents = 1;

8
drivers/pinctrl/mediatek/Kconfig
View File

@ -106,6 +106,13 @@ config PINCTRL_MT6779
In MTK platform, we support virtual gpio and use it to
map specific eint which doesn't have real gpio pin.
config PINCTRL_MT6795
bool "Mediatek MT6795 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
@ -166,6 +173,7 @@ config PINCTRL_MT8195
bool "Mediatek MT8195 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8365

1
drivers/pinctrl/mediatek/Makefile
View File

@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o

623
drivers/pinctrl/mediatek/pinctrl-mt6795.c Normal file
View File

@ -0,0 +1,623 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include "pinctrl-mtk-mt6795.h"
#include "pinctrl-paris.h"
#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 15, 0)
#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 16, 0)
#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 16, 1)
static const struct mtk_pin_field_calc mt6795_pin_dir_range[] = {
PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_pullen_range[] = {
PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_pullsel_range[] = {
PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_do_range[] = {
PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_di_range[] = {
PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_mode_range[] = {
PIN_FIELD15(0, 196, 0x600, 0x10, 0, 3),
};
static const struct mtk_pin_field_calc mt6795_pin_ies_range[] = {
PINS_FIELD16(0, 4, 0x900, 0x10, 1, 1),
PINS_FIELD16(5, 9, 0x900, 0x10, 2, 1),
PINS_FIELD16(10, 15, 0x900, 0x10, 10, 1),
PINS_FIELD16(16, 16, 0x900, 0x10, 2, 1),
PINS_FIELD16(17, 19, 0x910, 0x10, 3, 1),
PINS_FIELD16(20, 22, 0x910, 0x10, 4, 1),
PINS_FIELD16(23, 26, 0xce0, 0x10, 14, 1),
PINS_FIELD16(27, 27, 0xcc0, 0x10, 14, 1),
PINS_FIELD16(28, 28, 0xcd0, 0x10, 14, 1),
PINS_FIELD16(29, 32, 0x900, 0x10, 3, 1),
PINS_FIELD16(33, 33, 0x900, 0x10, 4, 1),
PINS_FIELD16(34, 36, 0x900, 0x10, 5, 1),
PINS_FIELD16(37, 38, 0x900, 0x10, 6, 1),
PINS_FIELD16(39, 39, 0x900, 0x10, 7, 1),
PINS_FIELD16(40, 40, 0x900, 0x10, 8, 1),
PINS_FIELD16(41, 42, 0x900, 0x10, 9, 1),
PINS_FIELD16(43, 46, 0x900, 0x10, 11, 1),
PINS_FIELD16(47, 61, 0x920, 0x10, 3, 1),
PINS_FIELD16(62, 66, 0x920, 0x10, 4, 1),
PINS_FIELD16(67, 67, 0x920, 0x10, 3, 1),
PINS_FIELD16(68, 72, 0x920, 0x10, 5, 1),
PINS_FIELD16(73, 77, 0x920, 0x10, 6, 1),
PINS_FIELD16(78, 91, 0x920, 0x10, 7, 1),
PINS_FIELD16(92, 92, 0x900, 0x10, 13, 1),
PINS_FIELD16(93, 95, 0x900, 0x10, 14, 1),
PINS_FIELD16(96, 99, 0x900, 0x10, 15, 1),
PINS_FIELD16(100, 103, 0xca0, 0x10, 14, 1),
PINS_FIELD16(104, 104, 0xc80, 0x10, 14, 1),
PINS_FIELD16(105, 105, 0xc90, 0x10, 14, 1),
PINS_FIELD16(106, 107, 0x910, 0x10, 0, 1),
PINS_FIELD16(108, 112, 0x910, 0x10, 1, 1),
PINS_FIELD16(113, 116, 0x910, 0x10, 2, 1),
PINS_FIELD16(117, 118, 0x910, 0x10, 5, 1),
PINS_FIELD16(119, 124, 0x910, 0x10, 6, 1),
PINS_FIELD16(125, 126, 0x910, 0x10, 7, 1),
PINS_FIELD16(129, 129, 0x910, 0x10, 8, 1),
PINS_FIELD16(130, 131, 0x910, 0x10, 9, 1),
PINS_FIELD16(132, 135, 0x910, 0x10, 8, 1),
PINS_FIELD16(136, 137, 0x910, 0x10, 7, 1),
PINS_FIELD16(154, 161, 0xc20, 0x10, 14, 1),
PINS_FIELD16(162, 162, 0xc10, 0x10, 14, 1),
PINS_FIELD16(163, 163, 0xc00, 0x10, 14, 1),
PINS_FIELD16(164, 164, 0xd10, 0x10, 14, 1),
PINS_FIELD16(165, 165, 0xd00, 0x10, 14, 1),
PINS_FIELD16(166, 169, 0x910, 0x10, 14, 1),
PINS_FIELD16(176, 179, 0x910, 0x10, 15, 1),
PINS_FIELD16(180, 180, 0x920, 0x10, 0, 1),
PINS_FIELD16(181, 184, 0x920, 0x10, 1, 1),
PINS_FIELD16(185, 191, 0x920, 0x10, 2, 1),
PINS_FIELD16(192, 192, 0x920, 0x10, 8, 1),
PINS_FIELD16(193, 194, 0x920, 0x10, 9, 1),
PINS_FIELD16(195, 196, 0x920, 0x10, 8, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_smt_range[] = {
PINS_FIELD16(0, 4, 0x930, 0x10, 1, 1),
PINS_FIELD16(5, 9, 0x930, 0x10, 2, 1),
PINS_FIELD16(10, 15, 0x930, 0x10, 10, 1),
PINS_FIELD16(16, 16, 0x930, 0x10, 2, 1),
PINS_FIELD16(17, 19, 0x940, 0x10, 3, 1),
PINS_FIELD16(20, 22, 0x940, 0x10, 4, 1),
PINS_FIELD16(23, 26, 0xce0, 0x10, 13, 1),
PINS_FIELD16(27, 27, 0xcc0, 0x10, 13, 1),
PINS_FIELD16(28, 28, 0xcd0, 0x10, 13, 1),
PINS_FIELD16(29, 32, 0x930, 0x10, 3, 1),
PINS_FIELD16(33, 33, 0x930, 0x10, 4, 1),
PINS_FIELD16(34, 36, 0x930, 0x10, 5, 1),
PINS_FIELD16(37, 38, 0x930, 0x10, 6, 1),
PINS_FIELD16(39, 39, 0x930, 0x10, 7, 1),
PINS_FIELD16(40, 40, 0x930, 0x10, 8, 1),
PINS_FIELD16(41, 42, 0x930, 0x10, 9, 1),
PINS_FIELD16(43, 46, 0x930, 0x10, 11, 1),
PINS_FIELD16(47, 61, 0x950, 0x10, 3, 1),
PINS_FIELD16(62, 66, 0x950, 0x10, 4, 1),
PINS_FIELD16(67, 67, 0x950, 0x10, 3, 1),
PINS_FIELD16(68, 72, 0x950, 0x10, 5, 1),
PINS_FIELD16(73, 77, 0x950, 0x10, 6, 1),
PINS_FIELD16(78, 91, 0x950, 0x10, 7, 1),
PINS_FIELD16(92, 92, 0x930, 0x10, 13, 1),
PINS_FIELD16(93, 95, 0x930, 0x10, 14, 1),
PINS_FIELD16(96, 99, 0x930, 0x10, 15, 1),
PINS_FIELD16(100, 103, 0xca0, 0x10, 13, 1),
PINS_FIELD16(104, 104, 0xc80, 0x10, 13, 1),
PINS_FIELD16(105, 105, 0xc90, 0x10, 13, 1),
PINS_FIELD16(106, 107, 0x940, 0x10, 0, 1),
PINS_FIELD16(108, 112, 0x940, 0x10, 1, 1),
PINS_FIELD16(113, 116, 0x940, 0x10, 2, 1),
PINS_FIELD16(117, 118, 0x940, 0x10, 5, 1),
PINS_FIELD16(119, 124, 0x940, 0x10, 6, 1),
PINS_FIELD16(125, 126, 0x940, 0x10, 7, 1),
PINS_FIELD16(129, 129, 0x940, 0x10, 8, 1),
PINS_FIELD16(130, 131, 0x940, 0x10, 9, 1),
PINS_FIELD16(132, 135, 0x940, 0x10, 8, 1),
PINS_FIELD16(136, 137, 0x940, 0x10, 7, 1),
PINS_FIELD16(154, 161, 0xc20, 0x10, 13, 1),
PINS_FIELD16(162, 162, 0xc10, 0x10, 13, 1),
PINS_FIELD16(163, 163, 0xc00, 0x10, 13, 1),
PINS_FIELD16(164, 164, 0xd10, 0x10, 13, 1),
PINS_FIELD16(165, 165, 0xd00, 0x10, 13, 1),
PINS_FIELD16(166, 169, 0x940, 0x10, 14, 1),
PINS_FIELD16(176, 179, 0x940, 0x10, 15, 1),
PINS_FIELD16(180, 180, 0x950, 0x10, 0, 1),
PINS_FIELD16(181, 184, 0x950, 0x10, 1, 1),
PINS_FIELD16(185, 191, 0x950, 0x10, 2, 1),
PINS_FIELD16(192, 192, 0x950, 0x10, 8, 1),
PINS_FIELD16(193, 194, 0x950, 0x10, 9, 1),
PINS_FIELD16(195, 196, 0x950, 0x10, 8, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_pupd_range[] = {
/* KROW */
PIN_FIELD16(119, 119, 0xe00, 0x10, 2, 1), /* KROW0 */
PIN_FIELD16(120, 120, 0xe00, 0x10, 6, 1), /* KROW1 */
PIN_FIELD16(121, 121, 0xe00, 0x10, 10, 1), /* KROW2 */
PIN_FIELD16(122, 122, 0xe10, 0x10, 2, 1), /* KCOL0 */
PIN_FIELD16(123, 123, 0xe10, 0x10, 6, 1), /* KCOL1 */
PIN_FIELD16(124, 124, 0xe10, 0x10, 10, 1), /* KCOL2 */
/* DPI */
PIN_FIELD16(138, 138, 0xd50, 0x10, 2, 1), /* CK */
PIN_FIELD16(139, 139, 0xd60, 0x10, 1, 1), /* DE */
PIN_FIELD16(140, 140, 0xd70, 0x10, 1, 1), /* data0 */
PIN_FIELD16(141, 141, 0xd70, 0x10, 3, 1), /* data1 */
PIN_FIELD16(142, 142, 0xd70, 0x10, 5, 1), /* data2 */
PIN_FIELD16(143, 143, 0xd70, 0x10, 7, 1), /* data3 */
PIN_FIELD16(144, 144, 0xd50, 0x10, 5, 1), /* data4 */
PIN_FIELD16(145, 145, 0xd50, 0x10, 7, 1), /* data5 */
PIN_FIELD16(146, 146, 0xd60, 0x10, 7, 1), /* data6 */
PIN_FIELD16(147, 147, 0xed0, 0x10, 6, 1), /* data7 */
PIN_FIELD16(148, 148, 0xed0, 0x10, 8, 1), /* data8 */
PIN_FIELD16(149, 149, 0xed0, 0x10, 10, 1), /* data9 */
PIN_FIELD16(150, 150, 0xed0, 0x10, 12, 1), /* data10 */
PIN_FIELD16(151, 151, 0xed0, 0x10, 14, 1), /* data11 */
PIN_FIELD16(152, 152, 0xd60, 0x10, 3, 1), /* hsync */
PIN_FIELD16(153, 153, 0xd60, 0x10, 5, 1), /* vsync */
/* MSDC0 */
PIN_FIELD16(154, 154, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(155, 155, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(156, 156, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(157, 157, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(158, 158, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(159, 159, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(160, 160, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(161, 161, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(162, 162, 0xc10, 0x10, 2, 1), /* CMD */
PIN_FIELD16(163, 163, 0xc00, 0x10, 2, 1), /* CLK */
PIN_FIELD16(164, 164, 0xd10, 0x10, 2, 1), /* DS */
PIN_FIELD16(165, 165, 0xd00, 0x10, 2, 1), /* RST */
/* MSDC1 */
PIN_FIELD16(170, 170, 0xc50, 0x10, 2, 1), /* CMD */
PIN_FIELD16(171, 171, 0xd20, 0x10, 2, 1), /* DAT0 */
PIN_FIELD16(172, 172, 0xd20, 0x10, 6, 1), /* DAT1 */
PIN_FIELD16(173, 173, 0xd20, 0x10, 10, 1), /* DAT2 */
PIN_FIELD16(174, 174, 0xd20, 0x10, 14, 1), /* DAT3 */
PIN_FIELD16(175, 175, 0xc40, 0x10, 2, 1), /* CLK */
/* MSDC2 */
PIN_FIELD16(100, 100, 0xd30, 0x10, 2, 1), /* DAT0 */
PIN_FIELD16(101, 101, 0xd30, 0x10, 6, 1), /* DAT1 */
PIN_FIELD16(102, 102, 0xd30, 0x10, 10, 1), /* DAT2 */
PIN_FIELD16(103, 103, 0xd30, 0x10, 14, 1), /* DAT3 */
PIN_FIELD16(104, 104, 0xc80, 0x10, 2, 1), /* CLK */
PIN_FIELD16(105, 105, 0xc90, 0x10, 2, 1), /* CMD */
/* MSDC3 */
PIN_FIELD16(23, 23, 0xd40, 0x10, 2, 1), /* DAT0 */
PIN_FIELD16(24, 24, 0xd40, 0x10, 6, 5), /* DAT1 */
PIN_FIELD16(25, 25, 0xd40, 0x10, 10, 9), /* DAT2 */
PIN_FIELD16(26, 26, 0xd40, 0x10, 14, 13), /* DAT3 */
PIN_FIELD16(27, 27, 0xcc0, 0x10, 2, 1), /* CLK */
PIN_FIELD16(28, 28, 0xcd0, 0x10, 2, 1) /* CMD */
};
static const struct mtk_pin_field_calc mt6795_pin_r0_range[] = {
PIN_FIELD16(23, 23, 0xd40, 0x10, 0, 1),
PIN_FIELD16(24, 24, 0xd40, 0x10, 4, 1),
PIN_FIELD16(25, 25, 0xd40, 0x10, 8, 1),
PIN_FIELD16(26, 26, 0xd40, 0x10, 12, 1),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 0, 1),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 0, 1),
PIN_FIELD16(100, 100, 0xd30, 0x10, 0, 1),
PIN_FIELD16(101, 101, 0xd30, 0x10, 4, 1),
PIN_FIELD16(102, 102, 0xd30, 0x10, 8, 1),
PIN_FIELD16(103, 103, 0xd30, 0x10, 12, 1),
PIN_FIELD16(104, 104, 0xc80, 0x10, 0, 1),
PIN_FIELD16(105, 105, 0xc90, 0x10, 0, 1),
PIN_FIELD16(119, 119, 0xe00, 0x10, 0, 1),
PIN_FIELD16(120, 120, 0xe00, 0x10, 4, 1),
PIN_FIELD16(121, 121, 0xe00, 0x10, 8, 1),
PIN_FIELD16(122, 122, 0xe10, 0x10, 0, 1),
PIN_FIELD16(123, 123, 0xe10, 0x10, 4, 1),
PIN_FIELD16(124, 124, 0xe10, 0x10, 8, 1),
PIN_FIELD16(138, 138, 0xd50, 0x10, 0, 1),
PIN_FIELD16(139, 139, 0xd60, 0x10, 0, 1),
PIN_FIELD16(140, 140, 0xd70, 0x10, 0, 1),
PIN_FIELD16(141, 141, 0xd70, 0x10, 1, 1),
PIN_FIELD16(142, 142, 0xd70, 0x10, 3, 1),
PIN_FIELD16(143, 143, 0xd70, 0x10, 5, 1),
PIN_FIELD16(144, 144, 0xd50, 0x10, 3, 1),
PIN_FIELD16(145, 145, 0xd50, 0x10, 5, 1),
PIN_FIELD16(146, 146, 0xd60, 0x10, 5, 1),
PIN_FIELD16(147, 147, 0xed0, 0x10, 4, 1),
PIN_FIELD16(148, 148, 0xed0, 0x10, 6, 1),
PIN_FIELD16(149, 149, 0xed0, 0x10, 8, 1),
PIN_FIELD16(150, 150, 0xed0, 0x10, 10, 1),
PIN_FIELD16(151, 151, 0xed0, 0x10, 12, 1),
PIN_FIELD16(152, 152, 0xd60, 0x10, 1, 1),
PIN_FIELD16(153, 153, 0xd60, 0x10, 3, 1),
PIN_FIELD16(154, 155, 0xc20, 0x10, 0, 1),
PIN_FIELD16(155, 156, 0xc20, 0x10, 0, 1),
PIN_FIELD16(156, 157, 0xc20, 0x10, 0, 1),
PIN_FIELD16(157, 158, 0xc20, 0x10, 0, 1),
PIN_FIELD16(158, 159, 0xc20, 0x10, 0, 1),
PIN_FIELD16(159, 160, 0xc20, 0x10, 0, 1),
PIN_FIELD16(160, 161, 0xc20, 0x10, 0, 1),
PIN_FIELD16(161, 161, 0xc20, 0x10, 0, 1),
PIN_FIELD16(162, 162, 0xc10, 0x10, 0, 1),
PIN_FIELD16(163, 163, 0xc00, 0x10, 0, 1),
PIN_FIELD16(164, 164, 0xd10, 0x10, 0, 1),
PIN_FIELD16(165, 165, 0xd00, 0x10, 0, 1),
PIN_FIELD16(170, 170, 0xc50, 0x10, 0, 1),
PIN_FIELD16(171, 171, 0xd20, 0x10, 0, 1),
PIN_FIELD16(172, 172, 0xd20, 0x10, 4, 1),
PIN_FIELD16(173, 173, 0xd20, 0x10, 8, 1),
PIN_FIELD16(174, 174, 0xd20, 0x10, 12, 1),
PIN_FIELD16(175, 175, 0xc40, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_r1_range[] = {
PIN_FIELD16(23, 23, 0xd40, 0x10, 1, 1),
PIN_FIELD16(24, 24, 0xd40, 0x10, 5, 1),
PIN_FIELD16(25, 25, 0xd40, 0x10, 9, 1),
PIN_FIELD16(26, 26, 0xd40, 0x10, 13, 1),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 1, 1),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 1, 1),
PIN_FIELD16(100, 100, 0xd30, 0x10, 1, 1),
PIN_FIELD16(101, 101, 0xd30, 0x10, 5, 1),
PIN_FIELD16(102, 102, 0xd30, 0x10, 9, 1),
PIN_FIELD16(103, 103, 0xd30, 0x10, 13, 1),
PIN_FIELD16(104, 104, 0xc80, 0x10, 1, 1),
PIN_FIELD16(105, 105, 0xc90, 0x10, 1, 1),
PIN_FIELD16(119, 119, 0xe00, 0x10, 1, 1),
PIN_FIELD16(120, 120, 0xe00, 0x10, 5, 1),
PIN_FIELD16(121, 121, 0xe00, 0x10, 9, 1),
PIN_FIELD16(122, 122, 0xe10, 0x10, 1, 1),
PIN_FIELD16(123, 123, 0xe10, 0x10, 5, 1),
PIN_FIELD16(124, 124, 0xe10, 0x10, 9, 1),
PIN_FIELD16(138, 138, 0xd50, 0x10, 1, 1),
PIN_FIELD16(139, 139, 0xd60, 0x10, 0, 1),
PIN_FIELD16(140, 140, 0xd70, 0x10, 0, 1),
PIN_FIELD16(141, 141, 0xd70, 0x10, 2, 1),
PIN_FIELD16(142, 142, 0xd70, 0x10, 4, 1),
PIN_FIELD16(143, 143, 0xd70, 0x10, 6, 1),
PIN_FIELD16(144, 144, 0xd50, 0x10, 4, 1),
PIN_FIELD16(145, 145, 0xd50, 0x10, 6, 1),
PIN_FIELD16(146, 146, 0xd60, 0x10, 6, 1),
PIN_FIELD16(147, 147, 0xed0, 0x10, 5, 1),
PIN_FIELD16(148, 148, 0xed0, 0x10, 7, 1),
PIN_FIELD16(149, 149, 0xed0, 0x10, 9, 1),
PIN_FIELD16(150, 150, 0xed0, 0x10, 11, 1),
PIN_FIELD16(151, 151, 0xed0, 0x10, 13, 1),
PIN_FIELD16(152, 152, 0xd60, 0x10, 2, 1),
PIN_FIELD16(153, 153, 0xd60, 0x10, 4, 1),
PIN_FIELD16(154, 155, 0xc20, 0x10, 1, 1),
PIN_FIELD16(155, 156, 0xc20, 0x10, 1, 1),
PIN_FIELD16(156, 157, 0xc20, 0x10, 1, 1),
PIN_FIELD16(157, 158, 0xc20, 0x10, 1, 1),
PIN_FIELD16(158, 159, 0xc20, 0x10, 1, 1),
PIN_FIELD16(159, 160, 0xc20, 0x10, 1, 1),
PIN_FIELD16(160, 161, 0xc20, 0x10, 1, 1),
PIN_FIELD16(161, 161, 0xc20, 0x10, 1, 1),
PIN_FIELD16(162, 162, 0xc10, 0x10, 1, 1),
PIN_FIELD16(163, 163, 0xc00, 0x10, 1, 1),
PIN_FIELD16(164, 164, 0xd10, 0x10, 1, 1),
PIN_FIELD16(165, 165, 0xd00, 0x10, 1, 1),
PIN_FIELD16(170, 170, 0xc50, 0x10, 1, 1),
PIN_FIELD16(171, 171, 0xd20, 0x10, 1, 1),
PIN_FIELD16(172, 172, 0xd20, 0x10, 5, 1),
PIN_FIELD16(173, 173, 0xd20, 0x10, 9, 1),
PIN_FIELD16(174, 174, 0xd20, 0x10, 13, 1),
PIN_FIELD16(175, 175, 0xc40, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_drv_range[] = {
PINS_FIELD16(0, 4, 0xb30, 0x10, 13, 2),
PINS_FIELD16(5, 9, 0xb30, 0x10, 1, 2),
PINS_FIELD16(10, 15, 0xb30, 0x10, 5, 2),
PIN_FIELD16(16, 16, 0xb30, 0x10, 1, 2),
PINS_FIELD16(17, 19, 0xb70, 0x10, 5, 2),
PINS_FIELD16(20, 22, 0xb70, 0x10, 9, 2),
PINS_FIELD16(23, 26, 0xce0, 0x10, 8, 2),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 8, 2),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 8, 2),
PINS_FIELD16(29, 32, 0xb80, 0x10, 13, 2),
PIN_FIELD16(33, 33, 0xb10, 0x10, 13, 2),
PINS_FIELD16(34, 36, 0xb10, 0x10, 9, 2),
PINS_FIELD16(37, 38, 0xb10, 0x10, 5, 2),
PIN_FIELD16(39, 39, 0xb20, 0x10, 1, 2),
PIN_FIELD16(40, 40, 0xb20, 0x10, 5, 2),
PINS_FIELD16(41, 42, 0xb20, 0x10, 9, 2),
PINS_FIELD16(47, 61, 0xb00, 0x10, 9, 2),
PINS_FIELD16(62, 66, 0xb70, 0x10, 1, 2),
PINS_FIELD16(67, 67, 0xb00, 0x10, 9, 2),
PINS_FIELD16(68, 72, 0xb60, 0x10, 13, 2),
PINS_FIELD16(73, 77, 0xb40, 0x10, 13, 2),
PIN_FIELD16(78, 78, 0xb00, 0x10, 12, 3),
PINS_FIELD16(79, 91, 0xb00, 0x10, 13, 2),
PIN_FIELD16(92, 92, 0xb60, 0x10, 5, 2),
PINS_FIELD16(93, 95, 0xb60, 0x10, 1, 2),
PINS_FIELD16(96, 99, 0xb80, 0x10, 9, 2),
PINS_FIELD16(100, 103, 0xca0, 0x10, 8, 2),
PIN_FIELD16(104, 104, 0xc80, 0x10, 8, 2),
PIN_FIELD16(105, 105, 0xc90, 0x10, 8, 2),
PINS_FIELD16(106, 107, 0xb50, 0x10, 9, 2),
PINS_FIELD16(108, 112, 0xb50, 0x10, 1, 2),
PINS_FIELD16(113, 116, 0xb80, 0x10, 5, 2),
PINS_FIELD16(117, 118, 0xb90, 0x10, 1, 2),
PINS_FIELD16(119, 124, 0xb50, 0x10, 5, 2),
PIN_FIELD16(127, 127, 0xb70, 0x10, 5, 2),
PIN_FIELD16(128, 128, 0xb70, 0x10, 9, 2),
PIN_FIELD16(129, 129, 0xb40, 0x10, 9, 2),
PINS_FIELD16(130, 131, 0xb40, 0x10, 13, 2),
PINS_FIELD16(132, 135, 0xb40, 0x10, 9, 2),
PIN_FIELD16(138, 138, 0xb50, 0x10, 8, 2),
PIN_FIELD16(139, 139, 0xb60, 0x10, 8, 2),
PINS_FIELD16(140, 151, 0xb70, 0x10, 8, 2),
PINS_FIELD16(152, 153, 0xb60, 0x10, 8, 2),
PINS_FIELD16(153, 153, 0xb60, 0x10, 8, 2),
PINS_FIELD16(154, 161, 0xc20, 0x10, 8, 2),
PIN_FIELD16(162, 162, 0xc10, 0x10, 8, 2),
PIN_FIELD16(163, 163, 0xc00, 0x10, 8, 2),
PIN_FIELD16(164, 164, 0xd10, 0x10, 8, 2),
PIN_FIELD16(165, 165, 0xd00, 0x10, 8, 2),
PINS_FIELD16(166, 169, 0xb80, 0x10, 1, 2),
PINS_FIELD16(170, 173, 0xc60, 0x10, 8, 2),
PIN_FIELD16(174, 174, 0xc40, 0x10, 8, 2),
PIN_FIELD16(175, 175, 0xc50, 0x10, 8, 2),
PINS_FIELD16(176, 179, 0xb70, 0x10, 13, 2),
PIN_FIELD16(180, 180, 0xb00, 0x10, 5, 2),
PINS_FIELD16(181, 184, 0xb00, 0x10, 1, 2),
PINS_FIELD16(185, 191, 0xb60, 0x10, 9, 2),
PIN_FIELD16(192, 192, 0xb40, 0x10, 1, 2),
PINS_FIELD16(193, 194, 0xb40, 0x10, 5, 2),
PINS_FIELD16(195, 196, 0xb40, 0x10, 1, 2),
};
static const struct mtk_pin_field_calc mt6795_pin_sr_range[] = {
PINS_FIELD16(0, 4, 0xb30, 0x10, 15, 1),
PINS_FIELD16(5, 9, 0xb30, 0x10, 3, 1),
PINS_FIELD16(10, 15, 0xb30, 0x10, 7, 1),
PIN_FIELD16(16, 16, 0xb30, 0x10, 5, 1),
PINS_FIELD16(23, 26, 0xce0, 0x10, 12, 1),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 12, 1),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 12, 1),
PINS_FIELD16(29, 32, 0xb80, 0x10, 15, 1),
PIN_FIELD16(33, 33, 0xb10, 0x10, 15, 1),
PINS_FIELD16(34, 36, 0xb10, 0x10, 11, 1),
PINS_FIELD16(37, 38, 0xb10, 0x10, 7, 1),
PIN_FIELD16(39, 39, 0xb20, 0x10, 3, 1),
PIN_FIELD16(40, 40, 0xb20, 0x10, 7, 1),
PINS_FIELD16(41, 42, 0xb20, 0x10, 11, 1),
PINS_FIELD16(47, 61, 0xb00, 0x10, 11, 1),
PINS_FIELD16(62, 66, 0xb70, 0x10, 3, 1),
PINS_FIELD16(67, 67, 0xb00, 0x10, 11, 1),
PINS_FIELD16(68, 72, 0xb60, 0x10, 15, 1),
PINS_FIELD16(73, 77, 0xb40, 0x10, 15, 1),
PIN_FIELD16(78, 78, 0xb00, 0x10, 15, 3),
PINS_FIELD16(79, 91, 0xb00, 0x10, 15, 1),
PIN_FIELD16(92, 92, 0xb60, 0x10, 7, 1),
PINS_FIELD16(93, 95, 0xb60, 0x10, 3, 1),
PINS_FIELD16(96, 99, 0xb80, 0x10, 11, 1),
PINS_FIELD16(100, 103, 0xca0, 0x10, 12, 1),
PIN_FIELD16(104, 104, 0xc80, 0x10, 12, 1),
PIN_FIELD16(105, 105, 0xc90, 0x10, 12, 1),
PINS_FIELD16(106, 107, 0xb50, 0x10, 11, 1),
PINS_FIELD16(108, 112, 0xb50, 0x10, 3, 1),
PINS_FIELD16(113, 116, 0xb80, 0x10, 7, 1),
PINS_FIELD16(117, 118, 0xb90, 0x10, 3, 1),
PINS_FIELD16(119, 124, 0xb50, 0x10, 7, 1),
PIN_FIELD16(127, 127, 0xb70, 0x10, 7, 1),
PIN_FIELD16(128, 128, 0xb70, 0x10, 11, 1),
PIN_FIELD16(129, 129, 0xb40, 0x10, 11, 1),
PINS_FIELD16(130, 131, 0xb40, 0x10, 15, 1),
PINS_FIELD16(132, 135, 0xb40, 0x10, 11, 1),
PIN_FIELD16(138, 138, 0xb50, 0x10, 12, 1),
PIN_FIELD16(139, 139, 0xb60, 0x10, 12, 1),
PINS_FIELD16(140, 151, 0xb70, 0x10, 12, 1),
PINS_FIELD16(152, 153, 0xb60, 0x10, 12, 1),
PINS_FIELD16(153, 153, 0xb60, 0x10, 12, 1),
PINS_FIELD16(154, 161, 0xc20, 0x10, 12, 1),
PIN_FIELD16(162, 162, 0xc10, 0x10, 12, 1),
PIN_FIELD16(163, 163, 0xc00, 0x10, 12, 1),
PIN_FIELD16(164, 164, 0xd10, 0x10, 12, 1),
PIN_FIELD16(165, 165, 0xd00, 0x10, 12, 1),
PINS_FIELD16(166, 169, 0xb80, 0x10, 3, 1),
PINS_FIELD16(170, 173, 0xc60, 0x10, 12, 1),
PIN_FIELD16(174, 174, 0xc40, 0x10, 12, 1),
PIN_FIELD16(175, 175, 0xc50, 0x10, 12, 1),
PINS_FIELD16(176, 179, 0xb70, 0x10, 15, 1),
PIN_FIELD16(180, 180, 0xb00, 0x10, 7, 1),
PINS_FIELD16(181, 184, 0xb00, 0x10, 3, 1),
PINS_FIELD16(185, 191, 0xb60, 0x10, 11, 1),
PIN_FIELD16(192, 192, 0xb40, 0x10, 3, 1),
PINS_FIELD16(193, 194, 0xb40, 0x10, 7, 1),
PINS_FIELD16(195, 196, 0xb40, 0x10, 3, 1),
};
static const struct mtk_pin_reg_calc mt6795_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6795_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6795_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6795_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6795_pin_do_range),
[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6795_pin_sr_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6795_pin_smt_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6795_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6795_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6795_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6795_pin_r1_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6795_pin_ies_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6795_pin_pullen_range),
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6795_pin_pullsel_range),
};
static const struct mtk_eint_hw mt6795_eint_hw = {
.port_mask = 7,
.ports = 7,
.ap_num = 224,
.db_cnt = 32,
};
static const unsigned int mt6795_pull_type[] = {
MTK_PULL_PULLSEL_TYPE,/*0*/ MTK_PULL_PULLSEL_TYPE,/*1*/
MTK_PULL_PULLSEL_TYPE,/*2*/ MTK_PULL_PULLSEL_TYPE,/*3*/
MTK_PULL_PULLSEL_TYPE,/*4*/ MTK_PULL_PULLSEL_TYPE,/*5*/
MTK_PULL_PULLSEL_TYPE,/*6*/ MTK_PULL_PULLSEL_TYPE,/*7*/
MTK_PULL_PULLSEL_TYPE,/*8*/ MTK_PULL_PULLSEL_TYPE,/*9*/
MTK_PULL_PULLSEL_TYPE,/*10*/ MTK_PULL_PULLSEL_TYPE,/*11*/
MTK_PULL_PULLSEL_TYPE,/*12*/ MTK_PULL_PULLSEL_TYPE,/*13*/
MTK_PULL_PULLSEL_TYPE,/*14*/ MTK_PULL_PULLSEL_TYPE,/*15*/
MTK_PULL_PULLSEL_TYPE,/*16*/ MTK_PULL_PULLSEL_TYPE,/*17*/
MTK_PULL_PULLSEL_TYPE,/*18*/ MTK_PULL_PULLSEL_TYPE,/*19*/
MTK_PULL_PULLSEL_TYPE,/*20*/ MTK_PULL_PULLSEL_TYPE,/*21*/
MTK_PULL_PULLSEL_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PULLSEL_TYPE,/*29*/
MTK_PULL_PULLSEL_TYPE,/*30*/ MTK_PULL_PULLSEL_TYPE,/*31*/
MTK_PULL_PULLSEL_TYPE,/*32*/ MTK_PULL_PULLSEL_TYPE,/*33*/
MTK_PULL_PULLSEL_TYPE,/*34*/ MTK_PULL_PULLSEL_TYPE,/*35*/
MTK_PULL_PULLSEL_TYPE,/*36*/ MTK_PULL_PULLSEL_TYPE,/*37*/
MTK_PULL_PULLSEL_TYPE,/*38*/ MTK_PULL_PULLSEL_TYPE,/*39*/
MTK_PULL_PULLSEL_TYPE,/*40*/ MTK_PULL_PULLSEL_TYPE,/*41*/
MTK_PULL_PULLSEL_TYPE,/*42*/ MTK_PULL_PULLSEL_TYPE,/*43*/
MTK_PULL_PULLSEL_TYPE,/*44*/ MTK_PULL_PULLSEL_TYPE,/*45*/
MTK_PULL_PULLSEL_TYPE,/*46*/ MTK_PULL_PULLSEL_TYPE,/*47*/
MTK_PULL_PULLSEL_TYPE,/*48*/ MTK_PULL_PULLSEL_TYPE,/*49*/
MTK_PULL_PULLSEL_TYPE,/*50*/ MTK_PULL_PULLSEL_TYPE,/*51*/
MTK_PULL_PULLSEL_TYPE,/*52*/ MTK_PULL_PULLSEL_TYPE,/*53*/
MTK_PULL_PULLSEL_TYPE,/*54*/ MTK_PULL_PULLSEL_TYPE,/*55*/
MTK_PULL_PULLSEL_TYPE,/*56*/ MTK_PULL_PULLSEL_TYPE,/*57*/
MTK_PULL_PULLSEL_TYPE,/*58*/ MTK_PULL_PULLSEL_TYPE,/*59*/
MTK_PULL_PULLSEL_TYPE,/*60*/ MTK_PULL_PULLSEL_TYPE,/*61*/
MTK_PULL_PULLSEL_TYPE,/*62*/ MTK_PULL_PULLSEL_TYPE,/*63*/
MTK_PULL_PULLSEL_TYPE,/*64*/ MTK_PULL_PULLSEL_TYPE,/*65*/
MTK_PULL_PULLSEL_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/
MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/
MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/
MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PULLSEL_TYPE,/*83*/
MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/
MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/
MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/
MTK_PULL_PULLSEL_TYPE,/*90*/ MTK_PULL_PULLSEL_TYPE,/*91*/
MTK_PULL_PULLSEL_TYPE,/*92*/ MTK_PULL_PULLSEL_TYPE,/*93*/
MTK_PULL_PULLSEL_TYPE,/*94*/ MTK_PULL_PULLSEL_TYPE,/*95*/
MTK_PULL_PULLSEL_TYPE,/*96*/ MTK_PULL_PULLSEL_TYPE,/*97*/
MTK_PULL_PULLSEL_TYPE,/*98*/ MTK_PULL_PULLSEL_TYPE,/*99*/
MTK_PULL_PUPD_R1R0_TYPE,/*100*/ MTK_PULL_PUPD_R1R0_TYPE,/*101*/
MTK_PULL_PUPD_R1R0_TYPE,/*102*/ MTK_PULL_PUPD_R1R0_TYPE,/*103*/
MTK_PULL_PUPD_R1R0_TYPE,/*104*/ MTK_PULL_PUPD_R1R0_TYPE,/*105*/
MTK_PULL_PULLSEL_TYPE,/*106*/ MTK_PULL_PULLSEL_TYPE,/*107*/
MTK_PULL_PULLSEL_TYPE,/*108*/ MTK_PULL_PULLSEL_TYPE,/*109*/
MTK_PULL_PULLSEL_TYPE,/*110*/ MTK_PULL_PULLSEL_TYPE,/*111*/
MTK_PULL_PULLSEL_TYPE,/*112*/ MTK_PULL_PULLSEL_TYPE,/*113*/
MTK_PULL_PULLSEL_TYPE,/*114*/ MTK_PULL_PULLSEL_TYPE,/*115*/
MTK_PULL_PULLSEL_TYPE,/*116*/ MTK_PULL_PULLSEL_TYPE,/*117*/
MTK_PULL_PULLSEL_TYPE,/*118*/ MTK_PULL_PUPD_R1R0_TYPE,/*119*/
MTK_PULL_PUPD_R1R0_TYPE,/*120*/ MTK_PULL_PUPD_R1R0_TYPE,/*121*/
MTK_PULL_PUPD_R1R0_TYPE,/*122*/ MTK_PULL_PUPD_R1R0_TYPE,/*123*/
MTK_PULL_PUPD_R1R0_TYPE,/*124*/ MTK_PULL_PULLSEL_TYPE,/*125*/
MTK_PULL_PULLSEL_TYPE,/*126*/ MTK_PULL_PULLSEL_TYPE,/*127*/
MTK_PULL_PULLSEL_TYPE,/*128*/ MTK_PULL_PULLSEL_TYPE,/*129*/
MTK_PULL_PULLSEL_TYPE,/*130*/ MTK_PULL_PULLSEL_TYPE,/*131*/
MTK_PULL_PULLSEL_TYPE,/*132*/ MTK_PULL_PULLSEL_TYPE,/*133*/
MTK_PULL_PULLSEL_TYPE,/*134*/ MTK_PULL_PULLSEL_TYPE,/*135*/
MTK_PULL_PULLSEL_TYPE,/*136*/ MTK_PULL_PULLSEL_TYPE,/*137*/
MTK_PULL_PUPD_R1R0_TYPE,/*138*/ MTK_PULL_PUPD_R1R0_TYPE,/*139*/
MTK_PULL_PUPD_R1R0_TYPE,/*140*/ MTK_PULL_PUPD_R1R0_TYPE,/*141*/
MTK_PULL_PUPD_R1R0_TYPE,/*142*/ MTK_PULL_PUPD_R1R0_TYPE,/*143*/
MTK_PULL_PUPD_R1R0_TYPE,/*144*/ MTK_PULL_PUPD_R1R0_TYPE,/*145*/
MTK_PULL_PUPD_R1R0_TYPE,/*146*/ MTK_PULL_PUPD_R1R0_TYPE,/*147*/
MTK_PULL_PUPD_R1R0_TYPE,/*148*/ MTK_PULL_PUPD_R1R0_TYPE,/*149*/
MTK_PULL_PUPD_R1R0_TYPE,/*150*/ MTK_PULL_PUPD_R1R0_TYPE,/*151*/
MTK_PULL_PUPD_R1R0_TYPE,/*152*/ MTK_PULL_PUPD_R1R0_TYPE,/*153*/
MTK_PULL_PUPD_R1R0_TYPE,/*154*/ MTK_PULL_PUPD_R1R0_TYPE,/*155*/
MTK_PULL_PUPD_R1R0_TYPE,/*156*/ MTK_PULL_PUPD_R1R0_TYPE,/*157*/
MTK_PULL_PUPD_R1R0_TYPE,/*158*/ MTK_PULL_PUPD_R1R0_TYPE,/*159*/
MTK_PULL_PUPD_R1R0_TYPE,/*160*/ MTK_PULL_PUPD_R1R0_TYPE,/*161*/
MTK_PULL_PUPD_R1R0_TYPE,/*162*/ MTK_PULL_PUPD_R1R0_TYPE,/*163*/
MTK_PULL_PUPD_R1R0_TYPE,/*164*/ MTK_PULL_PUPD_R1R0_TYPE,/*165*/
MTK_PULL_PULLSEL_TYPE,/*166*/ MTK_PULL_PULLSEL_TYPE,/*167*/
MTK_PULL_PULLSEL_TYPE,/*168*/ MTK_PULL_PULLSEL_TYPE,/*169*/
MTK_PULL_PUPD_R1R0_TYPE,/*170*/ MTK_PULL_PUPD_R1R0_TYPE,/*171*/
MTK_PULL_PUPD_R1R0_TYPE,/*172*/ MTK_PULL_PUPD_R1R0_TYPE,/*173*/
MTK_PULL_PUPD_R1R0_TYPE,/*174*/ MTK_PULL_PUPD_R1R0_TYPE,/*175*/
MTK_PULL_PULLSEL_TYPE,/*176*/ MTK_PULL_PULLSEL_TYPE,/*177*/
MTK_PULL_PULLSEL_TYPE,/*178*/ MTK_PULL_PULLSEL_TYPE,/*179*/
MTK_PULL_PULLSEL_TYPE,/*180*/ MTK_PULL_PULLSEL_TYPE,/*181*/
MTK_PULL_PULLSEL_TYPE,/*182*/ MTK_PULL_PULLSEL_TYPE,/*183*/
MTK_PULL_PULLSEL_TYPE,/*184*/ MTK_PULL_PULLSEL_TYPE,/*185*/
MTK_PULL_PULLSEL_TYPE,/*186*/ MTK_PULL_PULLSEL_TYPE,/*187*/
MTK_PULL_PULLSEL_TYPE,/*188*/ MTK_PULL_PULLSEL_TYPE,/*189*/
MTK_PULL_PULLSEL_TYPE,/*190*/ MTK_PULL_PULLSEL_TYPE,/*191*/
MTK_PULL_PULLSEL_TYPE,/*192*/ MTK_PULL_PULLSEL_TYPE,/*193*/
MTK_PULL_PULLSEL_TYPE,/*194*/ MTK_PULL_PULLSEL_TYPE,/*195*/
MTK_PULL_PULLSEL_TYPE,/*196*/
};
static const struct mtk_pin_soc mt6795_data = {
.reg_cal = mt6795_reg_cals,
.pins = mtk_pins_mt6795,
.npins = ARRAY_SIZE(mtk_pins_mt6795),
.ngrps = ARRAY_SIZE(mtk_pins_mt6795),
.nfuncs = 8,
.eint_hw = &mt6795_eint_hw,
.gpio_m = 0,
.base_names = mtk_default_register_base_names,
.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.pull_type = mt6795_pull_type,
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
.bias_get = mtk_pinconf_bias_get_rev1,
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
};
static const struct of_device_id mt6795_pctrl_match[] = {
{ .compatible = "mediatek,mt6795-pinctrl", .data = &mt6795_data },
{ }
};
static struct platform_driver mt6795_pinctrl_driver = {
.driver = {
.name = "mt6795-pinctrl",
.of_match_table = mt6795_pctrl_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mt6795_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);

1698
drivers/pinctrl/mediatek/pinctrl-mtk-mt6795.h Normal file
View File

File diff suppressed because it is too large Load Diff

3
drivers/pinctrl/meson/pinctrl-meson-s4.c
View File

@ -575,6 +575,7 @@ static struct meson_pmx_group meson_s4_periphs_groups[] = {
GROUP(tdm_d2_c, 4),
GROUP(tdm_d3_c, 4),
GROUP(tdm_fs1_c, 4),
GROUP(tdm_sclk1_c, 4),
GROUP(mclk_1_c, 4),
GROUP(tdm_d4_c, 4),
GROUP(tdm_d5_c, 4),
@ -936,7 +937,7 @@ static const char * const iso7816_groups[] = {
};
static const char * const tdm_groups[] = {
"tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c",
"tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c", "tdm_sclk1_c",
"tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d",
"tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h",
"tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2",

4
drivers/pinctrl/mvebu/Kconfig
View File

@ -45,6 +45,10 @@ config PINCTRL_ORION
bool
select PINCTRL_MVEBU
config PINCTRL_AC5
bool
select PINCTRL_MVEBU
config PINCTRL_ARMADA_37XX
bool
select GENERIC_PINCONF

1
drivers/pinctrl/mvebu/Makefile
View File

@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o
obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o
obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
obj-$(CONFIG_PINCTRL_AC5) += pinctrl-ac5.o

261
drivers/pinctrl/mvebu/pinctrl-ac5.c Normal file
View File

@ -0,0 +1,261 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell ac5 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2021 Marvell
*
* Noam Liron <lnoam@marvell.com>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
static struct mvebu_mpp_mode ac5_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d0"),
MPP_FUNCTION(2, "nand", "io4")),
MPP_MODE(1,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d1"),
MPP_FUNCTION(2, "nand", "io3")),
MPP_MODE(2,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d2"),
MPP_FUNCTION(2, "nand", "io2")),
MPP_MODE(3,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d3"),
MPP_FUNCTION(2, "nand", "io7")),
MPP_MODE(4,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d4"),
MPP_FUNCTION(2, "nand", "io6"),
MPP_FUNCTION(3, "uart3", "txd"),
MPP_FUNCTION(4, "uart2", "txd")),
MPP_MODE(5,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d5"),
MPP_FUNCTION(2, "nand", "io5"),
MPP_FUNCTION(3, "uart3", "rxd"),
MPP_FUNCTION(4, "uart2", "rxd")),
MPP_MODE(6,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d6"),
MPP_FUNCTION(2, "nand", "io0"),
MPP_FUNCTION(3, "i2c1", "sck")),
MPP_MODE(7,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d7"),
MPP_FUNCTION(2, "nand", "io1"),
MPP_FUNCTION(3, "i2c1", "sda")),
MPP_MODE(8,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "clk"),
MPP_FUNCTION(2, "nand", "wen")),
MPP_MODE(9,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "cmd"),
MPP_FUNCTION(2, "nand", "ale")),
MPP_MODE(10,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "ds"),
MPP_FUNCTION(2, "nand", "cle")),
MPP_MODE(11,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "rst"),
MPP_FUNCTION(2, "nand", "cen")),
MPP_MODE(12,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "clk")),
MPP_MODE(13,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "csn")),
MPP_MODE(14,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "mosi")),
MPP_MODE(15,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "miso")),
MPP_MODE(16,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "wpn"),
MPP_FUNCTION(2, "nand", "ren"),
MPP_FUNCTION(3, "uart1", "txd")),
MPP_MODE(17,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "hold"),
MPP_FUNCTION(2, "nand", "rb"),
MPP_FUNCTION(3, "uart1", "rxd")),
MPP_MODE(18,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "tsen_int", NULL),
MPP_FUNCTION(2, "uart2", "rxd"),
MPP_FUNCTION(3, "wd_int", NULL)),
MPP_MODE(19,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev_init_done", NULL),
MPP_FUNCTION(2, "uart2", "txd")),
MPP_MODE(20,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(2, "i2c1", "sck"),
MPP_FUNCTION(3, "spi1", "clk"),
MPP_FUNCTION(4, "uart3", "txd")),
MPP_MODE(21,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(2, "i2c1", "sda"),
MPP_FUNCTION(3, "spi1", "csn"),
MPP_FUNCTION(4, "uart3", "rxd")),
MPP_MODE(22,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(3, "spi1", "mosi")),
MPP_MODE(23,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(3, "spi1", "miso")),
MPP_MODE(24,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "wd_int", NULL),
MPP_FUNCTION(2, "uart2", "txd"),
MPP_FUNCTION(3, "uartsd", "txd")),
MPP_MODE(25,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "int_out", NULL),
MPP_FUNCTION(2, "uart2", "rxd"),
MPP_FUNCTION(3, "uartsd", "rxd")),
MPP_MODE(26,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "i2c0", "sck"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "uart3", "txd")),
MPP_MODE(27,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "i2c0", "sda"),
MPP_FUNCTION(2, "ptp", "pulse"),
MPP_FUNCTION(3, "uart3", "rxd")),
MPP_MODE(28,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "uart3", "txd")),
MPP_MODE(29,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "uart3", "rxd")),
MPP_MODE(30,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "ge", "mdio")),
MPP_MODE(31,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "ge", "mdio")),
MPP_MODE(32,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "uart0", "txd")),
MPP_MODE(33,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "uart0", "rxd"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "ptp", "pulse")),
MPP_MODE(34,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge", "mdio"),
MPP_FUNCTION(2, "uart3", "rxd")),
MPP_MODE(35,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge", "mdio"),
MPP_FUNCTION(2, "uart3", "txd"),
MPP_FUNCTION(3, "pcie", "rstoutn")),
MPP_MODE(36,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "clk0_tp"),
MPP_FUNCTION(2, "ptp", "clk1_tp")),
MPP_MODE(37,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "pulse_tp"),
MPP_FUNCTION(2, "wd_int", NULL)),
MPP_MODE(38,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "synce", "clk_out0")),
MPP_MODE(39,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "synce", "clk_out1")),
MPP_MODE(40,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "pclk_out0"),
MPP_FUNCTION(2, "ptp", "pclk_out1")),
MPP_MODE(41,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "ref_clk"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(4, "uart2", "txd"),
MPP_FUNCTION(5, "i2c1", "sck")),
MPP_MODE(42,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "clk0"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(4, "uart2", "rxd"),
MPP_FUNCTION(5, "i2c1", "sda")),
MPP_MODE(43,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "led", "clk")),
MPP_MODE(44,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "led", "stb")),
MPP_MODE(45,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "led", "data")),
};
static struct mvebu_pinctrl_soc_info ac5_pinctrl_info;
static const struct of_device_id ac5_pinctrl_of_match[] = {
{
.compatible = "marvell,ac5-pinctrl",
},
{ },
};
static const struct mvebu_mpp_ctrl ac5_mpp_controls[] = {
MPP_FUNC_CTRL(0, 45, NULL, mvebu_mmio_mpp_ctrl), };
static struct pinctrl_gpio_range ac5_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 46), };
static int ac5_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &ac5_pinctrl_info;
soc->variant = 0; /* no variants for ac5 */
soc->controls = ac5_mpp_controls;
soc->ncontrols = ARRAY_SIZE(ac5_mpp_controls);
soc->gpioranges = ac5_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(ac5_mpp_gpio_ranges);
soc->modes = ac5_mpp_modes;
soc->nmodes = ac5_mpp_controls[0].npins;
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver ac5_pinctrl_driver = {
.driver = {
.name = "ac5-pinctrl",
.of_match_table = of_match_ptr(ac5_pinctrl_of_match),
},
.probe = ac5_pinctrl_probe,
};
builtin_platform_driver(ac5_pinctrl_driver);

2
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View File

@ -764,7 +764,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev,
for (i = 0; i < nr_irq_parent; i++) {
int irq = irq_of_parse_and_map(np, i);
if (irq < 0)
if (!irq)
continue;
girq->parents[i] = irq;
}

7
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
View File

@ -440,6 +440,10 @@ static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
DB8500_PIN_C5 };
/* MC2 without the feedback clock */
static const unsigned mc2_a_2_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5 };
static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
DB8500_PIN_C12, DB8500_PIN_C11 };
static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
@ -699,6 +703,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc2_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
@ -856,7 +861,7 @@ DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
"lcd_d8_d11_a_1", "lcd_d12_d15_a_1", "lcd_d12_d23_a_1", "lcd_b_1",
"lcd_d16_d23_b_1");
DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_a_2", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1");
DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2_a_2", "mc2rstn_c_1");
DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");

2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -1113,6 +1113,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
spin_lock_init(&nmk_chip->lock);
chip = &nmk_chip->chip;
chip->parent = &dev->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->get_direction = nmk_gpio_get_dir;
@ -1154,7 +1155,6 @@ static int nmk_gpio_probe(struct platform_device *dev)
clk_enable(nmk_chip->clk);
nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
clk_disable(nmk_chip->clk);
chip->of_node = np;
ret = gpiochip_add_data(chip, nmk_chip);
if (ret)

4
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@ -1898,9 +1898,9 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
}
ret = irq_of_parse_and_map(np, 0);
if (ret < 0) {
if (!ret) {
dev_err(dev, "No IRQ for GPIO bank %u\n", id);
return ret;
return -EINVAL;
}
pctrl->gpio_bank[id].irq = ret;
pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;

2
drivers/pinctrl/pinctrl-apple-gpio.c
View File

@ -71,6 +71,7 @@ struct regmap_config regmap_config = {
.max_register = 512 * sizeof(u32),
.num_reg_defaults_raw = 512,
.use_relaxed_mmio = true,
.use_raw_spinlock = true,
};
/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
@ -509,6 +510,7 @@ static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
{ .compatible = "apple,pinctrl", },
{ }
};
MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match);
static struct platform_driver apple_gpio_pinctrl_driver = {
.driver = {

11
drivers/pinctrl/pinctrl-equilibrium.c
View File

@ -11,6 +11,7 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include "core.h"
#include "pinconf.h"
@ -167,11 +168,9 @@ static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
gc = &gctrl->chip;
gc->label = gctrl->name;
#if defined(CONFIG_OF_GPIO)
gc->of_node = gctrl->node;
#endif
gc->fwnode = gctrl->fwnode;
if (!of_property_read_bool(gctrl->node, "interrupt-controller")) {
if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) {
dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
gctrl->name);
return 0;
@ -209,7 +208,7 @@ static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata)
for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {
gctrl = drvdata->gpio_ctrls + i;
np = gctrl->node;
np = to_of_node(gctrl->fwnode);
gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
if (!gctrl->name)
@ -895,7 +894,7 @@ static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata)
pinbank_init(np_gpio, drvdata, banks + i, i);
gctrls[i].node = np_gpio;
gctrls[i].fwnode = of_fwnode_handle(np_gpio);
gctrls[i].bank = banks + i;
i++;
}

10
drivers/pinctrl/pinctrl-equilibrium.h
View File

@ -95,22 +95,24 @@ struct eqbr_pin_bank {
u32 aval_pinmap;
};
struct fwnode_handle;
/**
* struct eqbr_gpio_ctrl: represent a gpio controller.
* @node: device node of gpio controller.
* @chip: gpio chip.
* @fwnode: firmware node of gpio controller.
* @bank: pointer to corresponding pin bank.
* @membase: base address of the gpio controller.
* @chip: gpio chip.
* @ic: irq chip.
* @name: gpio chip name.
* @virq: irq number of the gpio chip to parent's irq domain.
* @lock: spin lock to protect gpio register write.
*/
struct eqbr_gpio_ctrl {
struct device_node *node;
struct gpio_chip chip;
struct fwnode_handle *fwnode;
struct eqbr_pin_bank *bank;
void __iomem *membase;
struct gpio_chip chip;
struct irq_chip ic;
const char *name;
unsigned int virq;

118
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -139,6 +139,30 @@ struct ingenic_gpio_chip {
unsigned int irq, reg_base;
};
static const unsigned long enabled_socs =
IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 |
IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 |
IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B |
IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 |
IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 |
IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 |
IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 |
IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 |
IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |
IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |
IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |
IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |
IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |
IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;
static bool
is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version)
{
return (enabled_socs >> version) &&
(!(enabled_socs & GENMASK(version - 1, 0))
|| jzpc->info->version >= version);
}
static const u32 jz4730_pull_ups[4] = {
0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,
};
@ -3242,7 +3266,7 @@ static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
u8 reg, u8 offset, bool set)
{
if (jzgc->jzpc->info->version == ID_JZ4730) {
if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
BIT(offset), set ? BIT(offset) : 0);
return;
@ -3300,9 +3324,9 @@ static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
u8 offset, int value)
{
if (jzgc->jzpc->info->version >= ID_JZ4770)
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
else if (jzgc->jzpc->info->version >= ID_JZ4740)
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
@ -3337,10 +3361,10 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
break;
}
if (jzgc->jzpc->info->version >= ID_JZ4770) {
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
reg1 = JZ4770_GPIO_PAT1;
reg2 = JZ4770_GPIO_PAT0;
} else if (jzgc->jzpc->info->version >= ID_JZ4740) {
} else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
reg1 = JZ4740_GPIO_TRIG;
reg2 = JZ4740_GPIO_DIR;
} else {
@ -3350,12 +3374,12 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
return;
}
if (jzgc->jzpc->info->version >= ID_X2000) {
if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
ingenic_gpio_shadow_set_bit_load(jzgc);
ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
} else if (jzgc->jzpc->info->version >= ID_X1000) {
} else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
ingenic_gpio_shadow_set_bit_load(jzgc);
@ -3371,7 +3395,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd)
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
if (jzgc->jzpc->info->version >= ID_JZ4740)
if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
@ -3383,7 +3407,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
if (jzgc->jzpc->info->version >= ID_JZ4740)
if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
@ -3395,9 +3419,9 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
if (jzgc->jzpc->info->version >= ID_JZ4770)
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
else if (jzgc->jzpc->info->version >= ID_JZ4740)
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
@ -3413,9 +3437,9 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
ingenic_gpio_irq_mask(irqd);
if (jzgc->jzpc->info->version >= ID_JZ4770)
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
else if (jzgc->jzpc->info->version >= ID_JZ4740)
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
@ -3429,7 +3453,7 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd)
bool high;
if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
(jzgc->jzpc->info->version < ID_X2000)) {
!is_soc_or_above(jzgc->jzpc, ID_X2000)) {
/*
* Switch to an interrupt for the opposite edge to the one that
* triggered the interrupt being ACKed.
@ -3441,9 +3465,9 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd)
irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
}
if (jzgc->jzpc->info->version >= ID_JZ4770)
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
else if (jzgc->jzpc->info->version >= ID_JZ4740)
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
@ -3468,7 +3492,7 @@ static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
irq_set_handler_locked(irqd, handle_bad_irq);
}
if ((type == IRQ_TYPE_EDGE_BOTH) && (jzgc->jzpc->info->version < ID_X2000)) {
if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
/*
* The hardware does not support interrupts on both edges. The
* best we can do is to set up a single-edge interrupt and then
@ -3500,9 +3524,9 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
chained_irq_enter(irq_chip, desc);
if (jzgc->jzpc->info->version >= ID_JZ4770)
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
else if (jzgc->jzpc->info->version >= ID_JZ4740)
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
else
flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
@ -3547,14 +3571,14 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
if (set) {
if (jzpc->info->version >= ID_JZ4740)
if (is_soc_or_above(jzpc, ID_JZ4740))
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_SET(reg), BIT(idx));
else
regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +
reg, BIT(idx));
} else {
if (jzpc->info->version >= ID_JZ4740)
if (is_soc_or_above(jzpc, ID_JZ4740))
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_CLEAR(reg), BIT(idx));
else
@ -3613,12 +3637,12 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
struct ingenic_pinctrl *jzpc = jzgc->jzpc;
unsigned int pin = gc->base + offset;
if (jzpc->info->version >= ID_JZ4770) {
if (is_soc_or_above(jzpc, ID_JZ4770)) {
if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
} else if (jzpc->info->version == ID_JZ4730) {
} else if (!is_soc_or_above(jzpc, ID_JZ4740)) {
if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
@ -3669,18 +3693,18 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
'A' + offt, idx, func);
if (jzpc->info->version >= ID_X1000) {
if (is_soc_or_above(jzpc, ID_X1000)) {
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
ingenic_shadow_config_pin_load(jzpc, pin);
} else if (jzpc->info->version >= ID_JZ4770) {
} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
} else if (jzpc->info->version >= ID_JZ4740) {
} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
@ -3738,16 +3762,16 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
'A' + offt, idx, input ? "in" : "out");
if (jzpc->info->version >= ID_X1000) {
if (is_soc_or_above(jzpc, ID_X1000)) {
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
ingenic_shadow_config_pin_load(jzpc, pin);
} else if (jzpc->info->version >= ID_JZ4770) {
} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
} else if (jzpc->info->version >= ID_JZ4740) {
} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
@ -3779,7 +3803,7 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int bias, reg;
bool pull, pullup, pulldown;
if (jzpc->info->version >= ID_X2000) {
if (is_soc_or_above(jzpc, ID_X2000)) {
pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
(jzpc->info->pull_ups[offt] & BIT(idx));
@ -3787,7 +3811,7 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
(jzpc->info->pull_downs[offt] & BIT(idx));
} else if (jzpc->info->version >= ID_X1830) {
} else if (is_soc_or_above(jzpc, ID_X1830)) {
unsigned int half = PINS_PER_GPIO_CHIP / 2;
unsigned int idxh = (pin % half) * 2;
@ -3804,9 +3828,9 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
} else {
if (jzpc->info->version >= ID_JZ4770)
if (is_soc_or_above(jzpc, ID_JZ4770))
pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
else if (jzpc->info->version >= ID_JZ4740)
else if (is_soc_or_above(jzpc, ID_JZ4740))
pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
else
pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);
@ -3835,9 +3859,9 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (jzpc->info->version >= ID_X2000)
if (is_soc_or_above(jzpc, ID_X2000))
reg = X2000_GPIO_SMT;
else if (jzpc->info->version >= ID_X1830)
else if (is_soc_or_above(jzpc, ID_X1830))
reg = X1830_GPIO_SMT;
else
return -EINVAL;
@ -3846,9 +3870,9 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_SLEW_RATE:
if (jzpc->info->version >= ID_X2000)
if (is_soc_or_above(jzpc, ID_X2000))
reg = X2000_GPIO_SR;
else if (jzpc->info->version >= ID_X1830)
else if (is_soc_or_above(jzpc, ID_X1830))
reg = X1830_GPIO_SR;
else
return -EINVAL;
@ -3867,7 +3891,7 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
unsigned int pin, unsigned int bias)
{
if (jzpc->info->version >= ID_X2000) {
if (is_soc_or_above(jzpc, ID_X2000)) {
switch (bias) {
case GPIO_PULL_UP:
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
@ -3885,7 +3909,7 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
}
} else if (jzpc->info->version >= ID_X1830) {
} else if (is_soc_or_above(jzpc, ID_X1830)) {
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int half = PINS_PER_GPIO_CHIP / 2;
unsigned int idxh = (pin % half) * 2;
@ -3903,9 +3927,9 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
REG_SET(X1830_GPIO_PEH), bias << idxh);
}
} else if (jzpc->info->version >= ID_JZ4770) {
} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
} else if (jzpc->info->version >= ID_JZ4740) {
} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
} else {
ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);
@ -3915,7 +3939,7 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
unsigned int pin, bool enable)
{
if (jzpc->info->version >= ID_X2000)
if (is_soc_or_above(jzpc, ID_X2000))
ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);
else
ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);
@ -3924,9 +3948,9 @@ static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
unsigned int pin, bool high)
{
if (jzpc->info->version >= ID_JZ4770)
if (is_soc_or_above(jzpc, ID_JZ4770))
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
else if (jzpc->info->version >= ID_JZ4740)
else if (is_soc_or_above(jzpc, ID_JZ4740))
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
else
ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);
@ -3935,7 +3959,7 @@ static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,
unsigned int pin, unsigned int slew)
{
if (jzpc->info->version >= ID_X2000)
if (is_soc_or_above(jzpc, ID_X2000))
ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);
else
ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);
@ -3991,7 +4015,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (jzpc->info->version < ID_X1830)
if (!is_soc_or_above(jzpc, ID_X1830))
return -EINVAL;
ingenic_set_schmitt_trigger(jzpc, pin, arg);
@ -4006,7 +4030,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_SLEW_RATE:
if (jzpc->info->version < ID_X1830)
if (!is_soc_or_above(jzpc, ID_X1830))
return -EINVAL;
ingenic_set_slew_rate(jzpc, pin, arg);

1
drivers/pinctrl/pinctrl-max77620.c
View File

@ -668,5 +668,4 @@ module_platform_driver(max77620_pinctrl_driver);
MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
MODULE_ALIAS("platform:max77620-pinctrl");
MODULE_LICENSE("GPL v2");

16
drivers/pinctrl/pinctrl-microchip-sgpio.c
View File

@ -688,11 +688,17 @@ static void microchip_sgpio_irq_setreg(struct irq_data *data,
static void microchip_sgpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
gpiochip_disable_irq(chip, data->hwirq);
}
static void microchip_sgpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
gpiochip_enable_irq(chip, data->hwirq);
microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
}
@ -746,6 +752,8 @@ static const struct irq_chip microchip_sgpio_irqchip = {
.irq_ack = microchip_sgpio_irq_ack,
.irq_unmask = microchip_sgpio_irq_unmask,
.irq_set_type = microchip_sgpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void sgpio_irq_handler(struct irq_desc *desc)
@ -840,7 +848,7 @@ static int microchip_sgpio_register_bank(struct device *dev,
gc = &bank->gpio;
gc->label = pctl_desc->name;
gc->parent = dev;
gc->of_node = to_of_node(fwnode);
gc->fwnode = fwnode;
gc->owner = THIS_MODULE;
gc->get_direction = microchip_sgpio_get_direction;
gc->direction_input = microchip_sgpio_direction_input;
@ -861,11 +869,7 @@ static int microchip_sgpio_register_bank(struct device *dev,
if (irq) {
struct gpio_irq_chip *girq = &gc->irq;
girq->chip = devm_kmemdup(dev, &microchip_sgpio_irqchip,
sizeof(microchip_sgpio_irqchip),
GFP_KERNEL);
if (!girq->chip)
return -ENOMEM;
gpio_irq_chip_set_chip(girq, &microchip_sgpio_irqchip);
girq->parent_handler = sgpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1,

22
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -19,6 +19,7 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include "core.h"
@ -60,6 +61,7 @@ enum {
FUNC_CAN0_a,
FUNC_CAN0_b,
FUNC_CAN1,
FUNC_CLKMON,
FUNC_NONE,
FUNC_FC0_a,
FUNC_FC0_b,
@ -138,6 +140,8 @@ enum {
FUNC_PTPSYNC_6,
FUNC_PTPSYNC_7,
FUNC_PWM,
FUNC_PWM_a,
FUNC_PWM_b,
FUNC_QSPI1,
FUNC_QSPI2,
FUNC_R,
@ -184,6 +188,7 @@ static const char *const ocelot_function_names[] = {
[FUNC_CAN0_a] = "can0_a",
[FUNC_CAN0_b] = "can0_b",
[FUNC_CAN1] = "can1",
[FUNC_CLKMON] = "clkmon",
[FUNC_NONE] = "none",
[FUNC_FC0_a] = "fc0_a",
[FUNC_FC0_b] = "fc0_b",
@ -262,6 +267,8 @@ static const char *const ocelot_function_names[] = {
[FUNC_PTPSYNC_6] = "ptpsync_6",
[FUNC_PTPSYNC_7] = "ptpsync_7",
[FUNC_PWM] = "pwm",
[FUNC_PWM_a] = "pwm_a",
[FUNC_PWM_b] = "pwm_b",
[FUNC_QSPI1] = "qspi1",
[FUNC_QSPI2] = "qspi2",
[FUNC_R] = "reserved",
@ -977,11 +984,11 @@ LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NON
LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R);
LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R);
LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R);
LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R);
LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R);
LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R);
LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);
LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
@ -1001,7 +1008,7 @@ LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN
LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R);
LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R);
LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R);
LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R);
LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R);
LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
@ -1908,6 +1915,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ocelot_pinctrl *info;
struct reset_control *reset;
struct regmap *pincfg;
void __iomem *base;
int ret;
@ -1923,6 +1931,12 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
reset = devm_reset_control_get_optional_shared(dev, "switch");
if (IS_ERR(reset))
return dev_err_probe(dev, PTR_ERR(reset),
"Failed to get reset\n");
reset_control_reset(reset);
base = devm_ioremap_resource(dev,
platform_get_resource(pdev, IORESOURCE_MEM, 0));
if (IS_ERR(base))

532
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -103,6 +103,25 @@
}, \
}
#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
iom2, iom3, pull0, pull1, \
pull2, pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
drv2, drv3, pull0, pull1, \
pull2, pull3) \
@ -197,6 +216,9 @@
#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
static struct regmap_config rockchip_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@ -837,6 +859,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
unsigned int val;
@ -878,6 +901,27 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
u32 reg0 = 0;
reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
ret = regmap_read(regmap, reg0, &val);
if (ret)
return ret;
if (!(val & BIT(8)))
return ((val >> bit) & mask);
reg = reg + 0x8000; /* BUS_IOC_BASE */
regmap = info->regmap_base;
}
} else if (bank->bank_num > 0) {
reg += 0x8000; /* BUS_IOC_BASE */
}
}
ret = regmap_read(regmap, reg, &val);
if (ret)
return ret;
@ -926,6 +970,7 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct device *dev = info->dev;
int iomux_num = (pin / 8);
struct regmap *regmap;
@ -966,6 +1011,46 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
if (mux < 8) {
reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= (mux & mask) << bit;
ret = regmap_update_bits(regmap, reg, rmask, data);
} else {
u32 reg0 = 0;
reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= 8 << bit;
ret = regmap_update_bits(regmap, reg0, rmask, data);
reg0 = reg + 0x8000; /* BUS_IOC_BASE */
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= mux << bit;
regmap = info->regmap_base;
ret |= regmap_update_bits(regmap, reg0, rmask, data);
}
} else {
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= (mux & mask) << bit;
ret = regmap_update_bits(regmap, reg, rmask, data);
}
return ret;
} else if (bank->bank_num > 0) {
reg += 0x8000; /* BUS_IOC_BASE */
}
}
if (mux > mask)
return -EINVAL;
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_location,
&route_reg, &route_val)) {
@ -1001,9 +1086,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
#define PX30_PULL_PINS_PER_REG 8
#define PX30_PULL_BANK_STRIDE 16
static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1023,6 +1108,8 @@ static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % PX30_PULL_PINS_PER_REG);
*bit *= PX30_PULL_BITS_PER_PIN;
return 0;
}
#define PX30_DRV_PMU_OFFSET 0x20
@ -1031,9 +1118,9 @@ static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
#define PX30_DRV_PINS_PER_REG 8
#define PX30_DRV_BANK_STRIDE 16
static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1053,6 +1140,8 @@ static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % PX30_DRV_PINS_PER_REG);
*bit *= PX30_DRV_BITS_PER_PIN;
return 0;
}
#define PX30_SCHMITT_PMU_OFFSET 0x38
@ -1092,9 +1181,9 @@ static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
#define RV1108_PULL_BITS_PER_PIN 2
#define RV1108_PULL_BANK_STRIDE 16
static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1113,6 +1202,8 @@ static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
*bit *= RV1108_PULL_BITS_PER_PIN;
return 0;
}
#define RV1108_DRV_PMU_OFFSET 0x20
@ -1121,9 +1212,9 @@ static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
#define RV1108_DRV_PINS_PER_REG 8
#define RV1108_DRV_BANK_STRIDE 16
static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1143,6 +1234,8 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1108_DRV_PINS_PER_REG;
*bit *= RV1108_DRV_BITS_PER_PIN;
return 0;
}
#define RV1108_SCHMITT_PMU_OFFSET 0x30
@ -1199,9 +1292,9 @@ static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK2928_PULL_PINS_PER_REG 16
#define RK2928_PULL_BANK_STRIDE 8
static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1211,13 +1304,15 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
*bit = pin_num % RK2928_PULL_PINS_PER_REG;
return 0;
};
#define RK3128_PULL_OFFSET 0x118
static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1227,6 +1322,8 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK2928_PULL_PINS_PER_REG;
return 0;
}
#define RK3188_PULL_OFFSET 0x164
@ -1235,9 +1332,9 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3188_PULL_BANK_STRIDE 16
#define RK3188_PULL_PMU_OFFSET 0x64
static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1267,12 +1364,14 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3288_PULL_OFFSET 0x140
static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1296,6 +1395,8 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3288_DRV_PMU_OFFSET 0x70
@ -1304,9 +1405,9 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3288_DRV_PINS_PER_REG 8
#define RK3288_DRV_BANK_STRIDE 16
static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1330,13 +1431,15 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
}
return 0;
}
#define RK3228_PULL_OFFSET 0x100
static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1347,13 +1450,15 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
return 0;
}
#define RK3228_DRV_GRF_OFFSET 0x200
static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1364,13 +1469,15 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
return 0;
}
#define RK3308_PULL_OFFSET 0xa0
static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1381,13 +1488,15 @@ static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
return 0;
}
#define RK3308_DRV_GRF_OFFSET 0x100
static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1398,14 +1507,16 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
return 0;
}
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1429,14 +1540,16 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3368_DRV_PMU_OFFSET 0x20
#define RK3368_DRV_GRF_OFFSET 0x200
static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1460,15 +1573,17 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
}
return 0;
}
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
#define RK3399_DRV_3BITS_PER_PIN 3
static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1494,11 +1609,13 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int drv_num = (pin_num / 8);
@ -1515,6 +1632,8 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % 8) * 3;
else
*bit = (pin_num % 8) * 2;
return 0;
}
#define RK3568_PULL_PMU_OFFSET 0x20
@ -1523,9 +1642,9 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3568_PULL_PINS_PER_REG 8
#define RK3568_PULL_BANK_STRIDE 0x10
static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1546,6 +1665,8 @@ static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
*bit *= RK3568_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3568_DRV_PMU_OFFSET 0x70
@ -1554,9 +1675,9 @@ static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3568_DRV_PINS_PER_REG 2
#define RK3568_DRV_BANK_STRIDE 0x40
static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
@ -1577,6 +1698,189 @@ static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % RK3568_DRV_PINS_PER_REG);
*bit *= RK3568_DRV_BITS_PER_PIN;
}
return 0;
}
#define RK3588_PMU1_IOC_REG (0x0000)
#define RK3588_PMU2_IOC_REG (0x4000)
#define RK3588_BUS_IOC_REG (0x8000)
#define RK3588_VCCIO1_4_IOC_REG (0x9000)
#define RK3588_VCCIO3_5_IOC_REG (0xA000)
#define RK3588_VCCIO2_IOC_REG (0xB000)
#define RK3588_VCCIO6_IOC_REG (0xC000)
#define RK3588_EMMC_IOC_REG (0xD000)
static const u32 rk3588_ds_regs[][2] = {
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
{RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
{RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
{RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
{RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
{RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
{RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
{RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
{RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
{RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
{RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
{RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
{RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
{RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
{RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
{RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
{RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
{RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
{RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
{RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
{RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
};
static const u32 rk3588_p_regs[][2] = {
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
};
static const u32 rk3588_smt_regs[][2] = {
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
};
#define RK3588_PULL_BITS_PER_PIN 2
#define RK3588_PULL_PINS_PER_REG 8
static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
u8 bank_num = bank->bank_num;
u32 pin = bank_num * 32 + pin_num;
int i;
for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
if (pin >= rk3588_p_regs[i][0]) {
*reg = rk3588_p_regs[i][1];
*regmap = info->regmap_base;
*bit = pin_num % RK3588_PULL_PINS_PER_REG;
*bit *= RK3588_PULL_BITS_PER_PIN;
return 0;
}
}
return -EINVAL;
}
#define RK3588_DRV_BITS_PER_PIN 4
#define RK3588_DRV_PINS_PER_REG 4
static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
u8 bank_num = bank->bank_num;
u32 pin = bank_num * 32 + pin_num;
int i;
for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
if (pin >= rk3588_ds_regs[i][0]) {
*reg = rk3588_ds_regs[i][1];
*regmap = info->regmap_base;
*bit = pin_num % RK3588_DRV_PINS_PER_REG;
*bit *= RK3588_DRV_BITS_PER_PIN;
return 0;
}
}
return -EINVAL;
}
#define RK3588_SMT_BITS_PER_PIN 1
#define RK3588_SMT_PINS_PER_REG 8
static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
u8 bank_num = bank->bank_num;
u32 pin = bank_num * 32 + pin_num;
int i;
for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
if (pin >= rk3588_smt_regs[i][0]) {
*reg = rk3588_smt_regs[i][1];
*regmap = info->regmap_base;
*bit = pin_num % RK3588_SMT_PINS_PER_REG;
*bit *= RK3588_SMT_BITS_PER_PIN;
return 0;
}
}
return -EINVAL;
}
static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
@ -1599,7 +1903,9 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ret)
return ret;
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
@ -1679,8 +1985,14 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
bank->bank_num, pin_num, strength);
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ctrl->type == RK3568) {
ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ret)
return ret;
if (ctrl->type == RK3588) {
rmask_bits = RK3588_DRV_BITS_PER_PIN;
ret = strength;
goto config;
} else if (ctrl->type == RK3568) {
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
goto config;
@ -1792,7 +2104,9 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
if (ctrl->type == RK3066B)
return PIN_CONFIG_BIAS_DISABLE;
ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ret)
return ret;
ret = regmap_read(regmap, reg, &data);
if (ret)
@ -1811,6 +2125,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RK3308:
case RK3368:
case RK3399:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
data >>= bit;
data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
@ -1839,7 +2154,9 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
if (ctrl->type == RK3066B)
return pull ? -EINVAL : 0;
ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ret)
return ret;
switch (ctrl->type) {
case RK2928:
@ -1857,6 +2174,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3368:
case RK3399:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
@ -2104,25 +2422,27 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3368:
case RK3399:
case RK3568:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
return false;
}
static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank,
unsigned int pin, u32 arg)
static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
unsigned int pin, u32 param, u32 arg)
{
struct rockchip_pin_output_deferred *cfg;
struct rockchip_pin_deferred *cfg;
cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
if (!cfg)
return -ENOMEM;
cfg->pin = pin;
cfg->param = param;
cfg->arg = arg;
list_add_tail(&cfg->head, &bank->deferred_output);
list_add_tail(&cfg->head, &bank->deferred_pins);
return 0;
}
@ -2143,6 +2463,25 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
/*
* Check for gpio driver not being probed yet.
* The lock makes sure that either gpio-probe has completed
* or the gpio driver hasn't probed yet.
*/
mutex_lock(&bank->deferred_lock);
if (!gpio || !gpio->direction_output) {
rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
arg);
mutex_unlock(&bank->deferred_lock);
if (rc)
return rc;
break;
}
mutex_unlock(&bank->deferred_lock);
}
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
rc = rockchip_set_pull(bank, pin - bank->pin_base,
@ -2171,27 +2510,21 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
if (rc != RK_FUNC_GPIO)
return -EINVAL;
/*
* Check for gpio driver not being probed yet.
* The lock makes sure that either gpio-probe has completed
* or the gpio driver hasn't probed yet.
*/
mutex_lock(&bank->deferred_lock);
if (!gpio || !gpio->direction_output) {
rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg);
mutex_unlock(&bank->deferred_lock);
if (rc)
return rc;
break;
}
mutex_unlock(&bank->deferred_lock);
rc = gpio->direction_output(gpio, pin - bank->pin_base,
arg);
if (rc)
return rc;
break;
case PIN_CONFIG_INPUT_ENABLE:
rc = rockchip_set_mux(bank, pin - bank->pin_base,
RK_FUNC_GPIO);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
rc = gpio->direction_input(gpio, pin - bank->pin_base);
if (rc)
return rc;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* rk3288 is the first with per-pin drive-strength */
if (!info->ctrl->drv_calc_reg)
@ -2500,7 +2833,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
pdesc++;
}
INIT_LIST_HEAD(&pin_bank->deferred_output);
INIT_LIST_HEAD(&pin_bank->deferred_pins);
mutex_init(&pin_bank->deferred_lock);
}
@ -2763,7 +3096,7 @@ static int rockchip_pinctrl_remove(struct platform_device *pdev)
{
struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
struct rockchip_pin_bank *bank;
struct rockchip_pin_output_deferred *cfg;
struct rockchip_pin_deferred *cfg;
int i;
of_platform_depopulate(&pdev->dev);
@ -2772,9 +3105,9 @@ static int rockchip_pinctrl_remove(struct platform_device *pdev)
bank = &info->ctrl->pin_banks[i];
mutex_lock(&bank->deferred_lock);
while (!list_empty(&bank->deferred_output)) {
cfg = list_first_entry(&bank->deferred_output,
struct rockchip_pin_output_deferred, head);
while (!list_empty(&bank->deferred_pins)) {
cfg = list_first_entry(&bank->deferred_pins,
struct rockchip_pin_deferred, head);
list_del(&cfg->head);
kfree(cfg);
}
@ -3207,6 +3540,29 @@ static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3588_pin_banks[] = {
RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
};
static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
.pin_banks = rk3588_pin_banks,
.nr_banks = ARRAY_SIZE(rk3588_pin_banks),
.label = "RK3588-GPIO",
.type = RK3588,
.pull_calc_reg = rk3588_calc_pull_reg_and_bit,
.drv_calc_reg = rk3588_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,px30-pinctrl",
.data = &px30_pin_ctrl },
@ -3238,6 +3594,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3399_pin_ctrl },
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },
{ .compatible = "rockchip,rk3588-pinctrl",
.data = &rk3588_pin_ctrl },
{},
};

177
drivers/pinctrl/pinctrl-rockchip.h
View File

@ -18,6 +18,171 @@
#ifndef _PINCTRL_ROCKCHIP_H
#define _PINCTRL_ROCKCHIP_H
#define RK_GPIO0_A0 0
#define RK_GPIO0_A1 1
#define RK_GPIO0_A2 2
#define RK_GPIO0_A3 3
#define RK_GPIO0_A4 4
#define RK_GPIO0_A5 5
#define RK_GPIO0_A6 6
#define RK_GPIO0_A7 7
#define RK_GPIO0_B0 8
#define RK_GPIO0_B1 9
#define RK_GPIO0_B2 10
#define RK_GPIO0_B3 11
#define RK_GPIO0_B4 12
#define RK_GPIO0_B5 13
#define RK_GPIO0_B6 14
#define RK_GPIO0_B7 15
#define RK_GPIO0_C0 16
#define RK_GPIO0_C1 17
#define RK_GPIO0_C2 18
#define RK_GPIO0_C3 19
#define RK_GPIO0_C4 20
#define RK_GPIO0_C5 21
#define RK_GPIO0_C6 22
#define RK_GPIO0_C7 23
#define RK_GPIO0_D0 24
#define RK_GPIO0_D1 25
#define RK_GPIO0_D2 26
#define RK_GPIO0_D3 27
#define RK_GPIO0_D4 28
#define RK_GPIO0_D5 29
#define RK_GPIO0_D6 30
#define RK_GPIO0_D7 31
#define RK_GPIO1_A0 32
#define RK_GPIO1_A1 33
#define RK_GPIO1_A2 34
#define RK_GPIO1_A3 35
#define RK_GPIO1_A4 36
#define RK_GPIO1_A5 37
#define RK_GPIO1_A6 38
#define RK_GPIO1_A7 39
#define RK_GPIO1_B0 40
#define RK_GPIO1_B1 41
#define RK_GPIO1_B2 42
#define RK_GPIO1_B3 43
#define RK_GPIO1_B4 44
#define RK_GPIO1_B5 45
#define RK_GPIO1_B6 46
#define RK_GPIO1_B7 47
#define RK_GPIO1_C0 48
#define RK_GPIO1_C1 49
#define RK_GPIO1_C2 50
#define RK_GPIO1_C3 51
#define RK_GPIO1_C4 52
#define RK_GPIO1_C5 53
#define RK_GPIO1_C6 54
#define RK_GPIO1_C7 55
#define RK_GPIO1_D0 56
#define RK_GPIO1_D1 57
#define RK_GPIO1_D2 58
#define RK_GPIO1_D3 59
#define RK_GPIO1_D4 60
#define RK_GPIO1_D5 61
#define RK_GPIO1_D6 62
#define RK_GPIO1_D7 63
#define RK_GPIO2_A0 64
#define RK_GPIO2_A1 65
#define RK_GPIO2_A2 66
#define RK_GPIO2_A3 67
#define RK_GPIO2_A4 68
#define RK_GPIO2_A5 69
#define RK_GPIO2_A6 70
#define RK_GPIO2_A7 71
#define RK_GPIO2_B0 72
#define RK_GPIO2_B1 73
#define RK_GPIO2_B2 74
#define RK_GPIO2_B3 75
#define RK_GPIO2_B4 76
#define RK_GPIO2_B5 77
#define RK_GPIO2_B6 78
#define RK_GPIO2_B7 79
#define RK_GPIO2_C0 80
#define RK_GPIO2_C1 81
#define RK_GPIO2_C2 82
#define RK_GPIO2_C3 83
#define RK_GPIO2_C4 84
#define RK_GPIO2_C5 85
#define RK_GPIO2_C6 86
#define RK_GPIO2_C7 87
#define RK_GPIO2_D0 88
#define RK_GPIO2_D1 89
#define RK_GPIO2_D2 90
#define RK_GPIO2_D3 91
#define RK_GPIO2_D4 92
#define RK_GPIO2_D5 93
#define RK_GPIO2_D6 94
#define RK_GPIO2_D7 95
#define RK_GPIO3_A0 96
#define RK_GPIO3_A1 97
#define RK_GPIO3_A2 98
#define RK_GPIO3_A3 99
#define RK_GPIO3_A4 100
#define RK_GPIO3_A5 101
#define RK_GPIO3_A6 102
#define RK_GPIO3_A7 103
#define RK_GPIO3_B0 104
#define RK_GPIO3_B1 105
#define RK_GPIO3_B2 106
#define RK_GPIO3_B3 107
#define RK_GPIO3_B4 108
#define RK_GPIO3_B5 109
#define RK_GPIO3_B6 110
#define RK_GPIO3_B7 111
#define RK_GPIO3_C0 112
#define RK_GPIO3_C1 113
#define RK_GPIO3_C2 114
#define RK_GPIO3_C3 115
#define RK_GPIO3_C4 116
#define RK_GPIO3_C5 117
#define RK_GPIO3_C6 118
#define RK_GPIO3_C7 119
#define RK_GPIO3_D0 120
#define RK_GPIO3_D1 121
#define RK_GPIO3_D2 122
#define RK_GPIO3_D3 123
#define RK_GPIO3_D4 124
#define RK_GPIO3_D5 125
#define RK_GPIO3_D6 126
#define RK_GPIO3_D7 127
#define RK_GPIO4_A0 128
#define RK_GPIO4_A1 129
#define RK_GPIO4_A2 130
#define RK_GPIO4_A3 131
#define RK_GPIO4_A4 132
#define RK_GPIO4_A5 133
#define RK_GPIO4_A6 134
#define RK_GPIO4_A7 135
#define RK_GPIO4_B0 136
#define RK_GPIO4_B1 137
#define RK_GPIO4_B2 138
#define RK_GPIO4_B3 139
#define RK_GPIO4_B4 140
#define RK_GPIO4_B5 141
#define RK_GPIO4_B6 142
#define RK_GPIO4_B7 143
#define RK_GPIO4_C0 144
#define RK_GPIO4_C1 145
#define RK_GPIO4_C2 146
#define RK_GPIO4_C3 147
#define RK_GPIO4_C4 148
#define RK_GPIO4_C5 149
#define RK_GPIO4_C6 150
#define RK_GPIO4_C7 151
#define RK_GPIO4_D0 152
#define RK_GPIO4_D1 153
#define RK_GPIO4_D2 154
#define RK_GPIO4_D3 155
#define RK_GPIO4_D4 156
#define RK_GPIO4_D5 157
#define RK_GPIO4_D6 158
#define RK_GPIO4_D7 159
enum rockchip_pinctrl_type {
PX30,
RV1108,
@ -30,6 +195,7 @@ enum rockchip_pinctrl_type {
RK3368,
RK3399,
RK3568,
RK3588,
};
/**
@ -171,7 +337,7 @@ struct rockchip_pin_bank {
u32 toggle_edge_mode;
u32 recalced_mask;
u32 route_mask;
struct list_head deferred_output;
struct list_head deferred_pins;
struct mutex deferred_lock;
};
@ -230,10 +396,10 @@ struct rockchip_pin_ctrl {
struct rockchip_mux_route_data *iomux_routes;
u32 niomux_routes;
void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
@ -247,9 +413,12 @@ struct rockchip_pin_config {
unsigned int nconfigs;
};
struct rockchip_pin_output_deferred {
enum pin_config_param;
struct rockchip_pin_deferred {
struct list_head head;
unsigned int pin;
enum pin_config_param param;
u32 arg;
};

11
drivers/pinctrl/pinctrl-starfive.c
View File

@ -1074,6 +1074,8 @@ static void starfive_irq_mask(struct irq_data *d)
value = readl_relaxed(ie) & ~mask;
writel_relaxed(value, ie);
raw_spin_unlock_irqrestore(&sfp->lock, flags);
gpiochip_disable_irq(&sfp->gc, d->hwirq);
}
static void starfive_irq_mask_ack(struct irq_data *d)
@ -1102,6 +1104,8 @@ static void starfive_irq_unmask(struct irq_data *d)
unsigned long flags;
u32 value;
gpiochip_enable_irq(&sfp->gc, d->hwirq);
raw_spin_lock_irqsave(&sfp->lock, flags);
value = readl_relaxed(ie) | mask;
writel_relaxed(value, ie);
@ -1163,14 +1167,15 @@ static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
return 0;
}
static struct irq_chip starfive_irq_chip = {
static const struct irq_chip starfive_irq_chip = {
.name = "StarFive GPIO",
.irq_ack = starfive_irq_ack,
.irq_mask = starfive_irq_mask,
.irq_mask_ack = starfive_irq_mask_ack,
.irq_unmask = starfive_irq_unmask,
.irq_set_type = starfive_irq_set_type,
.flags = IRQCHIP_SET_TYPE_MASKED,
.flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void starfive_gpio_irq_handler(struct irq_desc *desc)
@ -1308,7 +1313,7 @@ static int starfive_probe(struct platform_device *pdev)
sfp->gc.base = -1;
sfp->gc.ngpio = NR_GPIOS;
sfp->gc.irq.chip = &starfive_irq_chip;
gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
sfp->gc.irq.num_parents = 1;
sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,

7
drivers/pinctrl/pinctrl-thunderbay.c
View File

@ -1229,7 +1229,6 @@ static int thunderbay_pinctrl_probe(struct platform_device *pdev)
const struct of_device_id *of_id;
struct device *dev = &pdev->dev;
struct thunderbay_pinctrl *tpc;
struct resource *iomem;
int ret;
of_id = of_match_node(thunderbay_pinctrl_match, pdev->dev.of_node);
@ -1243,11 +1242,7 @@ static int thunderbay_pinctrl_probe(struct platform_device *pdev)
tpc->dev = dev;
tpc->soc = of_id->data;
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!iomem)
return -ENXIO;
tpc->base0 = devm_ioremap_resource(dev, iomem);
tpc->base0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(tpc->base0))
return PTR_ERR(tpc->base0);

19
drivers/pinctrl/qcom/Kconfig
View File

@ -239,6 +239,15 @@ config PINCTRL_SC7280
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7280 platform.
config PINCTRL_SC7280_LPASS_LPI
tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
config PINCTRL_SC8180X
tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
depends on (OF || ACPI)
@ -338,6 +347,15 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
config PINCTRL_SM8250_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
config PINCTRL_SM8350
tristate "Qualcomm Technologies Inc SM8350 pin controller driver"
depends on PINCTRL_MSM
@ -360,6 +378,7 @@ config PINCTRL_LPASS_LPI
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
depends on GPIOLIB
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the

2
drivers/pinctrl/qcom/Makefile
View File

@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
@ -39,6 +40,7 @@ obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o

309
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
View File

@ -4,93 +4,15 @@
* Copyright (c) 2020 Linaro Ltd.
*/
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#define LPI_SLEW_RATE_CTL_REG 0xa000
#define LPI_TLMM_REG_OFFSET 0x1000
#define LPI_SLEW_RATE_MAX 0x03
#define LPI_SLEW_BITS_SIZE 0x02
#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
#define LPI_GPIO_CFG_REG 0x00
#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
#define LPI_GPIO_OE_MASK BIT(9)
#define LPI_GPIO_VALUE_REG 0x04
#define LPI_GPIO_VALUE_IN_MASK BIT(0)
#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
#define LPI_GPIO_BIAS_DISABLE 0x0
#define LPI_GPIO_PULL_DOWN 0x1
#define LPI_GPIO_KEEPER 0x2
#define LPI_GPIO_PULL_UP 0x3
#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
#define NO_SLEW -1
#define LPI_FUNCTION(fname) \
[LPI_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.pin = id, \
.slew_offset = soff, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
LPI_MUX_##f2, \
LPI_MUX_##f3, \
LPI_MUX_##f4, \
}, \
.nfuncs = 5, \
}
struct lpi_pingroup {
const char *name;
const unsigned int *pins;
unsigned int npins;
unsigned int pin;
/* Bit offset in slew register for SoundWire pins only */
int slew_offset;
unsigned int *funcs;
unsigned int nfuncs;
};
struct lpi_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
};
struct lpi_pinctrl_variant_data {
const struct pinctrl_pin_desc *pins;
int npins;
const struct lpi_pingroup *groups;
int ngroups;
const struct lpi_function *functions;
int nfunctions;
};
#include "pinctrl-lpass-lpi.h"
#define MAX_LPI_NUM_CLKS 2
@ -106,136 +28,6 @@ struct lpi_pinctrl {
const struct lpi_pinctrl_variant_data *data;
};
/* sm8250 variant specific data */
static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
};
enum sm8250_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_qua_mi2s_data,
LPI_MUX_qua_mi2s_sclk,
LPI_MUX_qua_mi2s_ws,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_gpio,
LPI_MUX__,
};
static const unsigned int gpio0_pins[] = { 0 };
static const unsigned int gpio1_pins[] = { 1 };
static const unsigned int gpio2_pins[] = { 2 };
static const unsigned int gpio3_pins[] = { 3 };
static const unsigned int gpio4_pins[] = { 4 };
static const unsigned int gpio5_pins[] = { 5 };
static const unsigned int gpio6_pins[] = { 6 };
static const unsigned int gpio7_pins[] = { 7 };
static const unsigned int gpio8_pins[] = { 8 };
static const unsigned int gpio9_pins[] = { 9 };
static const unsigned int gpio10_pins[] = { 10 };
static const unsigned int gpio11_pins[] = { 11 };
static const unsigned int gpio12_pins[] = { 12 };
static const unsigned int gpio13_pins[] = { 13 };
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const i2s2_clk_groups[] = { "gpio10" };
static const char * const i2s2_ws_groups[] = { "gpio11" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
static const char * const i2s1_clk_groups[] = { "gpio6" };
static const char * const i2s1_ws_groups[] = { "gpio7" };
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_data_groups[] = { "gpio11" };
static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
static const struct lpi_pingroup sm8250_groups[] = {
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
};
static const struct lpi_function sm8250_functions[] = {
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(qua_mi2s_data),
LPI_FUNCTION(qua_mi2s_sclk),
LPI_FUNCTION(qua_mi2s_ws),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
};
static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
.pins = sm8250_lpi_pins,
.npins = ARRAY_SIZE(sm8250_lpi_pins),
.groups = sm8250_groups,
.ngroups = ARRAY_SIZE(sm8250_groups),
.functions = sm8250_functions,
.nfunctions = ARRAY_SIZE(sm8250_functions),
};
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr)
{
@ -250,38 +42,10 @@ static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
return 0;
}
static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev)
{
struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->data->ngroups;
}
static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->data->groups[group].name;
}
static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->data->groups[group].pins;
*num_pins = pctrl->data->groups[group].npins;
return 0;
}
static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
.get_groups_count = lpi_gpio_get_groups_count,
.get_group_name = lpi_gpio_get_group_name,
.get_group_pins = lpi_gpio_get_group_pins,
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinctrl_utils_free_map,
};
@ -435,7 +199,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
}
slew_offset = g->slew_offset;
if (slew_offset == NO_SLEW)
if (slew_offset == LPI_NO_SLEW)
break;
mutex_lock(&pctrl->slew_access_lock);
@ -582,7 +346,29 @@ static const struct gpio_chip lpi_gpio_template = {
.dbg_show = lpi_gpio_dbg_show,
};
static int lpi_pinctrl_probe(struct platform_device *pdev)
static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
{
int i, ret;
for (i = 0; i < pctrl->data->npins; i++) {
const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
(int *)&pin_info->number, 1, NULL);
if (ret < 0)
goto err_pinctrl;
}
return 0;
err_pinctrl:
for (; i > 0; i--)
pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
return ret;
}
int lpi_pinctrl_probe(struct platform_device *pdev)
{
const struct lpi_pinctrl_variant_data *data;
struct device *dev = &pdev->dev;
@ -615,9 +401,13 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
"Slew resource not provided\n");
ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
if (data->is_clk_optional)
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
else
ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
if (ret)
return dev_err_probe(dev, ret, "Can't get clocks\n");
return ret;
ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
if (ret)
@ -647,6 +437,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
goto err_pinctrl;
}
ret = lpi_build_pin_desc_groups(pctrl);
if (ret)
goto err_pinctrl;
ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "can't add gpio chip\n");
@ -661,35 +455,22 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
return ret;
}
EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
static int lpi_pinctrl_remove(struct platform_device *pdev)
int lpi_pinctrl_remove(struct platform_device *pdev)
{
struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
int i;
mutex_destroy(&pctrl->slew_access_lock);
clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
for (i = 0; i < pctrl->data->npins; i++)
pinctrl_generic_remove_group(pctrl->ctrl, i);
return 0;
}
EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,sm8250-lpass-lpi-pinctrl",
.data = &sm8250_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

86
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h Normal file
View File

@ -0,0 +1,86 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2020 Linaro Ltd.
*/
#ifndef __PINCTRL_LPASS_LPI_H__
#define __PINCTRL_LPASS_LPI_H__
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include "../core.h"
#define LPI_SLEW_RATE_CTL_REG 0xa000
#define LPI_TLMM_REG_OFFSET 0x1000
#define LPI_SLEW_RATE_MAX 0x03
#define LPI_SLEW_BITS_SIZE 0x02
#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
#define LPI_GPIO_CFG_REG 0x00
#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
#define LPI_GPIO_OE_MASK BIT(9)
#define LPI_GPIO_VALUE_REG 0x04
#define LPI_GPIO_VALUE_IN_MASK BIT(0)
#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
#define LPI_GPIO_BIAS_DISABLE 0x0
#define LPI_GPIO_PULL_DOWN 0x1
#define LPI_GPIO_KEEPER 0x2
#define LPI_GPIO_PULL_UP 0x3
#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
#define LPI_NO_SLEW -1
#define LPI_FUNCTION(fname) \
[LPI_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
{ \
.group.name = "gpio" #id, \
.group.pins = gpio##id##_pins, \
.pin = id, \
.slew_offset = soff, \
.group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
LPI_MUX_##f2, \
LPI_MUX_##f3, \
LPI_MUX_##f4, \
}, \
.nfuncs = 5, \
}
struct lpi_pingroup {
struct group_desc group;
unsigned int pin;
/* Bit offset in slew register for SoundWire pins only */
int slew_offset;
unsigned int *funcs;
unsigned int nfuncs;
};
struct lpi_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
};
struct lpi_pinctrl_variant_data {
const struct pinctrl_pin_desc *pins;
int npins;
const struct lpi_pingroup *groups;
int ngroups;
const struct lpi_function *functions;
int nfunctions;
bool is_clk_optional;
};
int lpi_pinctrl_probe(struct platform_device *pdev);
int lpi_pinctrl_remove(struct platform_device *pdev);
#endif /*__PINCTRL_LPASS_LPI_H__*/

167
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c Normal file
View File

@ -0,0 +1,167 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* ALSA SoC platform-machine driver for QTi LPASS
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_qua_mi2s_data,
LPI_MUX_qua_mi2s_sclk,
LPI_MUX_qua_mi2s_ws,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_gpio,
LPI_MUX__,
};
static int gpio0_pins[] = { 0 };
static int gpio1_pins[] = { 1 };
static int gpio2_pins[] = { 2 };
static int gpio3_pins[] = { 3 };
static int gpio4_pins[] = { 4 };
static int gpio5_pins[] = { 5 };
static int gpio6_pins[] = { 6 };
static int gpio7_pins[] = { 7 };
static int gpio8_pins[] = { 8 };
static int gpio9_pins[] = { 9 };
static int gpio10_pins[] = { 10 };
static int gpio11_pins[] = { 11 };
static int gpio12_pins[] = { 12 };
static int gpio13_pins[] = { 13 };
static int gpio14_pins[] = { 14 };
static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
};
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const i2s2_clk_groups[] = { "gpio10" };
static const char * const i2s2_ws_groups[] = { "gpio11" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
static const char * const i2s1_clk_groups[] = { "gpio6" };
static const char * const i2s1_ws_groups[] = { "gpio7" };
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_data_groups[] = { "gpio11" };
static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
static const struct lpi_pingroup sc7280_groups[] = {
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
};
static const struct lpi_function sc7280_functions[] = {
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(qua_mi2s_data),
LPI_FUNCTION(qua_mi2s_sclk),
LPI_FUNCTION(qua_mi2s_ws),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
};
static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
.pins = sc7280_lpi_pins,
.npins = ARRAY_SIZE(sc7280_lpi_pins),
.groups = sc7280_groups,
.ngroups = ARRAY_SIZE(sc7280_groups),
.functions = sc7280_functions,
.nfunctions = ARRAY_SIZE(sc7280_functions),
.is_clk_optional = true,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,sc7280-lpass-lpi-pinctrl",
.data = &sc7280_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-sc7280-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

22
drivers/pinctrl/qcom/pinctrl-sm8150.c
View File

@ -1500,6 +1500,25 @@ static const struct msm_pingroup sm8150_groups[] = {
[178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
};
static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = {
{ 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 },
{ 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 },
{ 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 },
{ 39, 125 }, { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 },
{ 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 51, 123 },
{ 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 },
{ 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 },
{ 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 },
{ 88, 117 }, { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 },
{ 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 },
{ 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 },
{ 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 },
{ 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 },
{ 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 },
{ 144, 115 }, { 144, 122 }, { 147, 102 }, { 150, 107 },
{ 152, 108 }, { 153, 109 }
};
static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
.pins = sm8150_pins,
.npins = ARRAY_SIZE(sm8150_pins),
@ -1510,6 +1529,9 @@ static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
.ngpios = 176,
.tiles = sm8150_tiles,
.ntiles = ARRAY_SIZE(sm8150_tiles),
.wakeirq_map = sm8150_pdc_map,
.nwakeirq_map = ARRAY_SIZE(sm8150_pdc_map),
.wakeirq_dual_edge_errata = true,
};
static int sm8150_pinctrl_probe(struct platform_device *pdev)

163
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c Normal file
View File

@ -0,0 +1,163 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2020 Linaro Ltd.
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_qua_mi2s_data,
LPI_MUX_qua_mi2s_sclk,
LPI_MUX_qua_mi2s_ws,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_gpio,
LPI_MUX__,
};
static int gpio0_pins[] = { 0 };
static int gpio1_pins[] = { 1 };
static int gpio2_pins[] = { 2 };
static int gpio3_pins[] = { 3 };
static int gpio4_pins[] = { 4 };
static int gpio5_pins[] = { 5 };
static int gpio6_pins[] = { 6 };
static int gpio7_pins[] = { 7 };
static int gpio8_pins[] = { 8 };
static int gpio9_pins[] = { 9 };
static int gpio10_pins[] = { 10 };
static int gpio11_pins[] = { 11 };
static int gpio12_pins[] = { 12 };
static int gpio13_pins[] = { 13 };
static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
};
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const i2s2_clk_groups[] = { "gpio10" };
static const char * const i2s2_ws_groups[] = { "gpio11" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
static const char * const i2s1_clk_groups[] = { "gpio6" };
static const char * const i2s1_ws_groups[] = { "gpio7" };
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_data_groups[] = { "gpio11" };
static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
static const struct lpi_pingroup sm8250_groups[] = {
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
};
static const struct lpi_function sm8250_functions[] = {
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(qua_mi2s_data),
LPI_FUNCTION(qua_mi2s_sclk),
LPI_FUNCTION(qua_mi2s_ws),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
};
static const struct lpi_pinctrl_variant_data sm8250_lpi_data = {
.pins = sm8250_lpi_pins,
.npins = ARRAY_SIZE(sm8250_lpi_pins),
.groups = sm8250_groups,
.ngroups = ARRAY_SIZE(sm8250_groups),
.functions = sm8250_functions,
.nfunctions = ARRAY_SIZE(sm8250_functions),
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,sm8250-lpass-lpi-pinctrl",
.data = &sm8250_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-sm8250-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

2
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -1146,6 +1146,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
@ -1183,6 +1184,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
{ .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
{ },
};

28
drivers/pinctrl/ralink/Kconfig
View File

@ -3,37 +3,33 @@ menu "Ralink pinctrl drivers"
depends on RALINK
config PINCTRL_RALINK
bool "Ralink pin control support"
default y if RALINK
config PINCTRL_RT2880
bool "RT2880 pinctrl driver for RALINK/Mediatek SOCs"
bool "Ralink pinctrl driver"
select PINMUX
select GENERIC_PINCONF
config PINCTRL_MT7620
bool "mt7620 pinctrl driver for RALINK/Mediatek SOCs"
bool "MT7620 pinctrl subdriver"
depends on RALINK && SOC_MT7620
select PINCTRL_RT2880
select PINCTRL_RALINK
config PINCTRL_MT7621
bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs"
bool "MT7621 pinctrl subdriver"
depends on RALINK && SOC_MT7621
select PINCTRL_RT2880
select PINCTRL_RALINK
config PINCTRL_RT288X
bool "RT288X pinctrl driver for RALINK/Mediatek SOCs"
config PINCTRL_RT2880
bool "RT2880 pinctrl subdriver"
depends on RALINK && SOC_RT288X
select PINCTRL_RT2880
select PINCTRL_RALINK
config PINCTRL_RT305X
bool "RT305X pinctrl driver for RALINK/Mediatek SOCs"
bool "RT305X pinctrl subdriver"
depends on RALINK && SOC_RT305X
select PINCTRL_RT2880
select PINCTRL_RALINK
config PINCTRL_RT3883
bool "RT3883 pinctrl driver for RALINK/Mediatek SOCs"
bool "RT3883 pinctrl subdriver"
depends on RALINK && SOC_RT3883
select PINCTRL_RT2880
select PINCTRL_RALINK
endmenu

4
drivers/pinctrl/ralink/Makefile
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
obj-$(CONFIG_PINCTRL_RALINK) += pinctrl-ralink.o
obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
obj-$(CONFIG_PINCTRL_RT288X) += pinctrl-rt288x.o
obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o
obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o

298
drivers/pinctrl/ralink/pinctrl-mt7620.c
View File

@ -5,7 +5,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinmux.h"
#include "pinctrl-ralink.h"
#define MT7620_GPIO_MODE_UART0_SHIFT 2
#define MT7620_GPIO_MODE_UART0_MASK 0x7
@ -54,20 +54,20 @@
#define MT7620_GPIO_MODE_EPHY 15
#define MT7620_GPIO_MODE_PA 20
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
static struct rt2880_pmx_func mdio_grp[] = {
static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
static struct ralink_pmx_func mdio_func[] = {
FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
};
static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
static struct rt2880_pmx_func uartf_grp[] = {
static struct ralink_pmx_func rgmii1_func[] = { FUNC("rgmii1", 0, 24, 12) };
static struct ralink_pmx_func refclk_func[] = { FUNC("spi refclk", 0, 37, 3) };
static struct ralink_pmx_func ephy_func[] = { FUNC("ephy", 0, 40, 5) };
static struct ralink_pmx_func rgmii2_func[] = { FUNC("rgmii2", 0, 60, 12) };
static struct ralink_pmx_func wled_func[] = { FUNC("wled", 0, 72, 1) };
static struct ralink_pmx_func pa_func[] = { FUNC("pa", 0, 18, 4) };
static struct ralink_pmx_func uartf_func[] = {
FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
@ -76,316 +76,316 @@ static struct rt2880_pmx_func uartf_grp[] = {
FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
};
static struct rt2880_pmx_func wdt_grp[] = {
static struct ralink_pmx_func wdt_func[] = {
FUNC("wdt rst", 0, 17, 1),
FUNC("wdt refclk", 0, 17, 1),
};
static struct rt2880_pmx_func pcie_rst_grp[] = {
static struct ralink_pmx_func pcie_rst_func[] = {
FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
};
static struct rt2880_pmx_func nd_sd_grp[] = {
static struct ralink_pmx_func nd_sd_func[] = {
FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13)
};
static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
static struct ralink_pmx_group mt7620a_pinmux_data[] = {
GRP("i2c", i2c_func, 1, MT7620_GPIO_MODE_I2C),
GRP("uartf", uartf_func, MT7620_GPIO_MODE_UART0_MASK,
MT7620_GPIO_MODE_UART0_SHIFT),
GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
GRP("spi", spi_func, 1, MT7620_GPIO_MODE_SPI),
GRP("uartlite", uartlite_func, 1, MT7620_GPIO_MODE_UART1),
GRP_G("wdt", wdt_func, MT7620_GPIO_MODE_WDT_MASK,
MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
GRP_G("mdio", mdio_func, MT7620_GPIO_MODE_MDIO_MASK,
MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
GRP("rgmii1", rgmii1_func, 1, MT7620_GPIO_MODE_RGMII1),
GRP("spi refclk", refclk_func, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
GRP_G("pcie", pcie_rst_func, MT7620_GPIO_MODE_PCIE_MASK,
MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
GRP_G("nd_sd", nd_sd_func, MT7620_GPIO_MODE_ND_SD_MASK,
MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
GRP("rgmii2", rgmii2_func, 1, MT7620_GPIO_MODE_RGMII2),
GRP("wled", wled_func, 1, MT7620_GPIO_MODE_WLED),
GRP("ephy", ephy_func, 1, MT7620_GPIO_MODE_EPHY),
GRP("pa", pa_func, 1, MT7620_GPIO_MODE_PA),
{ 0 }
};
static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
static struct ralink_pmx_func pwm1_func_mt76x8[] = {
FUNC("sdxc d6", 3, 19, 1),
FUNC("utif", 2, 19, 1),
FUNC("gpio", 1, 19, 1),
FUNC("pwm1", 0, 19, 1),
};
static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
static struct ralink_pmx_func pwm0_func_mt76x8[] = {
FUNC("sdxc d7", 3, 18, 1),
FUNC("utif", 2, 18, 1),
FUNC("gpio", 1, 18, 1),
FUNC("pwm0", 0, 18, 1),
};
static struct rt2880_pmx_func uart2_grp_mt7628[] = {
static struct ralink_pmx_func uart2_func_mt76x8[] = {
FUNC("sdxc d5 d4", 3, 20, 2),
FUNC("pwm", 2, 20, 2),
FUNC("gpio", 1, 20, 2),
FUNC("uart2", 0, 20, 2),
};
static struct rt2880_pmx_func uart1_grp_mt7628[] = {
static struct ralink_pmx_func uart1_func_mt76x8[] = {
FUNC("sw_r", 3, 45, 2),
FUNC("pwm", 2, 45, 2),
FUNC("gpio", 1, 45, 2),
FUNC("uart1", 0, 45, 2),
};
static struct rt2880_pmx_func i2c_grp_mt7628[] = {
static struct ralink_pmx_func i2c_func_mt76x8[] = {
FUNC("-", 3, 4, 2),
FUNC("debug", 2, 4, 2),
FUNC("gpio", 1, 4, 2),
FUNC("i2c", 0, 4, 2),
};
static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) };
static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) };
static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
static struct ralink_pmx_func refclk_func_mt76x8[] = { FUNC("refclk", 0, 37, 1) };
static struct ralink_pmx_func perst_func_mt76x8[] = { FUNC("perst", 0, 36, 1) };
static struct ralink_pmx_func wdt_func_mt76x8[] = { FUNC("wdt", 0, 38, 1) };
static struct ralink_pmx_func spi_func_mt76x8[] = { FUNC("spi", 0, 7, 4) };
static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
static struct ralink_pmx_func sd_mode_func_mt76x8[] = {
FUNC("jtag", 3, 22, 8),
FUNC("utif", 2, 22, 8),
FUNC("gpio", 1, 22, 8),
FUNC("sdxc", 0, 22, 8),
};
static struct rt2880_pmx_func uart0_grp_mt7628[] = {
static struct ralink_pmx_func uart0_func_mt76x8[] = {
FUNC("-", 3, 12, 2),
FUNC("-", 2, 12, 2),
FUNC("gpio", 1, 12, 2),
FUNC("uart0", 0, 12, 2),
};
static struct rt2880_pmx_func i2s_grp_mt7628[] = {
static struct ralink_pmx_func i2s_func_mt76x8[] = {
FUNC("antenna", 3, 0, 4),
FUNC("pcm", 2, 0, 4),
FUNC("gpio", 1, 0, 4),
FUNC("i2s", 0, 0, 4),
};
static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
static struct ralink_pmx_func spi_cs1_func_mt76x8[] = {
FUNC("-", 3, 6, 1),
FUNC("refclk", 2, 6, 1),
FUNC("gpio", 1, 6, 1),
FUNC("spi cs1", 0, 6, 1),
};
static struct rt2880_pmx_func spis_grp_mt7628[] = {
static struct ralink_pmx_func spis_func_mt76x8[] = {
FUNC("pwm_uart2", 3, 14, 4),
FUNC("utif", 2, 14, 4),
FUNC("gpio", 1, 14, 4),
FUNC("spis", 0, 14, 4),
};
static struct rt2880_pmx_func gpio_grp_mt7628[] = {
static struct ralink_pmx_func gpio_func_mt76x8[] = {
FUNC("pcie", 3, 11, 1),
FUNC("refclk", 2, 11, 1),
FUNC("gpio", 1, 11, 1),
FUNC("gpio", 0, 11, 1),
};
static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
static struct ralink_pmx_func p4led_kn_func_mt76x8[] = {
FUNC("jtag", 3, 30, 1),
FUNC("utif", 2, 30, 1),
FUNC("gpio", 1, 30, 1),
FUNC("p4led_kn", 0, 30, 1),
};
static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
static struct ralink_pmx_func p3led_kn_func_mt76x8[] = {
FUNC("jtag", 3, 31, 1),
FUNC("utif", 2, 31, 1),
FUNC("gpio", 1, 31, 1),
FUNC("p3led_kn", 0, 31, 1),
};
static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
static struct ralink_pmx_func p2led_kn_func_mt76x8[] = {
FUNC("jtag", 3, 32, 1),
FUNC("utif", 2, 32, 1),
FUNC("gpio", 1, 32, 1),
FUNC("p2led_kn", 0, 32, 1),
};
static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
static struct ralink_pmx_func p1led_kn_func_mt76x8[] = {
FUNC("jtag", 3, 33, 1),
FUNC("utif", 2, 33, 1),
FUNC("gpio", 1, 33, 1),
FUNC("p1led_kn", 0, 33, 1),
};
static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = {
static struct ralink_pmx_func p0led_kn_func_mt76x8[] = {
FUNC("jtag", 3, 34, 1),
FUNC("rsvd", 2, 34, 1),
FUNC("gpio", 1, 34, 1),
FUNC("p0led_kn", 0, 34, 1),
};
static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
static struct ralink_pmx_func wled_kn_func_mt76x8[] = {
FUNC("rsvd", 3, 35, 1),
FUNC("rsvd", 2, 35, 1),
FUNC("gpio", 1, 35, 1),
FUNC("wled_kn", 0, 35, 1),
};
static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
static struct ralink_pmx_func p4led_an_func_mt76x8[] = {
FUNC("jtag", 3, 39, 1),
FUNC("utif", 2, 39, 1),
FUNC("gpio", 1, 39, 1),
FUNC("p4led_an", 0, 39, 1),
};
static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
static struct ralink_pmx_func p3led_an_func_mt76x8[] = {
FUNC("jtag", 3, 40, 1),
FUNC("utif", 2, 40, 1),
FUNC("gpio", 1, 40, 1),
FUNC("p3led_an", 0, 40, 1),
};
static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
static struct ralink_pmx_func p2led_an_func_mt76x8[] = {
FUNC("jtag", 3, 41, 1),
FUNC("utif", 2, 41, 1),
FUNC("gpio", 1, 41, 1),
FUNC("p2led_an", 0, 41, 1),
};
static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
static struct ralink_pmx_func p1led_an_func_mt76x8[] = {
FUNC("jtag", 3, 42, 1),
FUNC("utif", 2, 42, 1),
FUNC("gpio", 1, 42, 1),
FUNC("p1led_an", 0, 42, 1),
};
static struct rt2880_pmx_func p0led_an_grp_mt7628[] = {
static struct ralink_pmx_func p0led_an_func_mt76x8[] = {
FUNC("jtag", 3, 43, 1),
FUNC("rsvd", 2, 43, 1),
FUNC("gpio", 1, 43, 1),
FUNC("p0led_an", 0, 43, 1),
};
static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
static struct ralink_pmx_func wled_an_func_mt76x8[] = {
FUNC("rsvd", 3, 44, 1),
FUNC("rsvd", 2, 44, 1),
FUNC("gpio", 1, 44, 1),
FUNC("wled_an", 0, 44, 1),
};
#define MT7628_GPIO_MODE_MASK 0x3
#define MT76X8_GPIO_MODE_MASK 0x3
#define MT7628_GPIO_MODE_P4LED_KN 58
#define MT7628_GPIO_MODE_P3LED_KN 56
#define MT7628_GPIO_MODE_P2LED_KN 54
#define MT7628_GPIO_MODE_P1LED_KN 52
#define MT7628_GPIO_MODE_P0LED_KN 50
#define MT7628_GPIO_MODE_WLED_KN 48
#define MT7628_GPIO_MODE_P4LED_AN 42
#define MT7628_GPIO_MODE_P3LED_AN 40
#define MT7628_GPIO_MODE_P2LED_AN 38
#define MT7628_GPIO_MODE_P1LED_AN 36
#define MT7628_GPIO_MODE_P0LED_AN 34
#define MT7628_GPIO_MODE_WLED_AN 32
#define MT7628_GPIO_MODE_PWM1 30
#define MT7628_GPIO_MODE_PWM0 28
#define MT7628_GPIO_MODE_UART2 26
#define MT7628_GPIO_MODE_UART1 24
#define MT7628_GPIO_MODE_I2C 20
#define MT7628_GPIO_MODE_REFCLK 18
#define MT7628_GPIO_MODE_PERST 16
#define MT7628_GPIO_MODE_WDT 14
#define MT7628_GPIO_MODE_SPI 12
#define MT7628_GPIO_MODE_SDMODE 10
#define MT7628_GPIO_MODE_UART0 8
#define MT7628_GPIO_MODE_I2S 6
#define MT7628_GPIO_MODE_CS1 4
#define MT7628_GPIO_MODE_SPIS 2
#define MT7628_GPIO_MODE_GPIO 0
#define MT76X8_GPIO_MODE_P4LED_KN 58
#define MT76X8_GPIO_MODE_P3LED_KN 56
#define MT76X8_GPIO_MODE_P2LED_KN 54
#define MT76X8_GPIO_MODE_P1LED_KN 52
#define MT76X8_GPIO_MODE_P0LED_KN 50
#define MT76X8_GPIO_MODE_WLED_KN 48
#define MT76X8_GPIO_MODE_P4LED_AN 42
#define MT76X8_GPIO_MODE_P3LED_AN 40
#define MT76X8_GPIO_MODE_P2LED_AN 38
#define MT76X8_GPIO_MODE_P1LED_AN 36
#define MT76X8_GPIO_MODE_P0LED_AN 34
#define MT76X8_GPIO_MODE_WLED_AN 32
#define MT76X8_GPIO_MODE_PWM1 30
#define MT76X8_GPIO_MODE_PWM0 28
#define MT76X8_GPIO_MODE_UART2 26
#define MT76X8_GPIO_MODE_UART1 24
#define MT76X8_GPIO_MODE_I2C 20
#define MT76X8_GPIO_MODE_REFCLK 18
#define MT76X8_GPIO_MODE_PERST 16
#define MT76X8_GPIO_MODE_WDT 14
#define MT76X8_GPIO_MODE_SPI 12
#define MT76X8_GPIO_MODE_SDMODE 10
#define MT76X8_GPIO_MODE_UART0 8
#define MT76X8_GPIO_MODE_I2S 6
#define MT76X8_GPIO_MODE_CS1 4
#define MT76X8_GPIO_MODE_SPIS 2
#define MT76X8_GPIO_MODE_GPIO 0
static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_PWM1),
GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_PWM0),
GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_UART2),
GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_UART1),
GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_I2C),
GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_SDMODE),
GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_UART0),
GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_I2S),
GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_CS1),
GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_SPIS),
GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_GPIO),
GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_WLED_AN),
GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P0LED_AN),
GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P1LED_AN),
GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P2LED_AN),
GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P3LED_AN),
GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P4LED_AN),
GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_WLED_KN),
GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P0LED_KN),
GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P1LED_KN),
GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P2LED_KN),
GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P3LED_KN),
GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P4LED_KN),
static struct ralink_pmx_group mt76x8_pinmux_data[] = {
GRP_G("pwm1", pwm1_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_PWM1),
GRP_G("pwm0", pwm0_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_PWM0),
GRP_G("uart2", uart2_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_UART2),
GRP_G("uart1", uart1_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_UART1),
GRP_G("i2c", i2c_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_I2C),
GRP("refclk", refclk_func_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK),
GRP("perst", perst_func_mt76x8, 1, MT76X8_GPIO_MODE_PERST),
GRP("wdt", wdt_func_mt76x8, 1, MT76X8_GPIO_MODE_WDT),
GRP("spi", spi_func_mt76x8, 1, MT76X8_GPIO_MODE_SPI),
GRP_G("sdmode", sd_mode_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_SDMODE),
GRP_G("uart0", uart0_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_UART0),
GRP_G("i2s", i2s_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_I2S),
GRP_G("spi cs1", spi_cs1_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_CS1),
GRP_G("spis", spis_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_SPIS),
GRP_G("gpio", gpio_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_GPIO),
GRP_G("wled_an", wled_an_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_WLED_AN),
GRP_G("p0led_an", p0led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P0LED_AN),
GRP_G("p1led_an", p1led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P1LED_AN),
GRP_G("p2led_an", p2led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P2LED_AN),
GRP_G("p3led_an", p3led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P3LED_AN),
GRP_G("p4led_an", p4led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P4LED_AN),
GRP_G("wled_kn", wled_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_WLED_KN),
GRP_G("p0led_kn", p0led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P0LED_KN),
GRP_G("p1led_kn", p1led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P1LED_KN),
GRP_G("p2led_kn", p2led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P2LED_KN),
GRP_G("p3led_kn", p3led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P3LED_KN),
GRP_G("p4led_kn", p4led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P4LED_KN),
{ 0 }
};
static int mt7620_pinmux_probe(struct platform_device *pdev)
static int mt7620_pinctrl_probe(struct platform_device *pdev)
{
if (is_mt76x8())
return rt2880_pinmux_init(pdev, mt7628an_pinmux_data);
return ralink_pinctrl_init(pdev, mt76x8_pinmux_data);
else
return rt2880_pinmux_init(pdev, mt7620a_pinmux_data);
return ralink_pinctrl_init(pdev, mt7620a_pinmux_data);
}
static const struct of_device_id mt7620_pinmux_match[] = {
{ .compatible = "ralink,rt2880-pinmux" },
static const struct of_device_id mt7620_pinctrl_match[] = {
{ .compatible = "ralink,mt7620-pinctrl" },
{}
};
MODULE_DEVICE_TABLE(of, mt7620_pinmux_match);
MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match);
static struct platform_driver mt7620_pinmux_driver = {
.probe = mt7620_pinmux_probe,
static struct platform_driver mt7620_pinctrl_driver = {
.probe = mt7620_pinctrl_probe,
.driver = {
.name = "rt2880-pinmux",
.of_match_table = mt7620_pinmux_match,
.name = "mt7620-pinctrl",
.of_match_table = mt7620_pinctrl_match,
},
};
static int __init mt7620_pinmux_init(void)
static int __init mt7620_pinctrl_init(void)
{
return platform_driver_register(&mt7620_pinmux_driver);
return platform_driver_register(&mt7620_pinctrl_driver);
}
core_initcall_sync(mt7620_pinmux_init);
core_initcall_sync(mt7620_pinctrl_init);

76
drivers/pinctrl/ralink/pinctrl-mt7621.c
View File

@ -3,7 +3,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinmux.h"
#include "pinctrl-ralink.h"
#define MT7621_GPIO_MODE_UART1 1
#define MT7621_GPIO_MODE_I2C 2
@ -34,83 +34,83 @@
#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
#define MT7621_GPIO_MODE_SDHCI_GPIO 1
static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
static struct rt2880_pmx_func uart3_grp[] = {
static struct ralink_pmx_func uart1_func[] = { FUNC("uart1", 0, 1, 2) };
static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 3, 2) };
static struct ralink_pmx_func uart3_func[] = {
FUNC("uart3", 0, 5, 4),
FUNC("i2s", 2, 5, 4),
FUNC("spdif3", 3, 5, 4),
};
static struct rt2880_pmx_func uart2_grp[] = {
static struct ralink_pmx_func uart2_func[] = {
FUNC("uart2", 0, 9, 4),
FUNC("pcm", 2, 9, 4),
FUNC("spdif2", 3, 9, 4),
};
static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
static struct rt2880_pmx_func wdt_grp[] = {
static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 13, 5) };
static struct ralink_pmx_func wdt_func[] = {
FUNC("wdt rst", 0, 18, 1),
FUNC("wdt refclk", 2, 18, 1),
};
static struct rt2880_pmx_func pcie_rst_grp[] = {
static struct ralink_pmx_func pcie_rst_func[] = {
FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
};
static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
static struct rt2880_pmx_func spi_grp[] = {
static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 20, 2) };
static struct ralink_pmx_func rgmii2_func[] = { FUNC("rgmii2", 0, 22, 12) };
static struct ralink_pmx_func spi_func[] = {
FUNC("spi", 0, 34, 7),
FUNC("nand1", 2, 34, 7),
};
static struct rt2880_pmx_func sdhci_grp[] = {
static struct ralink_pmx_func sdhci_func[] = {
FUNC("sdhci", 0, 41, 8),
FUNC("nand2", 2, 41, 8),
};
static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
static struct ralink_pmx_func rgmii1_func[] = { FUNC("rgmii1", 0, 49, 12) };
static struct rt2880_pmx_group mt7621_pinmux_data[] = {
GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
static struct ralink_pmx_group mt7621_pinmux_data[] = {
GRP("uart1", uart1_func, 1, MT7621_GPIO_MODE_UART1),
GRP("i2c", i2c_func, 1, MT7621_GPIO_MODE_I2C),
GRP_G("uart3", uart3_func, MT7621_GPIO_MODE_UART3_MASK,
MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
GRP_G("uart2", uart2_func, MT7621_GPIO_MODE_UART2_MASK,
MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
GRP("jtag", jtag_func, 1, MT7621_GPIO_MODE_JTAG),
GRP_G("wdt", wdt_func, MT7621_GPIO_MODE_WDT_MASK,
MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
GRP_G("pcie", pcie_rst_func, MT7621_GPIO_MODE_PCIE_MASK,
MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
GRP_G("mdio", mdio_func, MT7621_GPIO_MODE_MDIO_MASK,
MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
GRP("rgmii2", rgmii2_func, 1, MT7621_GPIO_MODE_RGMII2),
GRP_G("spi", spi_func, MT7621_GPIO_MODE_SPI_MASK,
MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
GRP_G("sdhci", sdhci_func, MT7621_GPIO_MODE_SDHCI_MASK,
MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
GRP("rgmii1", rgmii1_func, 1, MT7621_GPIO_MODE_RGMII1),
{ 0 }
};
static int mt7621_pinmux_probe(struct platform_device *pdev)
static int mt7621_pinctrl_probe(struct platform_device *pdev)
{
return rt2880_pinmux_init(pdev, mt7621_pinmux_data);
return ralink_pinctrl_init(pdev, mt7621_pinmux_data);
}
static const struct of_device_id mt7621_pinmux_match[] = {
{ .compatible = "ralink,rt2880-pinmux" },
static const struct of_device_id mt7621_pinctrl_match[] = {
{ .compatible = "ralink,mt7621-pinctrl" },
{}
};
MODULE_DEVICE_TABLE(of, mt7621_pinmux_match);
MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match);
static struct platform_driver mt7621_pinmux_driver = {
.probe = mt7621_pinmux_probe,
static struct platform_driver mt7621_pinctrl_driver = {
.probe = mt7621_pinctrl_probe,
.driver = {
.name = "rt2880-pinmux",
.of_match_table = mt7621_pinmux_match,
.name = "mt7621-pinctrl",
.of_match_table = mt7621_pinctrl_match,
},
};
static int __init mt7621_pinmux_init(void)
static int __init mt7621_pinctrl_init(void)
{
return platform_driver_register(&mt7621_pinmux_driver);
return platform_driver_register(&mt7621_pinctrl_driver);
}
core_initcall_sync(mt7621_pinmux_init);
core_initcall_sync(mt7621_pinctrl_init);

349
drivers/pinctrl/ralink/pinctrl-ralink.c Normal file
View File

@ -0,0 +1,349 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7620.h>
#include "pinctrl-ralink.h"
#include "../core.h"
#include "../pinctrl-utils.h"
#define SYSC_REG_GPIO_MODE 0x60
#define SYSC_REG_GPIO_MODE2 0x64
struct ralink_priv {
struct device *dev;
struct pinctrl_pin_desc *pads;
struct pinctrl_desc *desc;
struct ralink_pmx_func **func;
int func_count;
struct ralink_pmx_group *groups;
const char **group_names;
int group_count;
u8 *gpio;
int max_pins;
};
static int ralink_get_group_count(struct pinctrl_dev *pctrldev)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->group_count;
}
static const char *ralink_get_group_name(struct pinctrl_dev *pctrldev,
unsigned int group)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return (group >= p->group_count) ? NULL : p->group_names[group];
}
static int ralink_get_group_pins(struct pinctrl_dev *pctrldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (group >= p->group_count)
return -EINVAL;
*pins = p->groups[group].func[0].pins;
*num_pins = p->groups[group].func[0].pin_count;
return 0;
}
static const struct pinctrl_ops ralink_pctrl_ops = {
.get_groups_count = ralink_get_group_count,
.get_group_name = ralink_get_group_name,
.get_group_pins = ralink_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static int ralink_pmx_func_count(struct pinctrl_dev *pctrldev)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->func_count;
}
static const char *ralink_pmx_func_name(struct pinctrl_dev *pctrldev,
unsigned int func)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->func[func]->name;
}
static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
unsigned int func,
const char * const **groups,
unsigned int * const num_groups)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (p->func[func]->group_count == 1)
*groups = &p->group_names[p->func[func]->groups[0]];
else
*groups = p->group_names;
*num_groups = p->func[func]->group_count;
return 0;
}
static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev,
unsigned int func, unsigned int group)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
u32 mode = 0;
u32 reg = SYSC_REG_GPIO_MODE;
int i;
int shift;
/* dont allow double use */
if (p->groups[group].enabled) {
dev_err(p->dev, "%s is already enabled\n",
p->groups[group].name);
return 0;
}
p->groups[group].enabled = 1;
p->func[func]->enabled = 1;
shift = p->groups[group].shift;
if (shift >= 32) {
shift -= 32;
reg = SYSC_REG_GPIO_MODE2;
}
mode = rt_sysc_r32(reg);
mode &= ~(p->groups[group].mask << shift);
/* mark the pins as gpio */
for (i = 0; i < p->groups[group].func[0].pin_count; i++)
p->gpio[p->groups[group].func[0].pins[i]] = 1;
/* function 0 is gpio and needs special handling */
if (func == 0) {
mode |= p->groups[group].gpio << shift;
} else {
for (i = 0; i < p->func[func]->pin_count; i++)
p->gpio[p->func[func]->pins[i]] = 0;
mode |= p->func[func]->value << shift;
}
rt_sysc_w32(mode, reg);
return 0;
}
static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (!p->gpio[pin]) {
dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
return -EINVAL;
}
return 0;
}
static const struct pinmux_ops ralink_pmx_group_ops = {
.get_functions_count = ralink_pmx_func_count,
.get_function_name = ralink_pmx_func_name,
.get_function_groups = ralink_pmx_group_get_groups,
.set_mux = ralink_pmx_group_enable,
.gpio_request_enable = ralink_pmx_group_gpio_request_enable,
};
static struct pinctrl_desc ralink_pctrl_desc = {
.owner = THIS_MODULE,
.name = "ralink-pinctrl",
.pctlops = &ralink_pctrl_ops,
.pmxops = &ralink_pmx_group_ops,
};
static struct ralink_pmx_func gpio_func = {
.name = "gpio",
};
static int ralink_pinctrl_index(struct ralink_priv *p)
{
struct ralink_pmx_group *mux = p->groups;
int i, j, c = 0;
/* count the mux functions */
while (mux->name) {
p->group_count++;
mux++;
}
/* allocate the group names array needed by the gpio function */
p->group_names = devm_kcalloc(p->dev, p->group_count,
sizeof(char *), GFP_KERNEL);
if (!p->group_names)
return -ENOMEM;
for (i = 0; i < p->group_count; i++) {
p->group_names[i] = p->groups[i].name;
p->func_count += p->groups[i].func_count;
}
/* we have a dummy function[0] for gpio */
p->func_count++;
/* allocate our function and group mapping index buffers */
p->func = devm_kcalloc(p->dev, p->func_count,
sizeof(*p->func), GFP_KERNEL);
gpio_func.groups = devm_kcalloc(p->dev, p->group_count, sizeof(int),
GFP_KERNEL);
if (!p->func || !gpio_func.groups)
return -ENOMEM;
/* add a backpointer to the function so it knows its group */
gpio_func.group_count = p->group_count;
for (i = 0; i < gpio_func.group_count; i++)
gpio_func.groups[i] = i;
p->func[c] = &gpio_func;
c++;
/* add remaining functions */
for (i = 0; i < p->group_count; i++) {
for (j = 0; j < p->groups[i].func_count; j++) {
p->func[c] = &p->groups[i].func[j];
p->func[c]->groups = devm_kzalloc(p->dev, sizeof(int),
GFP_KERNEL);
if (!p->func[c]->groups)
return -ENOMEM;
p->func[c]->groups[0] = i;
p->func[c]->group_count = 1;
c++;
}
}
return 0;
}
static int ralink_pinctrl_pins(struct ralink_priv *p)
{
int i, j;
/*
* loop over the functions and initialize the pins array.
* also work out the highest pin used.
*/
for (i = 0; i < p->func_count; i++) {
int pin;
if (!p->func[i]->pin_count)
continue;
p->func[i]->pins = devm_kcalloc(p->dev,
p->func[i]->pin_count,
sizeof(int),
GFP_KERNEL);
for (j = 0; j < p->func[i]->pin_count; j++)
p->func[i]->pins[j] = p->func[i]->pin_first + j;
pin = p->func[i]->pin_first + p->func[i]->pin_count;
if (pin > p->max_pins)
p->max_pins = pin;
}
/* the buffer that tells us which pins are gpio */
p->gpio = devm_kcalloc(p->dev, p->max_pins, sizeof(u8), GFP_KERNEL);
/* the pads needed to tell pinctrl about our pins */
p->pads = devm_kcalloc(p->dev, p->max_pins,
sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
if (!p->pads || !p->gpio)
return -ENOMEM;
memset(p->gpio, 1, sizeof(u8) * p->max_pins);
for (i = 0; i < p->func_count; i++) {
if (!p->func[i]->pin_count)
continue;
for (j = 0; j < p->func[i]->pin_count; j++)
p->gpio[p->func[i]->pins[j]] = 0;
}
/* pin 0 is always a gpio */
p->gpio[0] = 1;
/* set the pads */
for (i = 0; i < p->max_pins; i++) {
/* strlen("ioXY") + 1 = 5 */
char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
if (!name)
return -ENOMEM;
snprintf(name, 5, "io%d", i);
p->pads[i].number = i;
p->pads[i].name = name;
}
p->desc->pins = p->pads;
p->desc->npins = p->max_pins;
return 0;
}
int ralink_pinctrl_init(struct platform_device *pdev,
struct ralink_pmx_group *data)
{
struct ralink_priv *p;
struct pinctrl_dev *dev;
int err;
if (!data)
return -ENOTSUPP;
/* setup the private data */
p = devm_kzalloc(&pdev->dev, sizeof(struct ralink_priv), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->dev = &pdev->dev;
p->desc = &ralink_pctrl_desc;
p->groups = data;
platform_set_drvdata(pdev, p);
/* init the device */
err = ralink_pinctrl_index(p);
if (err) {
dev_err(&pdev->dev, "failed to load index\n");
return err;
}
err = ralink_pinctrl_pins(p);
if (err) {
dev_err(&pdev->dev, "failed to load pins\n");
return err;
}
dev = pinctrl_register(p->desc, &pdev->dev, p);
return PTR_ERR_OR_ZERO(dev);
}

16
drivers/pinctrl/ralink/pinmux.h → drivers/pinctrl/ralink/pinctrl-ralink.h
View File

@ -3,8 +3,8 @@
* Copyright (C) 2012 John Crispin <john@phrozen.org>
*/
#ifndef _RT288X_PINMUX_H__
#define _RT288X_PINMUX_H__
#ifndef _PINCTRL_RALINK_H__
#define _PINCTRL_RALINK_H__
#define FUNC(name, value, pin_first, pin_count) \
{ name, value, pin_first, pin_count }
@ -19,9 +19,9 @@
.func = _func, .gpio = _gpio, \
.func_count = ARRAY_SIZE(_func) }
struct rt2880_pmx_group;
struct ralink_pmx_group;
struct rt2880_pmx_func {
struct ralink_pmx_func {
const char *name;
const char value;
@ -35,7 +35,7 @@ struct rt2880_pmx_func {
int enabled;
};
struct rt2880_pmx_group {
struct ralink_pmx_group {
const char *name;
int enabled;
@ -43,11 +43,11 @@ struct rt2880_pmx_group {
const char mask;
const char gpio;
struct rt2880_pmx_func *func;
struct ralink_pmx_func *func;
int func_count;
};
int rt2880_pinmux_init(struct platform_device *pdev,
struct rt2880_pmx_group *data);
int ralink_pinctrl_init(struct platform_device *pdev,
struct ralink_pmx_group *data);
#endif

375
drivers/pinctrl/ralink/pinctrl-rt2880.c
View File

@ -1,349 +1,60 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
*/
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include "pinctrl-ralink.h"
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7620.h>
#define RT2880_GPIO_MODE_I2C BIT(0)
#define RT2880_GPIO_MODE_UART0 BIT(1)
#define RT2880_GPIO_MODE_SPI BIT(2)
#define RT2880_GPIO_MODE_UART1 BIT(3)
#define RT2880_GPIO_MODE_JTAG BIT(4)
#define RT2880_GPIO_MODE_MDIO BIT(5)
#define RT2880_GPIO_MODE_SDRAM BIT(6)
#define RT2880_GPIO_MODE_PCI BIT(7)
#include "pinmux.h"
#include "../core.h"
#include "../pinctrl-utils.h"
static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
static struct ralink_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
static struct ralink_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
#define SYSC_REG_GPIO_MODE 0x60
#define SYSC_REG_GPIO_MODE2 0x64
struct rt2880_priv {
struct device *dev;
struct pinctrl_pin_desc *pads;
struct pinctrl_desc *desc;
struct rt2880_pmx_func **func;
int func_count;
struct rt2880_pmx_group *groups;
const char **group_names;
int group_count;
u8 *gpio;
int max_pins;
static struct ralink_pmx_group rt2880_pinmux_data_act[] = {
GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
{ 0 }
};
static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
static int rt2880_pinctrl_probe(struct platform_device *pdev)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->group_count;
return ralink_pinctrl_init(pdev, rt2880_pinmux_data_act);
}
static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
unsigned int group)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
static const struct of_device_id rt2880_pinctrl_match[] = {
{ .compatible = "ralink,rt2880-pinctrl" },
{}
};
MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match);
return (group >= p->group_count) ? NULL : p->group_names[group];
}
static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (group >= p->group_count)
return -EINVAL;
*pins = p->groups[group].func[0].pins;
*num_pins = p->groups[group].func[0].pin_count;
return 0;
}
static const struct pinctrl_ops rt2880_pctrl_ops = {
.get_groups_count = rt2880_get_group_count,
.get_group_name = rt2880_get_group_name,
.get_group_pins = rt2880_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
static struct platform_driver rt2880_pinctrl_driver = {
.probe = rt2880_pinctrl_probe,
.driver = {
.name = "rt2880-pinctrl",
.of_match_table = rt2880_pinctrl_match,
},
};
static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
static int __init rt2880_pinctrl_init(void)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->func_count;
}
static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
unsigned int func)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->func[func]->name;
}
static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
unsigned int func,
const char * const **groups,
unsigned int * const num_groups)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (p->func[func]->group_count == 1)
*groups = &p->group_names[p->func[func]->groups[0]];
else
*groups = p->group_names;
*num_groups = p->func[func]->group_count;
return 0;
}
static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
unsigned int func, unsigned int group)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
u32 mode = 0;
u32 reg = SYSC_REG_GPIO_MODE;
int i;
int shift;
/* dont allow double use */
if (p->groups[group].enabled) {
dev_err(p->dev, "%s is already enabled\n",
p->groups[group].name);
return 0;
}
p->groups[group].enabled = 1;
p->func[func]->enabled = 1;
shift = p->groups[group].shift;
if (shift >= 32) {
shift -= 32;
reg = SYSC_REG_GPIO_MODE2;
}
mode = rt_sysc_r32(reg);
mode &= ~(p->groups[group].mask << shift);
/* mark the pins as gpio */
for (i = 0; i < p->groups[group].func[0].pin_count; i++)
p->gpio[p->groups[group].func[0].pins[i]] = 1;
/* function 0 is gpio and needs special handling */
if (func == 0) {
mode |= p->groups[group].gpio << shift;
} else {
for (i = 0; i < p->func[func]->pin_count; i++)
p->gpio[p->func[func]->pins[i]] = 0;
mode |= p->func[func]->value << shift;
}
rt_sysc_w32(mode, reg);
return 0;
}
static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (!p->gpio[pin]) {
dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
return -EINVAL;
}
return 0;
}
static const struct pinmux_ops rt2880_pmx_group_ops = {
.get_functions_count = rt2880_pmx_func_count,
.get_function_name = rt2880_pmx_func_name,
.get_function_groups = rt2880_pmx_group_get_groups,
.set_mux = rt2880_pmx_group_enable,
.gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
};
static struct pinctrl_desc rt2880_pctrl_desc = {
.owner = THIS_MODULE,
.name = "rt2880-pinmux",
.pctlops = &rt2880_pctrl_ops,
.pmxops = &rt2880_pmx_group_ops,
};
static struct rt2880_pmx_func gpio_func = {
.name = "gpio",
};
static int rt2880_pinmux_index(struct rt2880_priv *p)
{
struct rt2880_pmx_group *mux = p->groups;
int i, j, c = 0;
/* count the mux functions */
while (mux->name) {
p->group_count++;
mux++;
}
/* allocate the group names array needed by the gpio function */
p->group_names = devm_kcalloc(p->dev, p->group_count,
sizeof(char *), GFP_KERNEL);
if (!p->group_names)
return -ENOMEM;
for (i = 0; i < p->group_count; i++) {
p->group_names[i] = p->groups[i].name;
p->func_count += p->groups[i].func_count;
}
/* we have a dummy function[0] for gpio */
p->func_count++;
/* allocate our function and group mapping index buffers */
p->func = devm_kcalloc(p->dev, p->func_count,
sizeof(*p->func), GFP_KERNEL);
gpio_func.groups = devm_kcalloc(p->dev, p->group_count, sizeof(int),
GFP_KERNEL);
if (!p->func || !gpio_func.groups)
return -ENOMEM;
/* add a backpointer to the function so it knows its group */
gpio_func.group_count = p->group_count;
for (i = 0; i < gpio_func.group_count; i++)
gpio_func.groups[i] = i;
p->func[c] = &gpio_func;
c++;
/* add remaining functions */
for (i = 0; i < p->group_count; i++) {
for (j = 0; j < p->groups[i].func_count; j++) {
p->func[c] = &p->groups[i].func[j];
p->func[c]->groups = devm_kzalloc(p->dev, sizeof(int),
GFP_KERNEL);
if (!p->func[c]->groups)
return -ENOMEM;
p->func[c]->groups[0] = i;
p->func[c]->group_count = 1;
c++;
}
}
return 0;
}
static int rt2880_pinmux_pins(struct rt2880_priv *p)
{
int i, j;
/*
* loop over the functions and initialize the pins array.
* also work out the highest pin used.
*/
for (i = 0; i < p->func_count; i++) {
int pin;
if (!p->func[i]->pin_count)
continue;
p->func[i]->pins = devm_kcalloc(p->dev,
p->func[i]->pin_count,
sizeof(int),
GFP_KERNEL);
for (j = 0; j < p->func[i]->pin_count; j++)
p->func[i]->pins[j] = p->func[i]->pin_first + j;
pin = p->func[i]->pin_first + p->func[i]->pin_count;
if (pin > p->max_pins)
p->max_pins = pin;
}
/* the buffer that tells us which pins are gpio */
p->gpio = devm_kcalloc(p->dev, p->max_pins, sizeof(u8), GFP_KERNEL);
/* the pads needed to tell pinctrl about our pins */
p->pads = devm_kcalloc(p->dev, p->max_pins,
sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
if (!p->pads || !p->gpio)
return -ENOMEM;
memset(p->gpio, 1, sizeof(u8) * p->max_pins);
for (i = 0; i < p->func_count; i++) {
if (!p->func[i]->pin_count)
continue;
for (j = 0; j < p->func[i]->pin_count; j++)
p->gpio[p->func[i]->pins[j]] = 0;
}
/* pin 0 is always a gpio */
p->gpio[0] = 1;
/* set the pads */
for (i = 0; i < p->max_pins; i++) {
/* strlen("ioXY") + 1 = 5 */
char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
if (!name)
return -ENOMEM;
snprintf(name, 5, "io%d", i);
p->pads[i].number = i;
p->pads[i].name = name;
}
p->desc->pins = p->pads;
p->desc->npins = p->max_pins;
return 0;
}
int rt2880_pinmux_init(struct platform_device *pdev,
struct rt2880_pmx_group *data)
{
struct rt2880_priv *p;
struct pinctrl_dev *dev;
int err;
if (!data)
return -ENOTSUPP;
/* setup the private data */
p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->dev = &pdev->dev;
p->desc = &rt2880_pctrl_desc;
p->groups = data;
platform_set_drvdata(pdev, p);
/* init the device */
err = rt2880_pinmux_index(p);
if (err) {
dev_err(&pdev->dev, "failed to load index\n");
return err;
}
err = rt2880_pinmux_pins(p);
if (err) {
dev_err(&pdev->dev, "failed to load pins\n");
return err;
}
dev = pinctrl_register(p->desc, &pdev->dev, p);
return PTR_ERR_OR_ZERO(dev);
return platform_driver_register(&rt2880_pinctrl_driver);
}
core_initcall_sync(rt2880_pinctrl_init);

60
drivers/pinctrl/ralink/pinctrl-rt288x.c
View File

@ -1,60 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinmux.h"
#define RT2880_GPIO_MODE_I2C BIT(0)
#define RT2880_GPIO_MODE_UART0 BIT(1)
#define RT2880_GPIO_MODE_SPI BIT(2)
#define RT2880_GPIO_MODE_UART1 BIT(3)
#define RT2880_GPIO_MODE_JTAG BIT(4)
#define RT2880_GPIO_MODE_MDIO BIT(5)
#define RT2880_GPIO_MODE_SDRAM BIT(6)
#define RT2880_GPIO_MODE_PCI BIT(7)
static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
{ 0 }
};
static int rt288x_pinmux_probe(struct platform_device *pdev)
{
return rt2880_pinmux_init(pdev, rt2880_pinmux_data_act);
}
static const struct of_device_id rt288x_pinmux_match[] = {
{ .compatible = "ralink,rt2880-pinmux" },
{}
};
MODULE_DEVICE_TABLE(of, rt288x_pinmux_match);
static struct platform_driver rt288x_pinmux_driver = {
.probe = rt288x_pinmux_probe,
.driver = {
.name = "rt2880-pinmux",
.of_match_table = rt288x_pinmux_match,
},
};
static int __init rt288x_pinmux_init(void)
{
return platform_driver_register(&rt288x_pinmux_driver);
}
core_initcall_sync(rt288x_pinmux_init);

66
drivers/pinctrl/ralink/pinctrl-rt305x.c
View File

@ -5,7 +5,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinmux.h"
#include "pinctrl-ralink.h"
#define RT305X_GPIO_MODE_UART0_SHIFT 2
#define RT305X_GPIO_MODE_UART0_MASK 0x7
@ -31,9 +31,9 @@
#define RT3352_GPIO_MODE_LNA 18
#define RT3352_GPIO_MODE_PA 20
static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct rt2880_pmx_func uartf_func[] = {
static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct ralink_pmx_func uartf_func[] = {
FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
@ -42,28 +42,28 @@ static struct rt2880_pmx_func uartf_func[] = {
FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
};
static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
static struct rt2880_pmx_func rt5350_cs1_func[] = {
static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
static struct ralink_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
static struct ralink_pmx_func rt5350_cs1_func[] = {
FUNC("spi_cs1", 0, 27, 1),
FUNC("wdg_cs1", 1, 27, 1),
};
static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
static struct rt2880_pmx_func rt3352_rgmii_func[] = {
static struct ralink_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
static struct ralink_pmx_func rt3352_rgmii_func[] = {
FUNC("rgmii", 0, 24, 12)
};
static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
static struct rt2880_pmx_func rt3352_cs1_func[] = {
static struct ralink_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
static struct ralink_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
static struct ralink_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
static struct ralink_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
static struct ralink_pmx_func rt3352_cs1_func[] = {
FUNC("spi_cs1", 0, 45, 1),
FUNC("wdg_cs1", 1, 45, 1),
};
static struct rt2880_pmx_group rt3050_pinmux_data[] = {
static struct ralink_pmx_group rt3050_pinmux_data[] = {
GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
@ -76,7 +76,7 @@ static struct rt2880_pmx_group rt3050_pinmux_data[] = {
{ 0 }
};
static struct rt2880_pmx_group rt3352_pinmux_data[] = {
static struct ralink_pmx_group rt3352_pinmux_data[] = {
GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
@ -92,7 +92,7 @@ static struct rt2880_pmx_group rt3352_pinmux_data[] = {
{ 0 }
};
static struct rt2880_pmx_group rt5350_pinmux_data[] = {
static struct ralink_pmx_group rt5350_pinmux_data[] = {
GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
@ -104,34 +104,34 @@ static struct rt2880_pmx_group rt5350_pinmux_data[] = {
{ 0 }
};
static int rt305x_pinmux_probe(struct platform_device *pdev)
static int rt305x_pinctrl_probe(struct platform_device *pdev)
{
if (soc_is_rt5350())
return rt2880_pinmux_init(pdev, rt5350_pinmux_data);
return ralink_pinctrl_init(pdev, rt5350_pinmux_data);
else if (soc_is_rt305x() || soc_is_rt3350())
return rt2880_pinmux_init(pdev, rt3050_pinmux_data);
return ralink_pinctrl_init(pdev, rt3050_pinmux_data);
else if (soc_is_rt3352())
return rt2880_pinmux_init(pdev, rt3352_pinmux_data);
return ralink_pinctrl_init(pdev, rt3352_pinmux_data);
else
return -EINVAL;
}
static const struct of_device_id rt305x_pinmux_match[] = {
{ .compatible = "ralink,rt2880-pinmux" },
static const struct of_device_id rt305x_pinctrl_match[] = {
{ .compatible = "ralink,rt305x-pinctrl" },
{}
};
MODULE_DEVICE_TABLE(of, rt305x_pinmux_match);
MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match);
static struct platform_driver rt305x_pinmux_driver = {
.probe = rt305x_pinmux_probe,
static struct platform_driver rt305x_pinctrl_driver = {
.probe = rt305x_pinctrl_probe,
.driver = {
.name = "rt2880-pinmux",
.of_match_table = rt305x_pinmux_match,
.name = "rt305x-pinctrl",
.of_match_table = rt305x_pinctrl_match,
},
};
static int __init rt305x_pinmux_init(void)
static int __init rt305x_pinctrl_init(void)
{
return platform_driver_register(&rt305x_pinmux_driver);
return platform_driver_register(&rt305x_pinctrl_driver);
}
core_initcall_sync(rt305x_pinmux_init);
core_initcall_sync(rt305x_pinctrl_init);

50
drivers/pinctrl/ralink/pinctrl-rt3883.c
View File

@ -3,7 +3,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinmux.h"
#include "pinctrl-ralink.h"
#define RT3883_GPIO_MODE_UART0_SHIFT 2
#define RT3883_GPIO_MODE_UART0_MASK 0x7
@ -39,9 +39,9 @@
#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct rt2880_pmx_func uartf_func[] = {
static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct ralink_pmx_func uartf_func[] = {
FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
@ -50,21 +50,21 @@ static struct rt2880_pmx_func uartf_func[] = {
FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
};
static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
static struct rt2880_pmx_func pci_func[] = {
static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
static struct ralink_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
static struct ralink_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
static struct ralink_pmx_func pci_func[] = {
FUNC("pci-dev", 0, 40, 32),
FUNC("pci-host2", 1, 40, 32),
FUNC("pci-host1", 2, 40, 32),
FUNC("pci-fnc", 3, 40, 32)
};
static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) };
static struct ralink_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
static struct ralink_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) };
static struct rt2880_pmx_group rt3883_pinmux_data[] = {
static struct ralink_pmx_group rt3883_pinmux_data[] = {
GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
@ -81,27 +81,27 @@ static struct rt2880_pmx_group rt3883_pinmux_data[] = {
{ 0 }
};
static int rt3883_pinmux_probe(struct platform_device *pdev)
static int rt3883_pinctrl_probe(struct platform_device *pdev)
{
return rt2880_pinmux_init(pdev, rt3883_pinmux_data);
return ralink_pinctrl_init(pdev, rt3883_pinmux_data);
}
static const struct of_device_id rt3883_pinmux_match[] = {
{ .compatible = "ralink,rt2880-pinmux" },
static const struct of_device_id rt3883_pinctrl_match[] = {
{ .compatible = "ralink,rt3883-pinctrl" },
{}
};
MODULE_DEVICE_TABLE(of, rt3883_pinmux_match);
MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match);
static struct platform_driver rt3883_pinmux_driver = {
.probe = rt3883_pinmux_probe,
static struct platform_driver rt3883_pinctrl_driver = {
.probe = rt3883_pinctrl_probe,
.driver = {
.name = "rt2880-pinmux",
.of_match_table = rt3883_pinmux_match,
.name = "rt3883-pinctrl",
.of_match_table = rt3883_pinctrl_match,
},
};
static int __init rt3883_pinmux_init(void)
static int __init rt3883_pinctrl_init(void)
{
return platform_driver_register(&rt3883_pinmux_driver);
return platform_driver_register(&rt3883_pinctrl_driver);
}
core_initcall_sync(rt3883_pinmux_init);
core_initcall_sync(rt3883_pinctrl_init);

7
drivers/pinctrl/renesas/Kconfig
View File

@ -38,8 +38,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
select PINCTRL_RZG2L if ARCH_R9A07G044
select PINCTRL_RZG2L if ARCH_R9A07G054
select PINCTRL_RZG2L if ARCH_RZG2L
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@ -184,14 +183,14 @@ config PINCTRL_RZA2
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZG2L
bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST
bool "pin control support for RZ/{G2L,G2UL,V2L}" if COMPILE_TEST
depends on OF
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L}
This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L}
platforms.
config PINCTRL_PFC_R8A77470

117
drivers/pinctrl/renesas/core.c
View File

@ -13,10 +13,11 @@
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/math.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
@ -71,12 +72,11 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc,
/* Fill them. */
for (i = 0; i < num_windows; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
windows->phys = res->start;
windows->size = resource_size(res);
windows->virt = devm_ioremap_resource(pfc->dev, res);
windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res);
if (IS_ERR(windows->virt))
return -ENOMEM;
windows->phys = res->start;
windows->size = resource_size(res);
windows++;
}
for (i = 0; i < num_irqs; i++)
@ -214,7 +214,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
*maskp = (1 << crp->var_field_width[in_pos]) - 1;
*posp = crp->reg_width;
for (k = 0; k <= in_pos; k++)
*posp -= crp->var_field_width[k];
*posp -= abs(crp->var_field_width[k]);
}
}
@ -262,14 +262,17 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
if (!r_width)
break;
for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) {
u32 ncomb;
u32 n;
if (f_width)
if (f_width) {
curr_width = f_width;
else
curr_width = config_reg->var_field_width[m];
} else {
curr_width = abs(config_reg->var_field_width[m]);
if (config_reg->var_field_width[m] < 0)
continue;
}
ncomb = 1 << curr_width;
for (n = 0; n < ncomb; n++) {
@ -281,7 +284,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
}
}
pos += ncomb;
m++;
}
k++;
}
@ -875,7 +877,8 @@ static const struct sh_pfc_pin __init *sh_pfc_find_pin(
static void __init sh_pfc_check_cfg_reg(const char *drvname,
const struct pinmux_cfg_reg *cfg_reg)
{
unsigned int i, n, rw, fw;
unsigned int i, n, rw, r;
int fw;
sh_pfc_check_reg(drvname, cfg_reg->reg,
GENMASK(cfg_reg->reg_width - 1, 0));
@ -883,16 +886,29 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname,
if (cfg_reg->field_width) {
fw = cfg_reg->field_width;
n = (cfg_reg->reg_width / fw) << fw;
for (i = 0, r = 0; i < n; i += 1 << fw) {
if (is0s(&cfg_reg->enum_ids[i], 1 << fw))
r++;
}
if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw)
sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n",
cfg_reg->reg);
/* Skip field checks (done at build time) */
goto check_enum_ids;
}
for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw))
sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
cfg_reg->reg, rw, rw + fw - 1);
n += 1 << fw;
rw += fw;
if (fw < 0) {
rw += -fw;
} else {
if (is0s(&cfg_reg->enum_ids[n], 1 << fw))
sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n",
cfg_reg->reg, rw, rw + fw - 1);
n += 1 << fw;
rw += fw;
}
}
if (rw != cfg_reg->reg_width)
@ -1007,7 +1023,18 @@ static void __init sh_pfc_compare_groups(const char *drvname,
static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
{
const struct pinmux_drive_reg *drive_regs = info->drive_regs;
#define drive_nfields ARRAY_SIZE(drive_regs->fields)
#define drive_ofs(i) drive_regs[(i) / drive_nfields]
#define drive_reg(i) drive_ofs(i).reg
#define drive_bit(i) ((i) % drive_nfields)
#define drive_field(i) drive_ofs(i).fields[drive_bit(i)]
const struct pinmux_bias_reg *bias_regs = info->bias_regs;
#define bias_npins ARRAY_SIZE(bias_regs->pins)
#define bias_ofs(i) bias_regs[(i) / bias_npins]
#define bias_puen(i) bias_ofs(i).puen
#define bias_pud(i) bias_ofs(i).pud
#define bias_bit(i) ((i) % bias_npins)
#define bias_pin(i) bias_ofs(i).pins[bias_bit(i)]
const char *drvname = info->name;
unsigned int *refcnts;
unsigned int i, j, k;
@ -1076,17 +1103,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
if (!drive_regs) {
sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
} else {
for (j = 0; drive_regs[j / 8].reg; j++) {
if (!drive_regs[j / 8].fields[j % 8].pin &&
!drive_regs[j / 8].fields[j % 8].offset &&
!drive_regs[j / 8].fields[j % 8].size)
for (j = 0; drive_reg(j); j++) {
if (!drive_field(j).pin &&
!drive_field(j).offset &&
!drive_field(j).size)
continue;
if (drive_regs[j / 8].fields[j % 8].pin == pin->pin)
if (drive_field(j).pin == pin->pin)
break;
}
if (!drive_regs[j / 8].reg)
if (!drive_reg(j))
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
pin->name);
}
@ -1164,20 +1191,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
for (i = 0; drive_regs && drive_regs[i].reg; i++)
sh_pfc_check_drive_reg(info, &drive_regs[i]);
for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) {
if (!drive_regs[i / 8].fields[i % 8].pin &&
!drive_regs[i / 8].fields[i % 8].offset &&
!drive_regs[i / 8].fields[i % 8].size)
for (i = 0; drive_regs && drive_reg(i); i++) {
if (!drive_field(i).pin && !drive_field(i).offset &&
!drive_field(i).size)
continue;
for (j = 0; j < i; j++) {
if (drive_regs[i / 8].fields[i % 8].pin ==
drive_regs[j / 8].fields[j % 8].pin &&
drive_regs[j / 8].fields[j % 8].offset &&
drive_regs[j / 8].fields[j % 8].size) {
sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n",
drive_regs[i / 8].reg, i % 8,
drive_regs[j / 8].reg, j % 8);
if (drive_field(i).pin == drive_field(j).pin &&
drive_field(j).offset && drive_field(j).size) {
sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
drive_reg(i), drive_bit(i),
drive_reg(j), drive_bit(j));
}
}
}
@ -1186,26 +1210,23 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
sh_pfc_check_bias_reg(info, &bias_regs[i]);
for (i = 0; bias_regs &&
(bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) {
if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE)
for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {
if (bias_pin(i) == SH_PFC_PIN_NONE)
continue;
for (j = 0; j < i; j++) {
if (bias_regs[i / 32].pins[i % 32] !=
bias_regs[j / 32].pins[j % 32])
if (bias_pin(i) != bias_pin(j))
continue;
if (bias_regs[i / 32].puen && bias_regs[j / 32].puen)
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
bias_regs[i / 32].puen, i % 32,
bias_regs[j / 32].puen, j % 32);
if (bias_regs[i / 32].pud && bias_regs[j / 32].pud)
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
bias_regs[i / 32].pud, i % 32,
bias_regs[j / 32].pud, j % 32);
if (bias_puen(i) && bias_puen(j))
sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
bias_puen(i), bias_bit(i),
bias_puen(j), bias_bit(j));
if (bias_pud(i) && bias_pud(j))
sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
bias_pud(i), bias_bit(i),
bias_pud(j), bias_bit(j));
}
}
/* Check ioctrl registers */

1
drivers/pinctrl/renesas/gpio.c
View File

@ -8,7 +8,6 @@
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/slab.h>

60
drivers/pinctrl/renesas/pfc-emev2.c
View File

@ -4,7 +4,6 @@
*
* Copyright (C) 2015 Niklas Söderlund
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
@ -1570,61 +1569,39 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
2, 2),
GROUP(-20, 2, 2, -6, 2),
GROUP(
/* 31 - 12 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* 31 - 12 RESERVED */
/* 11 - 10 */
FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
FN_SEL_LCD3_11_10_10, 0,
/* 9 - 8 */
FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
/* 7 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 7 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(-30, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 31 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(-30, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 31 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(-18, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* 31 - 14 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* 31 - 14 RESERVED */
/* 13 - 12 */
FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
/* 11 - 10 */
@ -1644,14 +1621,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
2, 2, 2),
GROUP(-22, 2, 2, 2, 2, 2),
GROUP(
/* 31 - 10 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 31 - 10 RESERVED */
/* 9 - 8 */
FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
/* 7 - 6 */
@ -1665,15 +1637,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(-30, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 31 - 2 RESERVED */
/* 1 - 0 */
FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
))

58
drivers/pinctrl/renesas/pfc-r8a73a4.c
View File

@ -2270,15 +2270,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL1CR_00_0, MSEL1CR_00_1,
))
},
{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
{ PINMUX_CFG_REG_VAR("MSEL3CR", 0xe6058020, 32,
GROUP(1, -2, 1, 1, 1, -2, 1, 1, 1, 1, 1, 1,
1, 1, 1, -2, 1, 1, 1, 1, -2, 1, -2, 1,
-1, 1, 1),
GROUP(
MSEL3CR_31_0, MSEL3CR_31_1,
0, 0,
0, 0,
/* RESERVED [2] */
MSEL3CR_28_0, MSEL3CR_28_1,
MSEL3CR_27_0, MSEL3CR_27_1,
MSEL3CR_26_0, MSEL3CR_26_1,
0, 0,
0, 0,
/* RESERVED [2] */
MSEL3CR_23_0, MSEL3CR_23_1,
MSEL3CR_22_0, MSEL3CR_22_1,
MSEL3CR_21_0, MSEL3CR_21_1,
@ -2288,19 +2290,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL3CR_17_0, MSEL3CR_17_1,
MSEL3CR_16_0, MSEL3CR_16_1,
MSEL3CR_15_0, MSEL3CR_15_1,
0, 0,
0, 0,
/* RESERVED [2] */
MSEL3CR_12_0, MSEL3CR_12_1,
MSEL3CR_11_0, MSEL3CR_11_1,
MSEL3CR_10_0, MSEL3CR_10_1,
MSEL3CR_09_0, MSEL3CR_09_1,
0, 0,
0, 0,
/* RESERVED [2] */
MSEL3CR_06_0, MSEL3CR_06_1,
0, 0,
0, 0,
/* RESERVED [2] */
MSEL3CR_03_0, MSEL3CR_03_1,
0, 0,
/* RESERVED [1] */
MSEL3CR_01_0, MSEL3CR_01_1,
MSEL3CR_00_0, MSEL3CR_00_1,
))
@ -2375,37 +2374,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
))
},
{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("MSEL8CR", 0xe6058034, 32,
GROUP(-15, 1, -14, 1, 1),
GROUP(
/* RESERVED [15] */
MSEL8CR_16_0, MSEL8CR_16_1,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
/* RESERVED [14] */
MSEL8CR_01_0, MSEL8CR_01_1,
MSEL8CR_00_0, MSEL8CR_00_1,
))

74
drivers/pinctrl/renesas/pfc-r8a7740.c
View File

@ -3250,89 +3250,93 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(210, 0xe60530d2), /* PORT210CR */
PORTCR(211, 0xe60530d3), /* PORT211CR */
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
{ PINMUX_CFG_REG_VAR("MSEL1CR", 0xe605800c, 32,
GROUP(1, 1, 1, 1, 1, 1, -9, 1, 1, 1, 1, 1,
-2, 1, -1, 1, 1, 1, 1, 1, 1, -1, 1),
GROUP(
MSEL1CR_31_0, MSEL1CR_31_1,
MSEL1CR_30_0, MSEL1CR_30_1,
MSEL1CR_29_0, MSEL1CR_29_1,
MSEL1CR_28_0, MSEL1CR_28_1,
MSEL1CR_27_0, MSEL1CR_27_1,
MSEL1CR_26_0, MSEL1CR_26_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED [9] */
MSEL1CR_16_0, MSEL1CR_16_1,
MSEL1CR_15_0, MSEL1CR_15_1,
MSEL1CR_14_0, MSEL1CR_14_1,
MSEL1CR_13_0, MSEL1CR_13_1,
MSEL1CR_12_0, MSEL1CR_12_1,
0, 0, 0, 0,
/* RESERVED [2] */
MSEL1CR_9_0, MSEL1CR_9_1,
0, 0,
/* RESERVED [1] */
MSEL1CR_7_0, MSEL1CR_7_1,
MSEL1CR_6_0, MSEL1CR_6_1,
MSEL1CR_5_0, MSEL1CR_5_1,
MSEL1CR_4_0, MSEL1CR_4_1,
MSEL1CR_3_0, MSEL1CR_3_1,
MSEL1CR_2_0, MSEL1CR_2_1,
0, 0,
/* RESERVED [1] */
MSEL1CR_0_0, MSEL1CR_0_1,
))
},
{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
{ PINMUX_CFG_REG_VAR("MSEL3CR", 0xE6058020, 32,
GROUP(-16, 1, -8, 1, -6),
GROUP(
/* RESERVED [16] */
MSEL3CR_15_0, MSEL3CR_15_1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED [8] */
MSEL3CR_6_0, MSEL3CR_6_1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* RESERVED [6] */
))
},
{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
{ PINMUX_CFG_REG_VAR("MSEL4CR", 0xE6058024, 32,
GROUP(-12, 1, 1, -2, 1, -4, 1, -3, 1, -1, 1, -2,
1, -1),
GROUP(
/* RESERVED [12] */
MSEL4CR_19_0, MSEL4CR_19_1,
MSEL4CR_18_0, MSEL4CR_18_1,
0, 0, 0, 0,
/* RESERVED [2] */
MSEL4CR_15_0, MSEL4CR_15_1,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED [4] */
MSEL4CR_10_0, MSEL4CR_10_1,
0, 0, 0, 0, 0, 0,
/* RESERVED [3] */
MSEL4CR_6_0, MSEL4CR_6_1,
0, 0,
/* RESERVED [1] */
MSEL4CR_4_0, MSEL4CR_4_1,
0, 0, 0, 0,
/* RESERVED [2] */
MSEL4CR_1_0, MSEL4CR_1_1,
0, 0,
/* RESERVED [1] */
))
},
{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
{ PINMUX_CFG_REG_VAR("MSEL5CR", 0xE6058028, 32,
GROUP(1, 1, 1, -1, 1, -1, 1, -1, 1, -1, 1,
-1, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1,
-1, 1, 1, 1, 1, 1, 1, 1, -1, 1),
GROUP(
MSEL5CR_31_0, MSEL5CR_31_1,
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_27_0, MSEL5CR_27_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_25_0, MSEL5CR_25_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_23_0, MSEL5CR_23_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_21_0, MSEL5CR_21_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_19_0, MSEL5CR_19_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_17_0, MSEL5CR_17_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_15_0, MSEL5CR_15_1,
MSEL5CR_14_0, MSEL5CR_14_1,
MSEL5CR_13_0, MSEL5CR_13_1,
MSEL5CR_12_0, MSEL5CR_12_1,
MSEL5CR_11_0, MSEL5CR_11_1,
MSEL5CR_10_0, MSEL5CR_10_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_8_0, MSEL5CR_8_1,
MSEL5CR_7_0, MSEL5CR_7_1,
MSEL5CR_6_0, MSEL5CR_6_1,
@ -3340,7 +3344,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL5CR_4_0, MSEL5CR_4_1,
MSEL5CR_3_0, MSEL5CR_3_1,
MSEL5CR_2_0, MSEL5CR_2_1,
0, 0,
/* RESERVED [1] */
MSEL5CR_0_0, MSEL5CR_0_1,
))
},

176
drivers/pinctrl/renesas/pfc-r8a77470.c
View File

@ -2485,16 +2485,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR0", 0xE6060004, 32,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP0_31_23 RESERVED */
GP_0_22_FN, FN_MMC0_D7,
GP_0_21_FN, FN_MMC0_D6,
GP_0_20_FN, FN_IP1_7_4,
@ -2519,16 +2514,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_1_FN, FN_USB0_OVC,
GP_0_0_FN, FN_USB0_PWEN, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP1_31_23 RESERVED */
GP_1_22_FN, FN_IP4_3_0,
GP_1_21_FN, FN_IP3_31_28,
GP_1_20_FN, FN_IP3_27_24,
@ -2587,22 +2577,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, FN_IP4_11_8,
GP_2_0_FN, FN_IP4_7_4, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR3", 0xE6060010, 32,
GROUP(-2, 1, 1, -10, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP3_31_30 RESERVED */
GP_3_29_FN, FN_IP10_19_16,
GP_3_28_FN, FN_IP10_15_12,
GP_3_27_FN, FN_IP10_11_8,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
/* GP3_26_17 RESERVED */
GP_3_16_FN, FN_IP10_7_4,
GP_3_15_FN, FN_IP10_3_0,
GP_3_14_FN, FN_IP9_31_28,
@ -2689,9 +2672,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_IP14_3_0,
GP_5_0_FN, FN_IP13_31_28, ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR0", 0xE6060040, 32, 4, GROUP(
/* IP0_31_28 [4] */
FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2717,9 +2698,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR1", 0xE6060044, 32, 4, GROUP(
/* IP1_31_28 [4] */
FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2745,9 +2724,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR2", 0xE6060048, 32, 4, GROUP(
/* IP2_31_28 [4] */
FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@ -2773,9 +2750,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR3", 0xE606004C, 32, 4, GROUP(
/* IP3_31_28 [4] */
FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
@ -2802,9 +2777,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, FN_AVB_AVTP_CAPTURE_A,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR4", 0xE6060050, 32, 4, GROUP(
/* IP4_31_28 [4] */
FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2830,9 +2803,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR5", 0xE6060054, 32, 4, GROUP(
/* IP5_31_28 [4] */
FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@ -2858,9 +2829,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR6", 0xE6060058, 32, 4, GROUP(
/* IP6_31_28 [4] */
FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@ -2886,9 +2855,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR7", 0xE606005C, 32, 4, GROUP(
/* IP7_31_28 [4] */
FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@ -2914,9 +2881,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR8", 0xE6060060, 32, 4, GROUP(
/* IP8_31_28 [4] */
FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@ -2942,9 +2907,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR9", 0xE6060064, 32, 4, GROUP(
/* IP9_31_28 [4] */
FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@ -2970,9 +2933,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR10", 0xE6060068, 32, 4, GROUP(
/* IP10_31_28 [4] */
FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -2999,9 +2960,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR11", 0xE606006C, 32, 4, GROUP(
/* IP11_31_28 [4] */
FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3031,9 +2990,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR12", 0xE6060070, 32, 4, GROUP(
/* IP12_31_28 [4] */
FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3059,9 +3016,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR13", 0xE6060074, 32, 4, GROUP(
/* IP13_31_28 [4] */
FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@ -3088,9 +3043,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR14", 0xE6060078, 32, 4, GROUP(
/* IP14_31_28 [4] */
FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3116,9 +3069,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR15", 0xE606007C, 32, 4, GROUP(
/* IP15_31_28 [4] */
FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@ -3144,9 +3095,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
{ PINMUX_CFG_REG("IPSR16", 0xE6060080, 32, 4, GROUP(
/* IP16_31_28 [4] */
FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3174,10 +3123,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP17_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_31_28 [4] RESERVED */
/* IP17_27_24 [4] */
FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3201,25 +3149,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
3, 3, 1, 2, 3, 3, 1),
GROUP(-5, 2, -2, 2, 2, 2, -1,
3, 3, -1, 2, 3, 3, 1),
GROUP(
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [5] */
/* SEL_ADGA [2] */
FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [2] */
/* SEL_CANCLK [2] */
FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
FN_SEL_CANCLK_3,
@ -3228,7 +3164,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_CAN0 [2] */
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
/* RESERVED [1] */
0, 0,
/* SEL_I2C04 [3] */
FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
FN_SEL_I2C04_4, 0, 0, 0,
@ -3236,7 +3171,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
FN_SEL_I2C03_4, 0, 0, 0,
/* RESERVED [1] */
0, 0,
/* SEL_I2C02 [2] */
FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
/* SEL_I2C01 [3] */
@ -3249,8 +3183,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_AVB_0, FN_SEL_AVB_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
1, 1, 2, 1, 1, 2, 2, 1),
GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, -1, 1, -1,
1, 1, -2, 1, 1, -2, 2, 1),
GROUP(
/* SEL_SCIFCLK [1] */
FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
@ -3273,52 +3207,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_MSIOF2 [2] */
FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
/* RESERVED [1] */
0, 0,
/* SEL_MSIOF1 [1] */
FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
/* RESERVED [1] */
0, 0,
/* SEL_MSIOF0 [1] */
FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
/* SEL_RCN [1] */
FN_SEL_RCN_0, FN_SEL_RCN_1,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_TMU2 [1] */
FN_SEL_TMU2_0, FN_SEL_TMU2_1,
/* SEL_TMU1 [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_HSCIF1 [2] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
/* SEL_HSCIF0 [1] */
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(-10, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [10] */
/* SEL_ADGB [2] */
FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
/* SEL_ADGC [2] */

98
drivers/pinctrl/renesas/pfc-r8a7778.c
View File

@ -2240,11 +2240,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
GROUP(-1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_31 [1] RESERVED */
/* IP0_30 [1] */
FN_A19, 0,
/* IP0_29 [1] */
@ -2296,13 +2295,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
GROUP(-2, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
3, 1, 1),
GROUP(
/* IP1_31 [1] */
0, 0,
/* IP1_30 [1] */
0, 0,
/* IP1_31_30 [2] RESERVED */
/* IP1_29_28 [2] */
FN_EX_CS1, FN_MMC_D4, 0, 0,
/* IP1_27_25 [3] */
@ -2437,11 +2433,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
GROUP(-1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
3, 3, 1),
GROUP(
/* IP4_31 [1] */
0, 0,
/* IP4_31 [1] RESERVED */
/* IP4_30_29 [2] */
FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0,
/* IP4_28_27 [2] */
@ -2481,12 +2476,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
GROUP(-1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
1, 2, 2, 2),
GROUP(
/* IP5_31 [1] */
0, 0,
/* IP5_31 [1] RESERVED */
/* IP5_30_29 [2] */
FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B,
/* IP5_28_26 [3] */
@ -2619,12 +2613,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
GROUP(-2, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30 [1] */
0, 0,
/* IP8_31_30 [2] RESERVED */
/* IP8_29_27 [3] */
FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5,
0, FN_HRX1_B, 0, 0,
@ -2660,12 +2651,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP9_31 [1] */
0, 0,
/* IP9_30 [1] */
0, 0,
/* IP9_31_30 [2] RESERVED */
/* IP9_29_27 [3] */
FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC,
FN_ETH_RXD1, FN_FMIN_C,
@ -2703,24 +2691,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
3, 3, 3),
GROUP(-7, 3, 3, 3, 3, 4, 3, 3, 3),
GROUP(
/* IP10_31 [1] */
0, 0,
/* IP10_30 [1] */
0, 0,
/* IP10_29 [1] */
0, 0,
/* IP10_28 [1] */
0, 0,
/* IP10_27 [1] */
0, 0,
/* IP10_26 [1] */
0, 0,
/* IP10_25 [1] */
0, 0,
/* IP10_31_25 [7] RESERVED */
/* IP10_24_22 [3] */
FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B,
FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0,
@ -2754,12 +2728,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
GROUP(-1, 1, 2, 2, 3, 2, 2, -1, 1, 1, 1, 2,
-1, 1, 1, 1, 2, 1, -1, 1, 1, 1, 1, 1),
GROUP(
/* SEL 31 [1] */
0, 0,
/* SEL 31 [1] RESERVED */
/* SEL_30 (SCIF5) [1] */
FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
/* SEL_29_28 (SCIF4) [2] */
@ -2779,8 +2752,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_20_19 (SCIF0) [2] */
FN_SEL_SCIF0_A, FN_SEL_SCIF0_B,
FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
/* SEL_18 [1] */
0, 0,
/* SEL_18 [1] RESERVED */
/* SEL_17 (SSI2) [1] */
FN_SEL_SSI2_A, FN_SEL_SSI2_B,
/* SEL_16 (SSI1) [1] */
@ -2790,8 +2762,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_14_13 (VI0) [2] */
FN_SEL_VI0_A, FN_SEL_VI0_B,
FN_SEL_VI0_C, FN_SEL_VI0_D,
/* SEL_12 [1] */
0, 0,
/* SEL_12 [1] RESERVED */
/* SEL_11 (SD2) [1] */
FN_SEL_SD2_A, FN_SEL_SD2_B,
/* SEL_10 (SD1) [1] */
@ -2803,8 +2774,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_IRQ2_C, 0,
/* SEL_6 (IRQ1) [1] */
FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
/* SEL_5 [1] */
0, 0,
/* SEL_5 [1] RESERVED */
/* SEL_4 (DREQ2) [1] */
FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
/* SEL_3 (DREQ1) [1] */
@ -2818,18 +2788,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
GROUP(-4, 1, 1, 2, 1, 1, -7,
2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
GROUP(
/* SEL_31 [1] */
0, 0,
/* SEL_30 [1] */
0, 0,
/* SEL_29 [1] */
0, 0,
/* SEL_28 [1] */
0, 0,
/* SEL_31_28 [4] RESERVED */
/* SEL_27 (CAN1) [1] */
FN_SEL_CAN1_A, FN_SEL_CAN1_B,
/* SEL_26 (CAN0) [1] */
@ -2841,20 +2804,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
/* SEL_22 (HSCIF0) [1] */
FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
/* SEL_21 [1] */
0, 0,
/* SEL_20 [1] */
0, 0,
/* SEL_19 [1] */
0, 0,
/* SEL_18 [1] */
0, 0,
/* SEL_17 [1] */
0, 0,
/* SEL_16 [1] */
0, 0,
/* SEL_15 [1] */
0, 0,
/* SEL_21_15 [7] RESERVED */
/* SEL_14_13 (REMOCON) [2] */
FN_SEL_REMOCON_A, FN_SEL_REMOCON_B,
FN_SEL_REMOCON_C, 0,

82
drivers/pinctrl/renesas/pfc-r8a7779.c
View File

@ -3300,13 +3300,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_A2,
GP_5_0_FN, FN_A1 ))
},
{ PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR6", 0xfffc001c, 32,
GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP6_31_9 RESERVED */
GP_6_8_FN, FN_IP3_20,
GP_6_7_FN, FN_IP3_19,
GP_6_6_FN, FN_IP3_18,
@ -3319,10 +3316,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
GROUP(1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(-1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_31 [1] RESERVED */
/* IP0_30_28 [3] */
FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
FN_HRTS1, FN_RX4_C, 0, 0,
@ -3358,10 +3354,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCIF_CLK, FN_TCLK0_C, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
GROUP(3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
GROUP(-3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
GROUP(
/* IP1_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_31_29 [3] RESERVED */
/* IP1_28_25 [4] */
FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
@ -3397,10 +3392,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
GROUP(1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
GROUP(-1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
GROUP(
/* IP2_31 [1] */
0, 0,
/* IP2_31 [1] RESERVED */
/* IP2_30_28 [3] */
FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
FN_AUDATA2, 0, 0, 0,
@ -3545,11 +3539,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
GROUP(1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
GROUP(-1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
1, 1, 1, 1, 3),
GROUP(
/* IP5_31 [1] */
0, 0,
/* IP5_31 [1] RESERVED */
/* IP5_30_29 [2] */
FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
/* IP5_28 [1] */
@ -3592,15 +3585,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_RX5, FN_RTS0_D_TANS_D, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
GROUP(1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
GROUP(-1, 2, -2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
2, 2, 2),
GROUP(
/* IP6_31 [1] */
0, 0,
/* IP6_31 [1] RESERVED */
/* IP6_30_29 [2] */
FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
/* IP_28_27 [2] */
0, 0, 0, 0,
/* IP_28_27 [2] RESERVED */
/* IP6_26_25 [2] */
FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
/* IP6_24_23 [2] */
@ -3631,11 +3622,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
GROUP(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
GROUP(-1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
3, 2, 2),
GROUP(
/* IP7_31 [1] */
0, 0,
/* IP7_31 [1] RESERVED */
/* IP7_30_29 [2] */
FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
/* IP7_28_27 [2] */
@ -3669,10 +3659,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
GROUP(1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
GROUP(-1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_31 [1] RESERVED */
/* IP8_30_28 [3] */
FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
FN_PWMFSW0_C, 0, 0, 0,
@ -3713,11 +3702,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
GROUP(2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
GROUP(-2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
1, 1, 1, 2, 2),
GROUP(
/* IP9_31_30 [2] */
0, 0, 0, 0,
/* IP9_31_30 [2] RESERVED */
/* IP9_29_28 [2] */
FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
/* IP9_27_26 [2] */
@ -3790,10 +3778,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP11_31_30 [2] */
0, 0, 0, 0,
/* IP11_31_30 [2] RESERVED */
/* IP11_29_27 [3] */
FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
@ -3826,19 +3813,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ADICLK_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
GROUP(4, 4, 4, 2, 3, 3, 3, 3, 3, 3),
GROUP(-14, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP12_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_23_20 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_19_18 [2] */
0, 0, 0, 0,
/* IP12_31_18 [14] RESERVED */
/* IP12_17_15 [3] */
FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
FN_SCK4_B, 0, 0, 0,
@ -3904,7 +3881,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, 2, 2, 2,
GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, -6,
2, 1, 1, 2, 1, 2, 2),
GROUP(
/* SEL_TMU1 [2] */
@ -3926,12 +3903,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
/* SEL_ADI [1] */
FN_SEL_ADI_0, FN_SEL_ADI_1,
/* [2] */
0, 0, 0, 0,
/* [2] */
0, 0, 0, 0,
/* [2] */
0, 0, 0, 0,
/* [6] RESERVED */
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
/* SEL_SIM [1] */

110
drivers/pinctrl/renesas/pfc-r8a7790.c
View File

@ -5122,10 +5122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_0_FN, FN_IP14_21_19 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
GROUP(-1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_31 [1] RESERVED */
/* IP0_30_27 [4] */
FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
@ -5159,10 +5158,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
GROUP(-2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
GROUP(
/* IP1_31_30 [2] */
0, 0, 0, 0,
/* IP1_31_30 [2] RESERVED */
/* IP1_29_28 [2] */
FN_A1, FN_PWM4, 0, 0,
/* IP1_27_26 [2] */
@ -5197,10 +5195,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
GROUP(-3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP2_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_31_29 [3] RESERVED */
/* IP2_28_26 [3] */
FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
@ -5261,10 +5258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP4_31_30 [2] */
0, 0, 0, 0,
/* IP4_31_30 [2] RESERVED */
/* IP4_29_27 [3] */
FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
@ -5295,10 +5291,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
GROUP(-2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
GROUP(
/* IP5_31_30 [2] */
0, 0, 0, 0,
/* IP5_31_30 [2] RESERVED */
/* IP5_29_27 [3] */
FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
@ -5368,10 +5363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
GROUP(-1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
GROUP(
/* IP7_31 [1] */
0, 0,
/* IP7_31 [1] RESERVED */
/* IP7_30_29 [2] */
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
/* IP7_28_27 [2] */
@ -5404,11 +5398,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
GROUP(-1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_31 [1] RESERVED */
/* IP8_30_29 [2] */
FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
/* IP8_28 [1] */
@ -5482,10 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
GROUP(-2, 4, 3, 4, 4, 4, 4, 3, 4),
GROUP(
/* IP10_31_30 [2] */
0, 0, 0, 0,
/* IP10_31_30 [2] RESERVED */
/* IP10_29_26 [4] */
FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
@ -5558,10 +5550,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
GROUP(
/* IP12_31 [1] */
0, 0,
/* IP12_31 [1] RESERVED */
/* IP12_30_28 [3] */
FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
@ -5598,10 +5589,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
GROUP(-1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_31 [1] RESERVED */
/* IP13_30_29 [2] */
FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
/* IP13_28_26 [3] */
@ -5635,10 +5625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
GROUP(-1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
GROUP(
/* IP14_30 [1] */
0, 0,
/* IP14_30 [1] RESERVED */
/* IP14_30_28 [3] */
FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
@ -5674,10 +5663,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_REMOCON, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_31_30 [2] RESERVED */
/* IP15_29_28 [2] */
FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
/* IP15_27_26 [2] */
@ -5710,26 +5698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
GROUP(-24, 1, 1, 3, 3),
GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_23_20 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_19_16 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_15_12 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_11_8 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_31_8 [24] RESERVED */
/* IP16_7 [1] */
FN_USB1_OVC, FN_TCLK1_B,
/* IP16_6 [1] */
@ -5743,7 +5714,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
1, 1, 1, 2, 1, 1, 2, 1, 1),
1, 1, 1, 2, -1, 1, 2, 1, 1),
GROUP(
/* SEL_SCIF1 [3] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
@ -5782,7 +5753,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_TSIF1 [2] */
FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
/* RESERVED [1] */
0, 0,
/* SEL_LBS [1] */
FN_SEL_LBS_0, FN_SEL_LBS_1,
/* SEL_TSIF0 [2] */
@ -5793,11 +5763,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
3, 3, 2, 3, 2, 2),
GROUP(-3, 1, 1, 1, 2, 1, 2, 1, -2, 1, 1, 1,
3, 3, 2, -3, 2, 2),
GROUP(
/* RESERVED [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_TMU1 [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* SEL_HSCIF1 [1] */
@ -5813,7 +5782,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_CAN1 [1] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_SCIF2 [1] */
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
/* SEL_ADI [1] */
@ -5829,36 +5797,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
/* RESERVED [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_SIM [2] */
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
/* SEL_SSI8 [2] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
GROUP(1, 1, -12, 2, -6, 3, 2, 3, 2),
GROUP(
/* SEL_IICDVFS [1] */
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
/* SEL_IIC0 [1] */
FN_SEL_IIC0_0, FN_SEL_IIC0_1,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [12] */
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* RESERVED [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [6] */
/* SEL_IIC2 [3] */
FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
FN_SEL_IIC2_4, 0, 0, 0,

111
drivers/pinctrl/renesas/pfc-r8a7791.c
View File

@ -5686,11 +5686,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_0_FN, FN_IP15_17_15 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
GROUP(-1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_31 [1] RESERVED */
/* IP0_30_29 [2] */
FN_A6, FN_MSIOF1_SCK,
0, 0,
@ -5783,10 +5782,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
GROUP(-2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
GROUP(
/* IP2_31_30 [2] */
0, 0, 0, 0,
/* IP2_31_30 [2] RESERVED */
/* IP2_29_27 [3] */
FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
FN_ATAG0_N, 0, FN_EX_WAIT1,
@ -5820,10 +5818,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(-1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(
/* IP3_31 [1] */
0, 0,
/* IP3_31 [1] RESERVED */
/* IP3_30_28 [3] */
FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
@ -5859,11 +5856,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
GROUP(-1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
3, 3, 2),
GROUP(
/* IP4_31 [1] */
0, 0,
/* IP4_31 [1] RESERVED */
/* IP4_30_28 [3] */
FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
@ -5943,10 +5939,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(-2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(
/* IP6_31_30 [2] */
0, 0, 0, 0,
/* IP6_31_30 [2] RESERVED */
/* IP6_29_27 [3] */
FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
FN_GPS_SIGN_C, FN_GPS_SIGN_D,
@ -5984,10 +5979,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
GROUP(-2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
GROUP(
/* IP7_31_30 [2] */
0, 0, 0, 0,
/* IP7_31_30 [2] RESERVED */
/* IP7_29_27 [3] */
FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
FN_SCIFA1_SCK, FN_SSI_SCK78_B,
@ -6026,10 +6020,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(-1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_31 [1] RESERVED */
/* IP8_30_28 [3] */
FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
0, 0, 0,
@ -6201,10 +6194,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_I2C1_SDA_D, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
GROUP(-2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_31_30 [2] RESERVED */
/* IP12_29_27 [3] */
FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
@ -6243,11 +6235,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
GROUP(-1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
1, 1, 1, 3, 2, 2, 3),
GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_31 [1] RESERVED */
/* IP13_30_28 [3] */
FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
0, 0, 0, 0,
@ -6340,10 +6331,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_31_30 [2] RESERVED */
/* IP15_29_27 [3] */
FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
FN_CAN0_TX_B, FN_VI1_DATA5_C,
@ -6382,23 +6372,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
GROUP(-20, 2, 2, 2, 3, 3),
GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_23_20 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_19_16 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_15_12 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED [20] */
/* IP16_11_10 [2] */
FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
/* IP16_9_8 [2] */
@ -6415,11 +6391,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
2, 2, 1, 2, 2, 2),
GROUP(-1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, -2,
2, -2, 1, 2, 2, 2),
GROUP(
/* RESERVED [1] */
0, 0,
/* SEL_SCIF1 [2] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
/* SEL_SCIFB [2] */
@ -6446,11 +6421,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_VI1 [2] */
FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_TMU [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* SEL_LBS [2] */
@ -6461,15 +6434,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
1, 2, 2, 2, 1, 1, 1),
GROUP(3, -1, 1, 3, 2, -1, 1, 2, -2, 1, 3, 2,
-1, 2, 2, 2, 1, -1, 1),
GROUP(
/* SEL_SCIF0 [3] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
0, 0, 0,
/* RESERVED [1] */
0, 0,
/* SEL_SCIF [1] */
FN_SEL_SCIF_0, FN_SEL_SCIF_1,
/* SEL_CAN0 [3] */
@ -6479,13 +6451,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_CAN1 [2] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
/* RESERVED [1] */
0, 0,
/* SEL_SCIFA2 [1] */
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
/* SEL_SCIF4 [2] */
FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_ADG [1] */
FN_SEL_ADG_0, FN_SEL_ADG_1,
/* SEL_FM [3] */
@ -6495,7 +6465,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SCIFA5 [2] */
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
/* RESERVED [1] */
0, 0,
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
/* SEL_SCIFA4 [2] */
@ -6505,13 +6474,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SIM [1] */
FN_SEL_SIM_0, FN_SEL_SIM_1,
/* RESERVED [1] */
0, 0,
/* SEL_SSI8 [1] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
3, 2, 2, 2, 1),
GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, -2, 2,
3, 2, -5),
GROUP(
/* SEL_HSCIF2 [2] */
FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
@ -6536,7 +6504,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SCIF5 [1] */
FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_I2C2 [2] */
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
/* SEL_I2C1 [3] */
@ -6545,16 +6512,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* SEL_I2C0 [2] */
FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [1] */
0, 0, ))
/* RESERVED [5] */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
1, 1, 2, 2, 2, 2),
GROUP(3, 2, 2, -1, 1, 1, 1, 3, -4, 3, -1,
1, 1, 2, -6),
GROUP(
/* SEL_SOF1 [3] */
FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
@ -6565,7 +6527,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_DIS [2] */
FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
/* RESERVED [1] */
0, 0,
/* SEL_RAD [1] */
FN_SEL_RAD_0, FN_SEL_RAD_1,
/* SEL_RCN [1] */
@ -6577,27 +6538,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_SOF2 [3] */
FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
FN_SEL_SOF2_3, FN_SEL_SOF2_4,
0, 0, 0,
/* RESERVED [1] */
0, 0,
/* SEL_SSI1 [1] */
FN_SEL_SSI1_0, FN_SEL_SSI1_1,
/* SEL_SSI0 [1] */
FN_SEL_SSI0_0, FN_SEL_SSI0_1,
/* SEL_SSP [2] */
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0, ))
/* RESERVED [6] */ ))
},
{ },
};

231
drivers/pinctrl/renesas/pfc-r8a7792.c
View File

@ -1999,16 +1999,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_1_FN, FN_IP0_1,
GP_0_0_FN, FN_IP0_0 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP1_31_23 RESERVED */
GP_1_22_FN, FN_DU1_CDE,
GP_1_21_FN, FN_DU1_DISP,
GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
@ -2101,22 +2096,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, FN_A17,
GP_3_0_FN, FN_A16 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_17 RESERVED */
GP_4_16_FN, FN_VI0_FIELD,
GP_4_15_FN, FN_VI0_D11_G3_Y3,
GP_4_14_FN, FN_VI0_D10_G2_Y2,
@ -2135,22 +2119,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, FN_VI0_CLKENB,
GP_4_0_FN, FN_VI0_CLK ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP5_31_17 RESERVED */
GP_5_16_FN, FN_VI1_FIELD,
GP_5_15_FN, FN_VI1_D11_G3_Y3,
GP_5_14_FN, FN_VI1_D10_G2_Y2,
@ -2169,22 +2142,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_1_FN, FN_VI1_CLKENB,
GP_5_0_FN, FN_VI1_CLK ))
},
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP6_31_17 RESERVED */
GP_6_16_FN, FN_IP2_16,
GP_6_15_FN, FN_IP2_15,
GP_6_14_FN, FN_IP2_14,
@ -2203,22 +2165,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, FN_IP2_1,
GP_6_0_FN, FN_IP2_0 ))
},
{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP7_31_17 RESERVED */
GP_7_16_FN, FN_VI3_FIELD,
GP_7_15_FN, FN_IP3_14,
GP_7_14_FN, FN_VI3_D10_Y2,
@ -2237,22 +2188,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_1_FN, FN_IP3_1,
GP_7_0_FN, FN_IP3_0 ))
},
{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP8_31_17 RESERVED */
GP_8_16_FN, FN_IP4_24,
GP_8_15_FN, FN_IP4_23,
GP_8_14_FN, FN_IP4_22,
@ -2271,22 +2211,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_8_1_FN, FN_IP4_0,
GP_8_0_FN, FN_VI4_CLK ))
},
{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP9_31_17 RESERVED */
GP_9_16_FN, FN_VI5_FIELD,
GP_9_15_FN, FN_VI5_D11_Y3,
GP_9_14_FN, FN_VI5_D10_Y2,
@ -2374,15 +2303,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_11_0_FN, FN_IP7_1_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
GROUP(4, 4,
GROUP(-8,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP0_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_31_24 [8] RESERVED */
/* IP0_23 [1] */
FN_DU0_DB7_C5, 0,
/* IP0_22 [1] */
@ -2433,17 +2359,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DR0_DATA0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
GROUP(4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP1_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_23 [1] */
0, 0,
/* IP1_31_23 [9] RESERVED */
/* IP1_22 [1] */
FN_A25, FN_SSL,
/* IP1_21 [1] */
@ -2492,19 +2412,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
GROUP(4, 4,
4, 3, 1,
GROUP(-15, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP2_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_23_20 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_19_17 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_31_17 [15] RESERVED */
/* IP2_16 [1] */
FN_VI2_FIELD, FN_AVB_TXD2,
/* IP2_15 [1] */
@ -2541,21 +2453,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI2_CLK, FN_AVB_RX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
GROUP(4, 4,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP3_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_23_20 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_19_16 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_15 [1] */
0, 0,
/* IP3_31_15 [17] RESERVED */
/* IP3_14 [1] */
FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
/* IP3_13 [1] */
@ -2588,14 +2489,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI3_CLK, FN_AVB_TX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
GROUP(4, 3, 1,
1, 1, 1, 2, 2, 2,
GROUP(-7, 1, 1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 1, 2, 1, 1),
GROUP(
/* IP4_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_27_25 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_31_25 [7] RESERVED */
/* IP4_24 [1] */
FN_VI4_FIELD, FN_VI3_D15_Y7,
/* IP4_23 [1] */
@ -2630,21 +2527,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
GROUP(4, 4,
4, 4,
4, 1, 1, 1, 1,
GROUP(-20, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP5_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_23_20 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_19_16 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_15_12 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_31_12 [20] RESERVED */
/* IP5_11 [1] */
FN_VI5_D8_Y0, FN_VI1_D23_R7,
/* IP5_10 [1] */
@ -2671,19 +2557,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
GROUP(4, 4,
4, 1, 2, 1,
2, 2, 2, 2,
GROUP(-13, 2, 1, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP6_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_23_20 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_19 [1] */
0, 0,
/* IP6_31_19 [13] RESERVED */
/* IP6_18_17 [2] */
FN_DREQ1_N, FN_RX3, 0, 0,
/* IP6_16 [1] */
@ -2714,17 +2591,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MSIOF0_SCK, FN_HSCK0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
GROUP(4, 4,
3, 1, 1, 1, 1, 1,
GROUP(-11, 1, 1, 1, 1, 1,
2, 2, 2, 2,
1, 1, 2, 2, 2),
GROUP(
/* IP7_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_27_24 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_23_21 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_31_21 [11] RESERVED */
/* IP7_20 [1] */
FN_AUDIO_CLKB, 0,
/* IP7_19 [1] */

97
drivers/pinctrl/renesas/pfc-r8a7794.c
View File

@ -4867,7 +4867,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
1, 1, 1, 1, 2, -7, 1),
GROUP(
/* IP0_31_30 [2] */
FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
@ -4903,25 +4903,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MMC_CLK, FN_SD2_CLK,
/* IP0_9_8 [2] */
FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
/* IP0_7 [1] */
0, 0,
/* IP0_6 [1] */
0, 0,
/* IP0_5 [1] */
0, 0,
/* IP0_4 [1] */
0, 0,
/* IP0_3 [1] */
0, 0,
/* IP0_2 [1] */
0, 0,
/* IP0_1 [1] */
0, 0,
/* IP0_7_1 [7] RESERVED */
/* IP0_0 [1] */
FN_SD1_CD, FN_CAN0_RX, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
GROUP(2, 2, 1, 1, -1, 1, 2, 2, 2, 3, 2, 2,
3, 2, 2, 2, 2),
GROUP(
/* IP1_31_30 [2] */
@ -4932,8 +4919,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A4, FN_SCIFB0_TXD,
/* IP1_26 [1] */
FN_A3, FN_SCIFB0_SCK,
/* IP1_25 [1] */
0, 0,
/* IP1_25 [1] RESERVED */
/* IP1_24 [1] */
FN_A1, FN_SCIFB1_TXD,
/* IP1_23_22 [2] */
@ -5160,12 +5146,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(1, -1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP7_31 [1] */
FN_DREQ0_N, FN_SCIFB1_RXD,
/* IP7_30 [1] */
0, 0,
/* IP7_30 [1] RESERVED */
/* IP7_29_27 [3] */
FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
@ -5234,10 +5219,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
GROUP(-1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
GROUP(
/* IP9_31 [1] */
0, 0,
/* IP9_31 [1] RESERVED */
/* IP9_30_28 [3] */
FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
FN_SSI_SDATA1_B, 0, 0, 0,
@ -5307,10 +5291,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
GROUP(-2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
GROUP(
/* IP11_31_30 [2] */
0, 0, 0, 0,
/* IP11_31_30 [2] RESERVED */
/* IP11_29_27 [3] */
FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
0, 0, 0, 0,
@ -5343,10 +5326,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
GROUP(-2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_31_30 [2] RESERVED */
/* IP12_29_27 [3] */
FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
@ -5379,18 +5361,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, FN_DREQ1_N_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(-5, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30 [1] */
0, 0,
/* IP13_29 [1] */
0, 0,
/* IP13_28 [1] */
0, 0,
/* IP13_27 [1] */
0, 0,
/* IP13_31_27 [5] RESERVED */
/* IP13_26_24 [3] */
FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
@ -5420,23 +5393,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
GROUP(2, -1, 2, 3, -4, 1, -1,
3, 3, 3, 3, 3, 2, -1),
GROUP(
/* SEL_ADG [2] */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
/* RESERVED [1] */
0, 0,
/* SEL_CAN [2] */
FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
/* SEL_DARC [3] */
FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
FN_SEL_DARC_4, 0, 0, 0,
/* RESERVED [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_ETH [1] */
FN_SEL_ETH_0, FN_SEL_ETH_1,
/* RESERVED [1] */
0, 0,
/* SEL_IC200 [3] */
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
FN_SEL_I2C00_4, 0, 0, 0,
@ -5454,12 +5425,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C04_4, 0, 0, 0,
/* SEL_I2C05 [2] */
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
/* RESERVED [1] */
0, 0, ))
/* RESERVED [1] */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
2, 2, -1, 1, 2, 2, 2, 1, 1, -2),
GROUP(
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
@ -5493,7 +5463,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
FN_SEL_SCIFA5_3,
/* RESERVED [1] */
0, 0,
/* SEL_TMU [1] */
FN_SEL_TMU_0, FN_SEL_TMU_1,
/* SEL_TSIF0 [2] */
@ -5506,12 +5475,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
/* SEL_HSCIF1 [1] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
/* RESERVED [2] */
0, 0, 0, 0, ))
/* RESERVED [2] */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
1, 1, -12),
GROUP(
/* SEL_SCIF0 [2] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
@ -5542,30 +5510,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SSI8_0, FN_SEL_SSI8_1,
/* SEL_SSI9 [1] */
FN_SEL_SSI9_0, FN_SEL_SSI9_1,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0, ))
/* RESERVED [12] */ ))
},
{ },
};

170
drivers/pinctrl/renesas/pfc-r8a77950.c
View File

@ -4701,23 +4701,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@ -4769,24 +4757,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1),
GROUP(
/* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@ -4803,23 +4778,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@ -4837,21 +4800,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@ -4939,35 +4892,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
GROUP(-28, 1, 1, 1, 1),
GROUP(
/* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@ -5148,13 +5076,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP16_7_4
IP16_3_0 ))
},
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
/* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
{ PINMUX_CFG_REG_VAR("IPSR17", 0xe6060244, 32,
GROUP(-24, 4, 4),
GROUP(
/* IP17_31_8 RESERVED */
IP17_7_4
IP17_3_0 ))
},
@ -5164,10 +5089,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
GROUP(-1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
1, 1, 1, 1, 1, 1, 2, 2, 1, 2, -1),
GROUP(
0, 0, /* RESERVED 31 */
/* RESERVED 31 */
MOD_SEL0_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@ -5189,11 +5114,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_5_4
MOD_SEL0_3
MOD_SEL0_2_1
0, 0, /* RESERVED 0 */ ))
/* RESERVED 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@ -5210,7 +5135,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
0, 0, 0, 0, /* RESERVED 8, 7 */
/* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@ -5220,35 +5145,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
GROUP(1, 1, 1, -28, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
/* RESERVED 28 */
0, 0,
/* RESERVED 27, 26, 25, 24 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 23, 22, 21, 20 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 19, 18, 17, 16 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 15, 14, 13, 12 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 11, 10, 9, 8 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 7, 6, 5, 4 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3 */
0, 0,
/* RESERVED 2, 1 */
0, 0, 0, 0,
/* RESERVED 28-1 */
MOD_SEL2_0 ))
},
{ },

169
drivers/pinctrl/renesas/pfc-r8a77951.c
View File

@ -5139,23 +5139,11 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@ -5207,24 +5195,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1),
GROUP(
/* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@ -5241,23 +5216,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@ -5275,21 +5238,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@ -5377,35 +5330,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
GROUP(-28, 1, 1, 1, 1),
GROUP(
/* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@ -5486,12 +5414,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_7_4
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
@ -5596,13 +5526,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_7_4
IP17_3_0 ))
},
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
GROUP(-24, 4, 4),
GROUP(
/* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
@ -5612,8 +5539,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
1, 1, 1, 2, 2, 1, 2, 3),
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
@ -5625,7 +5552,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
0, 0, /* RESERVED 15 */
/* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@ -5634,12 +5561,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0 ))
/* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@ -5656,7 +5582,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
0, 0, 0, 0, /* RESERVED 8, 7 */
/* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@ -5666,8 +5592,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
1, 4, 4, 4, 3, 1),
GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
-16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
@ -5676,25 +5602,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_26
MOD_SEL2_25_24_23
/* RESERVED 22 */
0, 0,
MOD_SEL2_21
MOD_SEL2_20
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
/* RESERVED 16 */
0, 0,
/* RESERVED 15, 14, 13, 12 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 11, 10, 9, 8 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 7, 6, 5, 4 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ },

166
drivers/pinctrl/renesas/pfc-r8a7796.c
View File

@ -5094,23 +5094,11 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@ -5162,24 +5150,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1),
GROUP(
/* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@ -5196,23 +5171,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@ -5230,21 +5193,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@ -5332,35 +5285,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
GROUP(-28, 1, 1, 1, 1),
GROUP(
/* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@ -5441,12 +5369,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_7_4
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
@ -5551,13 +5481,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_7_4
IP17_3_0 ))
},
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
GROUP(-24, 4, 4),
GROUP(
/* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
@ -5567,8 +5494,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
1, 1, 1, 2, 2, 1, 2, 3),
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
@ -5580,7 +5507,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
0, 0, /* RESERVED 15 */
/* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@ -5589,12 +5516,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0 ))
/* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@ -5611,7 +5537,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
0, 0, 0, 0, /* RESERVED 8, 7 */
/* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@ -5622,7 +5548,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
1, 4, 4, 4, 3, 1),
-16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
@ -5636,19 +5562,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
/* RESERVED 16 */
0, 0,
/* RESERVED 15, 14, 13, 12 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 11, 10, 9, 8 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 7, 6, 5, 4 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ },

166
drivers/pinctrl/renesas/pfc-r8a77965.c
View File

@ -5335,23 +5335,11 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@ -5403,24 +5391,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1),
GROUP(
/* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@ -5437,23 +5412,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@ -5471,21 +5434,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@ -5573,35 +5526,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
GROUP(-28, 1, 1, 1, 1),
GROUP(
/* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@ -5682,12 +5610,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_7_4
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
@ -5792,13 +5722,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_7_4
IP17_3_0 ))
},
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
GROUP(-24, 4, 4),
GROUP(
/* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
@ -5808,8 +5735,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
1, 1, 1, 2, 2, 1, 2, 3),
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
@ -5821,7 +5748,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
0, 0, /* RESERVED 15 */
/* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@ -5830,12 +5757,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0 ))
/* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@ -5852,7 +5778,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
0, 0, 0, 0, /* RESERVED 8, 7 */
/* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@ -5863,7 +5789,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
1, 4, 4, 4, 3, 1),
-16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
@ -5877,19 +5803,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
/* RESERVED 16 */
0, 0,
/* RESERVED 15, 14, 13, 12 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 11, 10, 9, 8 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 7, 6, 5, 4 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ },

136
drivers/pinctrl/renesas/pfc-r8a77970.c
View File

@ -231,7 +231,6 @@
#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
@ -290,8 +289,7 @@ FM(IP8_11_8) IP8_11_8 \
FM(IP8_15_12) IP8_15_12 \
FM(IP8_19_16) IP8_19_16 \
FM(IP8_23_20) IP8_23_20 \
FM(IP8_27_24) IP8_27_24 \
FM(IP8_31_28) IP8_31_28
FM(IP8_27_24) IP8_27_24
/* MOD_SEL0 */ /* 0 */ /* 1 */
#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
@ -2085,17 +2083,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP0_31_22 RESERVED */
GP_0_21_FN, GPSR0_21,
GP_0_20_FN, GPSR0_20,
GP_0_19_FN, GPSR0_19,
@ -2153,22 +2145,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP2_31_17 RESERVED */
GP_2_16_FN, GPSR2_16,
GP_2_15_FN, GPSR2_15,
GP_2_14_FN, GPSR2_14,
@ -2187,22 +2168,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP3_31_17 RESERVED */
GP_3_16_FN, GPSR3_16,
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
@ -2221,33 +2191,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
GROUP(-26, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_6 RESERVED */
GP_4_5_FN, GPSR4_5,
GP_4_4_FN, GPSR4_4,
GP_4_3_FN, GPSR4_3,
@ -2255,24 +2202,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1),
GROUP(
/* GP5_31_15 RESERVED */
GP_5_14_FN, GPSR5_14,
GP_5_13_FN, GPSR5_13,
GP_5_12_FN, GPSR5_12,
@ -2374,8 +2308,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_7_4
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
{ PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,
GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP8_31_28 RESERVED */
IP8_27_24
IP8_23_20
IP8_19_16
@ -2390,19 +2326,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* RESERVED 31, 30, 29, 28 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 27, 26, 25, 24 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 23, 22, 21, 20 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 19, 18, 17, 16 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 15, 14, 13, 12 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 31-12 */
MOD_SEL0_11
MOD_SEL0_10
MOD_SEL0_9

Some files were not shown because too many files have changed in this diff Show More