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Merge branch 'remotes/lorenzo/pci/risc-v'

Browse Source 
- sifive: Add pcie_aux clock to prci driver (Greentime Hu)

- sifive: Use reset-simple in prci driver for PCIe (Greentime Hu)

- Add SiFive FU740 PCIe host controller driver and DT binding (Paul
  Walmsley, Greentime Hu)

* remotes/lorenzo/pci/risc-v:
  riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
  PCI: fu740: Add SiFive FU740 PCIe host controller driver
  dt-bindings: PCI: Add SiFive FU740 PCIe host controller
  MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver
  clk: sifive: Use reset-simple in prci driver for PCIe driver
  clk: sifive: Add pcie_aux clock in prci driver for PCIe driver
This commit is contained in:
Bjorn Helgaas 2021-05-04 10:43:28 -05:00
commit 98d771eb3d
13 changed files with 556 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml Normal file
View File

@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive FU740 PCIe host controller
description: |+
SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
- Greentime Hu <greentime.hu@sifive.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
const: sifive,fu740-pcie
reg:
maxItems: 3
reg-names:
items:
- const: dbi
- const: config
- const: mgmt
num-lanes:
const: 8
msi-parent: true
interrupt-names:
items:
- const: msi
- const: inta
- const: intb
- const: intc
- const: intd
resets:
description: A phandle to the PCIe power up reset line.
maxItems: 1
pwren-gpios:
description: Should specify the GPIO for controlling the PCI bus device power on.
maxItems: 1
reset-gpios:
maxItems: 1
required:
- dma-coherent
- num-lanes
- interrupts
- interrupt-names
- interrupt-parent
- interrupt-map-mask
- interrupt-map
- clock-names
- clocks
- resets
- pwren-gpios
- reset-gpios
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
#include <dt-bindings/clock/sifive-fu740-prci.h>
pcie@e00000000 {
compatible = "sifive,fu740-pcie";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0xe 0x00000000 0x0 0x80000000>,
<0xd 0xf0000000 0x0 0x10000000>,
<0x0 0x100d0000 0x0 0x1000>;
reg-names = "dbi", "config", "mgmt";
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
num-lanes = <0x8>;
interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic0>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
<0x0 0x0 0x0 0x2 &plic0 58>,
<0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>;
clock-names = "pcie_aux";
clocks = <&prci PRCI_CLK_PCIE_AUX>;
resets = <&prci 4>;
pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>;
};
};

8
MAINTAINERS
View File

@ -13692,6 +13692,14 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
F: drivers/pci/controller/dwc/*imx6*
PCI DRIVER FOR FU740
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Greentime Hu <greentime.hu@sifive.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
F: drivers/pci/controller/dwc/pcie-fu740.c
PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
M: Jonathan Derrick <jonathan.derrick@intel.com>
L: linux-pci@vger.kernel.org

33
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
View File

@ -159,6 +159,7 @@ prci: clock-controller@10000000 {
reg = <0x0 0x10000000 0x0 0x1000>;
clocks = <&hfclk>, <&rtcclk>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart0: serial@10010000 {
compatible = "sifive,fu740-c000-uart", "sifive,uart0";
@ -289,5 +290,37 @@ gpio: gpio@10060000 {
clocks = <&prci PRCI_CLK_PCLK>;
status = "disabled";
};
pcie@e00000000 {
compatible = "sifive,fu740-pcie";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0xe 0x00000000 0x0 0x80000000>,
<0xd 0xf0000000 0x0 0x10000000>,
<0x0 0x100d0000 0x0 0x1000>;
reg-names = "dbi", "config", "mgmt";
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
num-lanes = <0x8>;
interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic0>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
<0x0 0x0 0x0 0x2 &plic0 58>,
<0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>;
clock-names = "pcie_aux";
clocks = <&prci PRCI_CLK_PCIE_AUX>;
pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>;
resets = <&prci 4>;
status = "okay";
};
};
};

2
drivers/clk/sifive/Kconfig
View File

@ -10,6 +10,8 @@ if CLK_SIFIVE
config CLK_SIFIVE_PRCI
bool "PRCI driver for SiFive SoCs"
select RESET_CONTROLLER
select RESET_SIMPLE
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
Supports the Power Reset Clock interface (PRCI) IP block found in

11
drivers/clk/sifive/fu740-prci.c
View File

@ -72,6 +72,12 @@ static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
};
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
.enable = sifive_prci_pcie_aux_clock_enable,
.disable = sifive_prci_pcie_aux_clock_disable,
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
};
/* List of clock controls provided by the PRCI */
struct __prci_clock __prci_init_clocks_fu740[] = {
[PRCI_CLK_COREPLL] = {
@ -120,4 +126,9 @@ struct __prci_clock __prci_init_clocks_fu740[] = {
.parent_name = "hfpclkpll",
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
},
[PRCI_CLK_PCIE_AUX] = {
.name = "pcie_aux",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
},
};

2
drivers/clk/sifive/fu740-prci.h
View File

@ -9,7 +9,7 @@
#include "sifive-prci.h"
#define NUM_CLOCK_FU740 8
#define NUM_CLOCK_FU740 9
extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];

54
drivers/clk/sifive/sifive-prci.c
View File

@ -453,6 +453,47 @@ void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
}
/* PCIE AUX clock APIs for enable, disable. */
int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw)
{
struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
struct __prci_data *pd = pc->pd;
u32 r;
r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);
if (r & PRCI_PCIE_AUX_EN_MASK)
return 1;
else
return 0;
}
int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw)
{
struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
struct __prci_data *pd = pc->pd;
u32 r __maybe_unused;
if (sifive_prci_pcie_aux_clock_is_enabled(hw))
return 0;
__prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);
r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
return 0;
}
void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw)
{
struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
struct __prci_data *pd = pc->pd;
u32 r __maybe_unused;
__prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);
r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
}
/**
* __prci_register_clocks() - register clock controls in the PRCI
* @dev: Linux struct device
@ -547,6 +588,19 @@ static int sifive_prci_probe(struct platform_device *pdev)
if (IS_ERR(pd->va))
return PTR_ERR(pd->va);
pd->reset.rcdev.owner = THIS_MODULE;
pd->reset.rcdev.nr_resets = PRCI_RST_NR;
pd->reset.rcdev.ops = &reset_simple_ops;
pd->reset.rcdev.of_node = pdev->dev.of_node;
pd->reset.active_low = true;
pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
spin_lock_init(&pd->reset.lock);
r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
if (r) {
dev_err(dev, "could not register reset controller: %d\n", r);
return r;
}
r = __prci_register_clocks(dev, pd, desc);
if (r) {
dev_err(dev, "could not register clocks: %d\n", r);

13
drivers/clk/sifive/sifive-prci.h
View File

@ -11,6 +11,7 @@
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
#include <linux/clk-provider.h>
#include <linux/reset/reset-simple.h>
#include <linux/platform_device.h>
/*
@ -67,6 +68,11 @@
#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* PCIEAUX */
#define PRCI_PCIE_AUX_OFFSET 0x14
#define PRCI_PCIE_AUX_EN_SHIFT 0
#define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT)
/* GEMGXLPLLCFG0 */
#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
@ -116,6 +122,8 @@
#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \
(0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
#define PRCI_RST_NR 7
/* CLKMUXSTATUSREG */
#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
@ -216,6 +224,7 @@
*/
struct __prci_data {
void __iomem *va;
struct reset_simple_data reset;
struct clk_hw_onecell_data hw_clks;
};
@ -296,4 +305,8 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate);
int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw);
int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw);
void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw);
#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */

9
drivers/pci/controller/dwc/Kconfig
View File

@ -319,4 +319,13 @@ config PCIE_AL
required only for DT-based platforms. ACPI platforms with the
Annapurna Labs PCIe controller don't need to enable this.
config PCIE_FU740
bool "SiFive FU740 PCIe host controller"
depends on PCI_MSI_IRQ_DOMAIN
depends on SOC_SIFIVE || COMPILE_TEST
select PCIE_DW_HOST
help
Say Y here if you want PCIe controller support for the SiFive
FU740.
endmenu

1
drivers/pci/controller/dwc/Makefile
View File

@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o

309
drivers/pci/controller/dwc/pcie-fu740.c Normal file
View File

@ -0,0 +1,309 @@
// SPDX-License-Identifier: GPL-2.0
/*
* FU740 DesignWare PCIe Controller integration
* Copyright (C) 2019-2021 SiFive, Inc.
* Paul Walmsley
* Greentime Hu
*
* Based in part on the i.MX6 PCIe host controller shim which is:
*
* Copyright (C) 2013 Kosagi
* https://www.kosagi.com
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/resource.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/reset.h>
#include "pcie-designware.h"
#define to_fu740_pcie(x) dev_get_drvdata((x)->dev)
struct fu740_pcie {
struct dw_pcie pci;
void __iomem *mgmt_base;
struct gpio_desc *reset;
struct gpio_desc *pwren;
struct clk *pcie_aux;
struct reset_control *rst;
};
#define SIFIVE_DEVICESRESETREG 0x28
#define PCIEX8MGMT_PERST_N 0x0
#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
#define PCIEX8MGMT_DEVICE_TYPE 0x708
#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
#define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0)
#define PCIEX8MGMT_PHY_LOS_THRSHLD BIT(5)
#define PCIEX8MGMT_PHY_TERM_EN BIT(9)
#define PCIEX8MGMT_PHY_TERM_ACDC BIT(10)
#define PCIEX8MGMT_PHY_EN BIT(11)
#define PCIEX8MGMT_PHY_INIT_VAL (PCIEX8MGMT_PHY_CDR_TRACK_EN|\
PCIEX8MGMT_PHY_LOS_THRSHLD|\
PCIEX8MGMT_PHY_TERM_EN|\
PCIEX8MGMT_PHY_TERM_ACDC|\
PCIEX8MGMT_PHY_EN)
#define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 0x1008
#define PCIEX8MGMT_PHY_LANE_OFF 0x100
#define PCIEX8MGMT_PHY_LANE0_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 0)
#define PCIEX8MGMT_PHY_LANE1_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 1)
#define PCIEX8MGMT_PHY_LANE2_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 2)
#define PCIEX8MGMT_PHY_LANE3_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 3)
static void fu740_pcie_assert_reset(struct fu740_pcie *afp)
{
/* Assert PERST_N GPIO */
gpiod_set_value_cansleep(afp->reset, 0);
/* Assert controller PERST_N */
writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);
}
static void fu740_pcie_deassert_reset(struct fu740_pcie *afp)
{
/* Deassert controller PERST_N */
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);
/* Deassert PERST_N GPIO */
gpiod_set_value_cansleep(afp->reset, 1);
}
static void fu740_pcie_power_on(struct fu740_pcie *afp)
{
gpiod_set_value_cansleep(afp->pwren, 1);
/*
* Ensure that PERST has been asserted for at least 100 ms.
* Section 2.2 of PCI Express Card Electromechanical Specification
* Revision 3.0
*/
msleep(100);
}
static void fu740_pcie_drive_reset(struct fu740_pcie *afp)
{
fu740_pcie_assert_reset(afp);
fu740_pcie_power_on(afp);
fu740_pcie_deassert_reset(afp);
}
static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr,
const uint16_t wrdata, struct fu740_pcie *afp)
{
struct device *dev = afp->pci.dev;
void __iomem *phy_cr_para_addr;
void __iomem *phy_cr_para_wr_data;
void __iomem *phy_cr_para_wr_en;
void __iomem *phy_cr_para_ack;
int ret, val;
/* Setup */
if (phy) {
phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR;
phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA;
phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN;
phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK;
} else {
phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR;
phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA;
phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN;
phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK;
}
writel_relaxed(addr, phy_cr_para_addr);
writel_relaxed(wrdata, phy_cr_para_wr_data);
writel_relaxed(1, phy_cr_para_wr_en);
/* Wait for wait_idle */
ret = readl_poll_timeout(phy_cr_para_ack, val, val, 10, 5000);
if (ret)
dev_warn(dev, "Wait for wait_idle state failed!\n");
/* Clear */
writel_relaxed(0, phy_cr_para_wr_en);
/* Wait for ~wait_idle */
ret = readl_poll_timeout(phy_cr_para_ack, val, !val, 10, 5000);
if (ret)
dev_warn(dev, "Wait for !wait_idle state failed!\n");
}
static void fu740_pcie_init_phy(struct fu740_pcie *afp)
{
/* Enable phy cr_para_sel interfaces */
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
/*
* Wait 10 cr_para cycles to guarantee that the registers are ready
* to be edited.
*/
ndelay(10);
/* Set PHY AC termination mode */
fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
}
static int fu740_pcie_start_link(struct dw_pcie *pci)
{
struct device *dev = pci->dev;
struct fu740_pcie *afp = dev_get_drvdata(dev);
/* Enable LTSSM */
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
return 0;
}
static int fu740_pcie_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct fu740_pcie *afp = to_fu740_pcie(pci);
struct device *dev = pci->dev;
int ret;
/* Power on reset */
fu740_pcie_drive_reset(afp);
/* Enable pcieauxclk */
ret = clk_prepare_enable(afp->pcie_aux);
if (ret) {
dev_err(dev, "unable to enable pcie_aux clock\n");
return ret;
}
/*
* Assert hold_phy_rst (hold the controller LTSSM in reset after
* power_up_rst_n for register programming with cr_para)
*/
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
/* Deassert power_up_rst_n */
ret = reset_control_deassert(afp->rst);
if (ret) {
dev_err(dev, "unable to deassert pcie_power_up_rst_n\n");
return ret;
}
fu740_pcie_init_phy(afp);
/* Disable pcieauxclk */
clk_disable_unprepare(afp->pcie_aux);
/* Clear hold_phy_rst */
writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
/* Enable pcieauxclk */
ret = clk_prepare_enable(afp->pcie_aux);
/* Set RC mode */
writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);
return 0;
}
static const struct dw_pcie_host_ops fu740_pcie_host_ops = {
.host_init = fu740_pcie_host_init,
};
static const struct dw_pcie_ops dw_pcie_ops = {
.start_link = fu740_pcie_start_link,
};
static int fu740_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct dw_pcie *pci;
struct fu740_pcie *afp;
afp = devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL);
if (!afp)
return -ENOMEM;
pci = &afp->pci;
pci->dev = dev;
pci->ops = &dw_pcie_ops;
pci->pp.ops = &fu740_pcie_host_ops;
/* SiFive specific region: mgmt */
afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");
if (IS_ERR(afp->mgmt_base))
return PTR_ERR(afp->mgmt_base);
/* Fetch GPIOs */
afp->reset = devm_gpiod_get_optional(dev, "reset-gpios", GPIOD_OUT_LOW);
if (IS_ERR(afp->reset))
return dev_err_probe(dev, PTR_ERR(afp->reset), "unable to get reset-gpios\n");
afp->pwren = devm_gpiod_get_optional(dev, "pwren-gpios", GPIOD_OUT_LOW);
if (IS_ERR(afp->pwren))
return dev_err_probe(dev, PTR_ERR(afp->pwren), "unable to get pwren-gpios\n");
/* Fetch clocks */
afp->pcie_aux = devm_clk_get(dev, "pcie_aux");
if (IS_ERR(afp->pcie_aux))
return dev_err_probe(dev, PTR_ERR(afp->pcie_aux),
"pcie_aux clock source missing or invalid\n");
/* Fetch reset */
afp->rst = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(afp->rst))
return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n");
platform_set_drvdata(pdev, afp);
return dw_pcie_host_init(&pci->pp);
}
static void fu740_pcie_shutdown(struct platform_device *pdev)
{
struct fu740_pcie *afp = platform_get_drvdata(pdev);
/* Bring down link, so bootloader gets clean state in case of reboot */
fu740_pcie_assert_reset(afp);
}
static const struct of_device_id fu740_pcie_of_match[] = {
{ .compatible = "sifive,fu740-pcie", },
{},
};
static struct platform_driver fu740_pcie_driver = {
.driver = {
.name = "fu740-pcie",
.of_match_table = fu740_pcie_of_match,
.suppress_bind_attrs = true,
},
.probe = fu740_pcie_probe,
.shutdown = fu740_pcie_shutdown,
};
builtin_platform_driver(fu740_pcie_driver);

1
drivers/reset/Kconfig
View File

@ -197,6 +197,7 @@ config RESET_SIMPLE
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- ZTE's zx2967 family
- SiFive FU740 SoCs
config RESET_STM32MP157
bool "STM32MP157 Reset Driver" if COMPILE_TEST

1
include/dt-bindings/clock/sifive-fu740-prci.h
View File

@ -19,5 +19,6 @@
#define PRCI_CLK_CLTXPLL 5
#define PRCI_CLK_TLCLK 6
#define PRCI_CLK_PCLK 7
#define PRCI_CLK_PCIE_AUX 8
#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */