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RISC-V: hwprobe: Expose Zicboz extension and its block size

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Expose Zicboz through hwprobe and also provide a key to extract its
respective block size. Opportunistically add a macro and apply it to
current extensions in order to avoid duplicating code.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230918131518.56803-11-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Andrew Jones 2023-09-18 15:15:22 +02:00 committed by Palmer Dabbelt
parent 43c16d51a1
commit 9c7646d5ff
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
4 changed files with 40 additions and 14 deletions
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6
Documentation/riscv/hwprobe.rst
View File

@ -77,6 +77,9 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
in version 1.0 of the Bit-Manipulation ISA extensions. in version 1.0 of the Bit-Manipulation ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors. information about the selected set of processors.
@ -96,3 +99,6 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
not supported at all and will generate a misaligned address fault. not supported at all and will generate a misaligned address fault.
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
represents the size of the Zicboz block in bytes.

2
arch/riscv/include/asm/hwprobe.h
View File

@ -8,6 +8,6 @@
#include <uapi/asm/hwprobe.h> #include <uapi/asm/hwprobe.h>
#define RISCV_HWPROBE_MAX_KEY 5 #define RISCV_HWPROBE_MAX_KEY 6
#endif #endif

2
arch/riscv/include/uapi/asm/hwprobe.h
View File

@ -29,6 +29,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBA (1 << 3)
#define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBB (1 << 4)
#define RISCV_HWPROBE_EXT_ZBS (1 << 5) #define RISCV_HWPROBE_EXT_ZBS (1 << 5)
#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
@ -36,6 +37,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
#endif #endif

44
arch/riscv/kernel/sys_riscv.c
View File

@ -145,26 +145,38 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
for_each_cpu(cpu, cpus) { for_each_cpu(cpu, cpus) {
struct riscv_isainfo *isainfo = &hart_isa[cpu]; struct riscv_isainfo *isainfo = &hart_isa[cpu];
if (riscv_isa_extension_available(isainfo->isa, ZBA)) #define EXT_KEY(ext) \
pair->value |= RISCV_HWPROBE_EXT_ZBA; do { \
else if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \
missing |= RISCV_HWPROBE_EXT_ZBA; pair->value |= RISCV_HWPROBE_EXT_##ext; \
else \
missing |= RISCV_HWPROBE_EXT_##ext; \
} while (false)
if (riscv_isa_extension_available(isainfo->isa, ZBB)) /*
pair->value |= RISCV_HWPROBE_EXT_ZBB; * Only use EXT_KEY() for extensions which can be exposed to userspace,
else * regardless of the kernel's configuration, as no other checks, besides
missing |= RISCV_HWPROBE_EXT_ZBB; * presence in the hart_isa bitmap, are made.
*/
if (riscv_isa_extension_available(isainfo->isa, ZBS)) EXT_KEY(ZBA);
pair->value |= RISCV_HWPROBE_EXT_ZBS; EXT_KEY(ZBB);
else EXT_KEY(ZBS);
missing |= RISCV_HWPROBE_EXT_ZBS; EXT_KEY(ZICBOZ);
#undef EXT_KEY
} }
/* Now turn off reporting features if any CPU is missing it. */ /* Now turn off reporting features if any CPU is missing it. */
pair->value &= ~missing; pair->value &= ~missing;
} }
static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)
{
struct riscv_hwprobe pair;
hwprobe_isa_ext0(&pair, cpus);
return (pair.value & ext);
}
static u64 hwprobe_misaligned(const struct cpumask *cpus) static u64 hwprobe_misaligned(const struct cpumask *cpus)
{ {
int cpu; int cpu;
@ -215,6 +227,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
pair->value = hwprobe_misaligned(cpus); pair->value = hwprobe_misaligned(cpus);
break; break;
case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
pair->value = 0;
if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
pair->value = riscv_cboz_block_size;
break;
/* /*
* For forward compatibility, unknown keys don't fail the whole * For forward compatibility, unknown keys don't fail the whole
* call, but get their element key set to -1 and value set to 0 * call, but get their element key set to -1 and value set to 0