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[ARM] 3367/1: CLCD mode no longer supported on the RealView boards

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Patch from Catalin Marinas

Chosing of the CLCD RGB mode is no longer possible via the SYS_CLCD
register on the RealView boards. Instead, this configuration is done in the
CLCD primecell control register directly.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas 2006-03-16 14:10:20 +00:00 committed by Russell King
parent 243f196d57
commit 9e7714d080
1 changed files with 3 additions and 27 deletions
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30
arch/arm/mach-realview/core.c
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@ -202,11 +202,6 @@ struct clk realview_clcd_clk = {
/* /*
* CLCD support. * CLCD support.
*/ */
#define SYS_CLCD_MODE_MASK (3 << 0)
#define SYS_CLCD_MODE_888 (0 << 0)
#define SYS_CLCD_MODE_5551 (1 << 0)
#define SYS_CLCD_MODE_565_RLSB (2 << 0)
#define SYS_CLCD_MODE_565_BLSB (3 << 0)
#define SYS_CLCD_NLCDIOON (1 << 2) #define SYS_CLCD_NLCDIOON (1 << 2)
#define SYS_CLCD_VDDPOSSWITCH (1 << 3) #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
#define SYS_CLCD_PWR3V5SWITCH (1 << 4) #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
@ -360,29 +355,10 @@ static void realview_clcd_enable(struct clcd_fb *fb)
void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
u32 val; u32 val;
/*
* Enable the PSUs
*/
val = readl(sys_clcd); val = readl(sys_clcd);
val &= ~SYS_CLCD_MODE_MASK;
switch (fb->fb.var.green.length) {
case 5:
val |= SYS_CLCD_MODE_5551;
break;
case 6:
val |= SYS_CLCD_MODE_565_RLSB;
break;
case 8:
val |= SYS_CLCD_MODE_888;
break;
}
/*
* Set the MUX
*/
writel(val, sys_clcd);
/*
* And now enable the PSUs
*/
val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
writel(val, sys_clcd); writel(val, sys_clcd);
} }