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RISC-V: KVM: Allow vector crypto extensions for Guest/VM
We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable vector crypto extensions for Guest/VM. This includes extensions Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, and Zvkt. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
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@ -150,6 +150,16 @@ enum KVM_RISCV_ISA_EXT_ID {
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KVM_RISCV_ISA_EXT_ZKSED,
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KVM_RISCV_ISA_EXT_ZKSH,
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KVM_RISCV_ISA_EXT_ZKT,
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KVM_RISCV_ISA_EXT_ZVBB,
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KVM_RISCV_ISA_EXT_ZVBC,
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KVM_RISCV_ISA_EXT_ZVKB,
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KVM_RISCV_ISA_EXT_ZVKG,
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KVM_RISCV_ISA_EXT_ZVKNED,
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KVM_RISCV_ISA_EXT_ZVKNHA,
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KVM_RISCV_ISA_EXT_ZVKNHB,
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KVM_RISCV_ISA_EXT_ZVKSED,
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KVM_RISCV_ISA_EXT_ZVKSH,
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KVM_RISCV_ISA_EXT_ZVKT,
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KVM_RISCV_ISA_EXT_MAX,
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};
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@ -62,6 +62,16 @@ static const unsigned long kvm_isa_ext_arr[] = {
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KVM_ISA_EXT_ARR(ZKSED),
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KVM_ISA_EXT_ARR(ZKSH),
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KVM_ISA_EXT_ARR(ZKT),
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KVM_ISA_EXT_ARR(ZVBB),
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KVM_ISA_EXT_ARR(ZVBC),
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KVM_ISA_EXT_ARR(ZVKB),
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KVM_ISA_EXT_ARR(ZVKG),
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KVM_ISA_EXT_ARR(ZVKNED),
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KVM_ISA_EXT_ARR(ZVKNHA),
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KVM_ISA_EXT_ARR(ZVKNHB),
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KVM_ISA_EXT_ARR(ZVKSED),
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KVM_ISA_EXT_ARR(ZVKSH),
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KVM_ISA_EXT_ARR(ZVKT),
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};
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static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
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@ -121,6 +131,16 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
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case KVM_RISCV_ISA_EXT_ZKSED:
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case KVM_RISCV_ISA_EXT_ZKSH:
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case KVM_RISCV_ISA_EXT_ZKT:
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case KVM_RISCV_ISA_EXT_ZVBB:
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case KVM_RISCV_ISA_EXT_ZVBC:
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case KVM_RISCV_ISA_EXT_ZVKB:
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case KVM_RISCV_ISA_EXT_ZVKG:
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case KVM_RISCV_ISA_EXT_ZVKNED:
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case KVM_RISCV_ISA_EXT_ZVKNHA:
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case KVM_RISCV_ISA_EXT_ZVKNHB:
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case KVM_RISCV_ISA_EXT_ZVKSED:
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case KVM_RISCV_ISA_EXT_ZVKSH:
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case KVM_RISCV_ISA_EXT_ZVKT:
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return false;
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/* Extensions which can be disabled using Smstateen */
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case KVM_RISCV_ISA_EXT_SSAIA:
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