mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-01-04 04:06:26 +00:00
ARM: SoC updates for 5.11
These are update for SoC specific code, mostly in the
32-bit architecture:
- A rework for handling MMIO accesses in Renesas SoCs
in a more portable way
- Updates to SoC version detection in NXP i.MX SoCs.
- Smaller bug fixes for OMAP, Samsung, Marvell, Amlogic,
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Arnd Bergmann:
"These are updates for SoC specific code, mostly in the 32-bit
architecture:
- A rework for handling MMIO accesses in Renesas SoCs in a more
portable way
- Updates to SoC version detection in NXP i.MX SoCs.
- Smaller bug fixes for OMAP, Samsung, Marvell, Amlogic"
* tag 'arm-soc-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits)
arm64: Kconfig: meson: drop pinctrl
ARM: mxs: Add serial number support for i.MX23, i.MX28 SoCs
MAINTAINERS: switch mvebu tree to kernel.org
MAINTAINERS: Add an entry for MikroTik CRS3xx 98DX3236 boards
ARM: shmobile: Stop using __raw_*() I/O accessors
ARM: shmobile: sh73a0: Remove obsolete static mapping
ARM: shmobile: sh73a0: Use ioremap() to map SMP registers
ARM: shmobile: sh73a0: Use ioremap() to map L2C registers
ARM: shmobile: r8a7779: Remove obsolete static mappings
ARM: shmobile: r8a7779: Use ioremap() to map SMP registers
ARM: shmobile: r8a7779: Use ioremap() to map INTC2 registers
ARM: shmobile: r8a7778: Introduce HPBREG_BASE
ARM: OMAP1: clock: Use IS_ERR_OR_NULL() to clean code
ARM: OMAP2+: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare
ARM: OMAP2+: Remove redundant assignment to variable ret
ARM: OMAP2+: Fix kfree NULL pointer in omap2xxx_clkt_vps_init
ARM: OMAP2+: Fix memleak in omap2xxx_clkt_vps_init
ARM: exynos: extend cpuidle support to P4 Note boards
ARM: imx: mach-imx6q: correctly identify i.MX6QP SoCs
ARM: imx: imx7ulp: Add a comment explaining the B2 silicon version
...
This commit is contained in:
Linus Torvalds
commit
b06db0b393
15
MAINTAINERS
15
MAINTAINERS
@ -2026,7 +2026,7 @@ M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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M: Gregory Clement <gregory.clement@bootlin.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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T: git git://git.infradead.org/linux-mvebu.git
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
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F: Documentation/devicetree/bindings/soc/dove/
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F: arch/arm/boot/dts/dove*
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F: arch/arm/boot/dts/orion5x*
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@ -2042,7 +2042,7 @@ M: Gregory Clement <gregory.clement@bootlin.com>
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M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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T: git git://git.infradead.org/linux-mvebu.git
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
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F: arch/arm/boot/dts/armada*
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F: arch/arm/boot/dts/kirkwood*
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F: arch/arm/configs/mvebu_*_defconfig
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@ -11780,6 +11780,17 @@ M: Oliver Neukum <oliver@neukum.org>
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S: Maintained
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F: drivers/usb/image/microtek.*
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MIKROTIK CRS3XX 98DX3236 BOARD SUPPORT
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M: Luka Kovacic <luka.kovacic@sartura.hr>
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M: Luka Perkov <luka.perkov@sartura.hr>
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S: Maintained
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F: arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts
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F: arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts
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F: arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts
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F: arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts
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F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts
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F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts
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MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
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M: Sakari Ailus <sakari.ailus@linux.intel.com>
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L: linux-media@vger.kernel.org
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@ -177,7 +177,8 @@ static void __init exynos_dt_machine_init(void)
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if (of_machine_is_compatible("samsung,exynos4210") ||
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(of_machine_is_compatible("samsung,exynos4412") &&
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(of_machine_is_compatible("samsung,trats2") ||
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of_machine_is_compatible("samsung,midas"))) ||
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of_machine_is_compatible("samsung,midas") ||
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of_machine_is_compatible("samsung,p4note"))) ||
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of_machine_is_compatible("samsung,exynos3250") ||
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of_machine_is_compatible("samsung,exynos5250"))
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platform_device_register(&exynos_cpuidle);
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@ -206,8 +207,8 @@ static void __init exynos_dt_fixup(void)
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}
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DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
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.l2c_aux_val = 0x38400000,
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.l2c_aux_mask = 0xc60fffff,
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.l2c_aux_val = 0x08400000,
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.l2c_aux_mask = 0xf60fffff,
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.smp = smp_ops(exynos_smp_ops),
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.map_io = exynos_init_io,
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.init_early = exynos_firmware_init,
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@ -215,7 +215,7 @@ void exynos_core_restart(u32 core_id)
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unsigned int timeout = 16;
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u32 val;
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if (!of_machine_is_compatible("samsung,exynos3250"))
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if (!soc_is_exynos3250())
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return;
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while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
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@ -245,8 +245,13 @@ static void __init imx6q_axi_init(void)
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static void __init imx6q_init_machine(void)
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{
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if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
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imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
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if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
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/*
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* SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP.
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* Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0),
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* e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1.
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*/
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imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10);
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else
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imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
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imx_get_soc_revision());
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@ -37,6 +37,7 @@ static void __init imx7ulp_set_revision(void)
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* bit[31:28] of JTAG_ID register defines revision as below from B0:
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* 0001 B0
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* 0010 B1
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* 0011 B2
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*/
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switch (revision >> 28) {
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case 1:
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@ -45,6 +46,9 @@ static void __init imx7ulp_set_revision(void)
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case 2:
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imx_set_soc_revision(IMX_CHIP_REVISION_2_1);
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break;
|
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case 3:
|
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imx_set_soc_revision(IMX_CHIP_REVISION_2_2);
|
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break;
|
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default:
|
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imx_set_soc_revision(IMX_CHIP_REVISION_1_0);
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break;
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|
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@ -22,6 +22,7 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/system_info.h>
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#include <asm/system_misc.h>
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|
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#include "pm.h"
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@ -51,6 +52,9 @@
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#define MXS_CLR_ADDR 0x8
|
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#define MXS_TOG_ADDR 0xc
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|
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#define HW_OCOTP_OPS2 19 /* offset 0x150 */
|
||||
#define HW_OCOTP_OPS3 20 /* offset 0x160 */
|
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|
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static u32 chipid;
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static u32 socid;
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|
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@ -379,6 +383,8 @@ static void __init mxs_machine_init(void)
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struct device *parent;
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struct soc_device *soc_dev;
|
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struct soc_device_attribute *soc_dev_attr;
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u64 soc_uid = 0;
|
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const u32 *ocotp = mxs_get_ocotp();
|
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int ret;
|
||||
|
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
||||
@ -394,8 +400,21 @@ static void __init mxs_machine_init(void)
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soc_dev_attr->soc_id = mxs_get_soc_id();
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soc_dev_attr->revision = mxs_get_revision();
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if (socid == HW_DIGCTL_CHIPID_MX23) {
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soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3];
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} else if (socid == HW_DIGCTL_CHIPID_MX28) {
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soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2];
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soc_uid <<= 32;
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system_serial_low = ocotp[HW_OCOTP_OPS3];
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soc_uid |= system_serial_low;
|
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}
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||||
|
||||
if (soc_uid)
|
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soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
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|
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->serial_number);
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr);
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return;
|
||||
|
||||
@ -612,7 +612,7 @@ int clk_enable(struct clk *clk)
|
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unsigned long flags;
|
||||
int ret;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
if (IS_ERR_OR_NULL(clk))
|
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return -EINVAL;
|
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|
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spin_lock_irqsave(&clockfw_lock, flags);
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@ -627,7 +627,7 @@ void clk_disable(struct clk *clk)
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{
|
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unsigned long flags;
|
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|
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if (clk == NULL || IS_ERR(clk))
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
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@ -650,7 +650,7 @@ unsigned long clk_get_rate(struct clk *clk)
|
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unsigned long flags;
|
||||
unsigned long ret;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
if (IS_ERR_OR_NULL(clk))
|
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return 0;
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
@ -670,7 +670,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
|
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unsigned long flags;
|
||||
long ret;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
@ -686,7 +686,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
unsigned long flags;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
return ret;
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
@ -791,7 +791,7 @@ void clk_preinit(struct clk *clk)
|
||||
|
||||
int clk_register(struct clk *clk)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
@ -817,7 +817,7 @@ EXPORT_SYMBOL(clk_register);
|
||||
|
||||
void clk_unregister(struct clk *clk)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
return;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
|
||||
@ -235,7 +235,7 @@ void omap2xxx_clkt_vps_init(void)
|
||||
|
||||
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
|
||||
if (!hw)
|
||||
goto cleanup;
|
||||
return;
|
||||
init.name = "virt_prcm_set";
|
||||
init.ops = &virt_prcm_set_ops;
|
||||
init.parent_names = &parent_name;
|
||||
@ -244,9 +244,12 @@ void omap2xxx_clkt_vps_init(void)
|
||||
hw->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &hw->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
printk(KERN_ERR "Failed to register clock\n");
|
||||
kfree(hw);
|
||||
return;
|
||||
}
|
||||
|
||||
clkdev_create(clk, "cpufreq_ck", NULL);
|
||||
return;
|
||||
cleanup:
|
||||
kfree(hw);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -385,8 +385,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
|
||||
}
|
||||
|
||||
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
||||
if (oc->_clk)
|
||||
clk_prepare_enable(oc->_clk);
|
||||
clk_prepare_enable(oc->_clk);
|
||||
|
||||
dispc_disable_outputs();
|
||||
|
||||
@ -412,8 +411,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
|
||||
pr_debug("dss_core: softreset done\n");
|
||||
|
||||
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
||||
if (oc->_clk)
|
||||
clk_disable_unprepare(oc->_clk);
|
||||
clk_disable_unprepare(oc->_clk);
|
||||
|
||||
r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
|
||||
|
||||
|
||||
@ -334,10 +334,9 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
|
||||
struct omap_hwmod **hwmods;
|
||||
|
||||
od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
|
||||
if (!od) {
|
||||
ret = -ENOMEM;
|
||||
if (!od)
|
||||
goto oda_exit1;
|
||||
}
|
||||
|
||||
od->hwmods_cnt = oh_cnt;
|
||||
|
||||
hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
|
||||
|
||||
@ -64,7 +64,7 @@ static int shmobile_smp_scu_psr_core_disabled(int cpu)
|
||||
{
|
||||
unsigned long mask = SCU_PM_POWEROFF << (cpu * 8);
|
||||
|
||||
if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
|
||||
if ((readl(shmobile_scu_base + 8) & mask) == mask)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
|
||||
@ -14,6 +14,8 @@
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define HPBREG_BASE 0xfe700000
|
||||
|
||||
#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
|
||||
#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
|
||||
|
||||
@ -22,19 +24,19 @@
|
||||
|
||||
static void __init r8a7778_init_irq_dt(void)
|
||||
{
|
||||
void __iomem *base = ioremap(0xfe700000, 0x00100000);
|
||||
void __iomem *base = ioremap(HPBREG_BASE, 0x00100000);
|
||||
|
||||
BUG_ON(!base);
|
||||
|
||||
irqchip_init();
|
||||
|
||||
/* route all interrupts to ARM */
|
||||
__raw_writel(0x73ffffff, base + INT2NTSR0);
|
||||
__raw_writel(0xffffffff, base + INT2NTSR1);
|
||||
writel(0x73ffffff, base + INT2NTSR0);
|
||||
writel(0xffffffff, base + INT2NTSR1);
|
||||
|
||||
/* unmask all known interrupts in INTCS2 */
|
||||
__raw_writel(0x08330773, base + INT2SMSKCR0);
|
||||
__raw_writel(0x00311110, base + INT2SMSKCR1);
|
||||
writel(0x08330773, base + INT2SMSKCR0);
|
||||
writel(0x00311110, base + INT2SMSKCR1);
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
@ -15,53 +15,36 @@
|
||||
#include "common.h"
|
||||
#include "r8a7779.h"
|
||||
|
||||
static struct map_desc r8a7779_io_desc[] __initdata = {
|
||||
/* 2M identity mapping for 0xf0000000 (MPCORE) */
|
||||
{
|
||||
.virtual = 0xf0000000,
|
||||
.pfn = __phys_to_pfn(0xf0000000),
|
||||
.length = SZ_2M,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
/* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
|
||||
{
|
||||
.virtual = 0xfe000000,
|
||||
.pfn = __phys_to_pfn(0xfe000000),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
};
|
||||
|
||||
static void __init r8a7779_map_io(void)
|
||||
{
|
||||
debug_ll_io_init();
|
||||
iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
|
||||
}
|
||||
#define HPBREG_BASE 0xfe700000
|
||||
|
||||
/* IRQ */
|
||||
#define INT2SMSKCR0 IOMEM(0xfe7822a0)
|
||||
#define INT2SMSKCR1 IOMEM(0xfe7822a4)
|
||||
#define INT2SMSKCR2 IOMEM(0xfe7822a8)
|
||||
#define INT2SMSKCR3 IOMEM(0xfe7822ac)
|
||||
#define INT2SMSKCR4 IOMEM(0xfe7822b0)
|
||||
#define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */
|
||||
#define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */
|
||||
#define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */
|
||||
#define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */
|
||||
#define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */
|
||||
|
||||
#define INT2NTSR0 IOMEM(0xfe700060)
|
||||
#define INT2NTSR1 IOMEM(0xfe700064)
|
||||
#define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */
|
||||
#define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */
|
||||
|
||||
static void __init r8a7779_init_irq_dt(void)
|
||||
{
|
||||
void __iomem *base = ioremap(HPBREG_BASE, 0x00100000);
|
||||
|
||||
irqchip_init();
|
||||
|
||||
/* route all interrupts to ARM */
|
||||
__raw_writel(0xffffffff, INT2NTSR0);
|
||||
__raw_writel(0x3fffffff, INT2NTSR1);
|
||||
writel(0xffffffff, base + INT2NTSR0);
|
||||
writel(0x3fffffff, base + INT2NTSR1);
|
||||
|
||||
/* unmask all known interrupts in INTCS2 */
|
||||
__raw_writel(0xfffffff0, INT2SMSKCR0);
|
||||
__raw_writel(0xfff7ffff, INT2SMSKCR1);
|
||||
__raw_writel(0xfffbffdf, INT2SMSKCR2);
|
||||
__raw_writel(0xbffffffc, INT2SMSKCR3);
|
||||
__raw_writel(0x003fee3f, INT2SMSKCR4);
|
||||
writel(0xfffffff0, base + INT2SMSKCR0);
|
||||
writel(0xfff7ffff, base + INT2SMSKCR1);
|
||||
writel(0xfffbffdf, base + INT2SMSKCR2);
|
||||
writel(0xbffffffc, base + INT2SMSKCR3);
|
||||
writel(0x003fee3f, base + INT2SMSKCR4);
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
static const char *const r8a7779_compat_dt[] __initconst = {
|
||||
@ -71,7 +54,6 @@ static const char *const r8a7779_compat_dt[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
|
||||
.smp = smp_ops(r8a7779_smp_ops),
|
||||
.map_io = r8a7779_map_io,
|
||||
.init_irq = r8a7779_init_irq_dt,
|
||||
.init_late = shmobile_init_late,
|
||||
.dt_compat = r8a7779_compat_dt,
|
||||
|
||||
@ -22,29 +22,11 @@
|
||||
#include "common.h"
|
||||
#include "sh73a0.h"
|
||||
|
||||
static struct map_desc sh73a0_io_desc[] __initdata = {
|
||||
/* create a 1:1 identity mapping for 0xe6xxxxxx
|
||||
* used by CPGA, INTC and PFC.
|
||||
*/
|
||||
{
|
||||
.virtual = 0xe6000000,
|
||||
.pfn = __phys_to_pfn(0xe6000000),
|
||||
.length = 256 << 20,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
};
|
||||
|
||||
static void __init sh73a0_map_io(void)
|
||||
{
|
||||
debug_ll_io_init();
|
||||
iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
|
||||
}
|
||||
|
||||
static void __init sh73a0_generic_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Shared attribute override enable, 64K*8way */
|
||||
l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
|
||||
l2x0_init(ioremap(0xf0100000, PAGE_SIZE), 0x00400000, 0xc20f0fff);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -55,7 +37,6 @@ static const char *const sh73a0_boards_compat_dt[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
|
||||
.smp = smp_ops(sh73a0_smp_ops),
|
||||
.map_io = sh73a0_map_io,
|
||||
.init_machine = sh73a0_generic_init,
|
||||
.init_late = shmobile_init_late,
|
||||
.dt_compat = sh73a0_boards_compat_dt,
|
||||
|
||||
@ -20,8 +20,10 @@
|
||||
#include "common.h"
|
||||
#include "r8a7779.h"
|
||||
|
||||
#define AVECR IOMEM(0xfe700040)
|
||||
#define R8A7779_SCU_BASE 0xf0000000
|
||||
#define HPBREG_BASE 0xfe700000
|
||||
#define AVECR 0x0040 /* ARM Reset Vector Address Register */
|
||||
|
||||
#define R8A7779_SCU_BASE 0xf0000000
|
||||
|
||||
static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
@ -36,11 +38,15 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
|
||||
static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
void __iomem *base = ioremap(HPBREG_BASE, 0x1000);
|
||||
|
||||
/* Map the reset vector (in headsmp-scu.S, headsmp.S) */
|
||||
__raw_writel(__pa(shmobile_boot_vector), AVECR);
|
||||
writel(__pa(shmobile_boot_vector), base + AVECR);
|
||||
|
||||
/* setup r8a7779 specific SCU bits */
|
||||
shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus);
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
|
||||
@ -16,31 +16,42 @@
|
||||
#include "common.h"
|
||||
#include "sh73a0.h"
|
||||
|
||||
#define WUPCR IOMEM(0xe6151010)
|
||||
#define SRESCR IOMEM(0xe6151018)
|
||||
#define PSTR IOMEM(0xe6151040)
|
||||
#define SBAR IOMEM(0xe6180020)
|
||||
#define APARMBAREA IOMEM(0xe6f10020)
|
||||
#define CPG_BASE2 0xe6151000
|
||||
#define WUPCR 0x10 /* System-CPU Wake Up Control Register */
|
||||
#define SRESCR 0x18 /* System-CPU Software Reset Control Register */
|
||||
#define PSTR 0x40 /* System-CPU Power Status Register */
|
||||
|
||||
#define SYSC_BASE 0xe6180000
|
||||
#define SBAR 0x20 /* SYS Boot Address Register */
|
||||
|
||||
#define AP_BASE 0xe6f10000
|
||||
#define APARMBAREA 0x20 /* Address Translation Area Register */
|
||||
|
||||
#define SH73A0_SCU_BASE 0xf0000000
|
||||
|
||||
static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned int lcpu = cpu_logical_map(cpu);
|
||||
void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE);
|
||||
|
||||
if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3)
|
||||
__raw_writel(1 << lcpu, WUPCR); /* wake up */
|
||||
if (((readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3)
|
||||
writel(1 << lcpu, cpg2 + WUPCR); /* wake up */
|
||||
else
|
||||
__raw_writel(1 << lcpu, SRESCR); /* reset */
|
||||
|
||||
writel(1 << lcpu, cpg2 + SRESCR); /* reset */
|
||||
iounmap(cpg2);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
void __iomem *ap = ioremap(AP_BASE, PAGE_SIZE);
|
||||
void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE);
|
||||
|
||||
/* Map the reset vector (in headsmp.S) */
|
||||
__raw_writel(0, APARMBAREA); /* 4k */
|
||||
__raw_writel(__pa(shmobile_boot_vector), SBAR);
|
||||
writel(0, ap + APARMBAREA); /* 4k */
|
||||
writel(__pa(shmobile_boot_vector), sysc + SBAR);
|
||||
iounmap(sysc);
|
||||
iounmap(ap);
|
||||
|
||||
/* setup sh73a0 specific SCU bits */
|
||||
shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus);
|
||||
|
||||
@ -152,11 +152,6 @@ config ARCH_MEDIATEK
|
||||
|
||||
config ARCH_MESON
|
||||
bool "Amlogic Platforms"
|
||||
select PINCTRL
|
||||
select PINCTRL_MESON
|
||||
select COMMON_CLK_GXBB
|
||||
select COMMON_CLK_AXG
|
||||
select COMMON_CLK_G12A
|
||||
select MESON_IRQ_GPIO
|
||||
help
|
||||
This enables support for the arm64 based Amlogic SoCs
|
||||
|
||||
Loading…
Reference in New Issue
Block a user