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MIPS: perf: Add support for OCTEON III perf events.

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According to Hardware Reference Manual, OCTEON III
are mostly same as previous OCTEON models. So just
enable them and extend supported event code.
0x3e and 0x3f still reserved.

Signed-off-by: Jia Qingtong <jiaqingtong97@163.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jia Qingtong 2021-01-01 17:32:00 +08:00 committed by Thomas Bogendoerfer
parent 68324a68fb
commit c2b49a3237
1 changed files with 13 additions and 9 deletions
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22
arch/mips/kernel/perf_event_mipsxx.c
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@ -1919,19 +1919,22 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
{
unsigned int raw_id = config & 0xff;
unsigned int base_id = raw_id & 0x7f;
unsigned int base_id = config & 0x7f;
unsigned int event_max;
raw_event.cntr_mask = CNTR_ALL;
raw_event.event_id = base_id;
if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
if (base_id > 0x42)
return ERR_PTR(-EOPNOTSUPP);
} else {
if (base_id > 0x3a)
return ERR_PTR(-EOPNOTSUPP);
if (current_cpu_type() == CPU_CAVIUM_OCTEON3)
event_max = 0x5f;
else if (current_cpu_type() == CPU_CAVIUM_OCTEON2)
event_max = 0x42;
else
event_max = 0x3a;
if (base_id > event_max) {
return ERR_PTR(-EOPNOTSUPP);
}
switch (base_id) {
@ -1941,7 +1944,7 @@ static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
case 0x1f:
case 0x2f:
case 0x34:
case 0x3b ... 0x3f:
case 0x3e ... 0x3f:
return ERR_PTR(-EOPNOTSUPP);
default:
break;
@ -2077,6 +2080,7 @@ init_hw_perf_events(void)
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
case CPU_CAVIUM_OCTEON3:
mipspmu.name = "octeon";
mipspmu.general_event_map = &octeon_event_map;
mipspmu.cache_event_map = &octeon_cache_map;