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staging: rtl8723bs: use MAX_RF_PATH_NUM as ceiling to rf path index

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use MAX_RF_PATH_NUM as ceiling to rf path index.
Only 2 rf paths are used, not 4. Remove also
TX_POWER_BY_RATE_NUM_RF left unused.

Use RF_PATH_A as loop starting point instead of
hardcoded 0, as in other places.

Related comments modified accordingly.

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Link: https://lore.kernel.org/r/88da23cef57131b39a63b2757b91f959553dd65d.1628329348.git.fabioaiuto83@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Fabio Aiuto 2021-08-07 11:48:11 +02:00 committed by Greg Kroah-Hartman
parent da4c99c261
commit c4c7c7182e
3 changed files with 9 additions and 13 deletions
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2
drivers/staging/rtl8723bs/hal/hal_com_phycfg.c
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@ -347,7 +347,7 @@ void PHY_InitTxPowerByRate(struct adapter *padapter)
struct hal_com_data *pHalData = GET_HAL_DATA(padapter); struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
u8 rfPath, rate; u8 rfPath, rate;
for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath) for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath)
for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate) for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
pHalData->TxPwrByRateOffset[rfPath][rate] = 0; pHalData->TxPwrByRateOffset[rfPath][rate] = 0;
} }

12
drivers/staging/rtl8723bs/include/hal_data.h
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@ -234,14 +234,12 @@ struct hal_com_data {
u8 TxPwrInPercentage; u8 TxPwrInPercentage;
u8 TxPwrCalibrateRate; u8 TxPwrCalibrateRate;
/* TX power by rate table at most 4RF path. */ /* TX power by rate table */
/* The register is */ /* RF: at most 2 = AB = 0/1 */
/* VHT TX power by rate off setArray = */ /* CCK = 0 OFDM = 1 HT-MCS 0-7 = 2 */
/* RF: at most 4*4 = ABCD = 0/1/2/3 */
/* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */
u8 TxPwrByRateTable; u8 TxPwrByRateTable;
u8 TxPwrByRateBand; u8 TxPwrByRateBand;
s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_RF][TX_PWR_BY_RATE_NUM_RATE]; s8 TxPwrByRateOffset[MAX_RF_PATH_NUM][TX_PWR_BY_RATE_NUM_RATE];
/* */ /* */
/* 2 Power Limit Table */ /* 2 Power Limit Table */
@ -259,7 +257,7 @@ struct hal_com_data {
[MAX_RF_PATH_NUM]; [MAX_RF_PATH_NUM];
/* Store the original power by rate value of the base of each rate section of rf path A & B */ /* Store the original power by rate value of the base of each rate section of rf path A & B */
u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF][MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; u8 TxPwrByRateBase2_4G[MAX_RF_PATH_NUM][MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
/* For power group */ /* For power group */
u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];

8
drivers/staging/rtl8723bs/include/hal_pg.h
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@ -14,11 +14,9 @@
*/ */
#define MAX_TX_COUNT 4 #define MAX_TX_COUNT 4
/* For VHT series TX power by rate table. */ /* TX power by rate table. */
/* VHT TX power by rate off setArray = */ /* RF: = AB = 0/1 */
/* RF: at most 4*4 = ABCD = 0/1/2/3 */ /* CCK = 0 OFDM = 1 HT-MCS 0-7 = 2 */
/* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */
#define TX_PWR_BY_RATE_NUM_RF 4
#define TX_PWR_BY_RATE_NUM_RATE 84 #define TX_PWR_BY_RATE_NUM_RATE 84
#define MAX_RF_PATH_NUM 2 #define MAX_RF_PATH_NUM 2
#define MAX_CHNL_GROUP_24G 6 #define MAX_CHNL_GROUP_24G 6