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irqchip: nvic: Fix offset for Interrupt Priority Offsets

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According to ARM(v7M) ARM Interrupt Priority Offsets located at
0xE000E400-0xE000E5EC, while 0xE000E300-0xE000E33C covers read-only
Interrupt Active Bit Registers

Fixes: 292ec080491d ("irqchip: Add support for ARMv7-M NVIC")
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211201110259.84857-1-vladimir.murzin@arm.com
This commit is contained in:
Vladimir Murzin 2021-12-01 11:02:58 +00:00 committed by Marc Zyngier
parent 357a9c4b79
commit c5e0cbe285
1 changed files with 1 additions and 1 deletions
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2
drivers/irqchip/irq-nvic.c
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@ -26,7 +26,7 @@
#define NVIC_ISER 0x000
#define NVIC_ICER 0x080
#define NVIC_IPR 0x300
#define NVIC_IPR 0x400
#define NVIC_MAX_BANKS 16
/*