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rtc: support for the Amlogic on-chip RTC
This is the third amlogic driver. The RTC hardware of A4 SoC is different from the previous one. This RTC hardware includes a timing function and an alarm function. But the existing has only timing function, alarm function is using the system clock to implement a virtual alarm. Add the RTC driver to support it. Signed-off-by: Yiting Deng <yiting.deng@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20241112-rtc-v6-2-a71b60d2f354@amlogic.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Yiting Deng
Alexandre Belloni
parent
ce57cf7319
commit
c89ac9182e
@ -2091,4 +2091,16 @@ config RTC_DRV_SSD202D
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This driver can also be built as a module, if so, the module
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will be called "rtc-ssd20xd".
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config RTC_DRV_AMLOGIC_A4
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tristate "Amlogic RTC"
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depends on ARCH_MESON || COMPILE_TEST
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select REGMAP_MMIO
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default y
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help
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If you say yes here you get support for the RTC block on the
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Amlogic A113L2(A4) and A113X2(A5) SoCs.
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This driver can also be built as a module. If so, the module
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will be called "rtc-amlogic-a4".
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endif # RTC_CLASS
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@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_ABB5ZES3) += rtc-ab-b5ze-s3.o
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obj-$(CONFIG_RTC_DRV_ABEOZ9) += rtc-ab-eoz9.o
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obj-$(CONFIG_RTC_DRV_ABX80X) += rtc-abx80x.o
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obj-$(CONFIG_RTC_DRV_AC100) += rtc-ac100.o
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obj-$(CONFIG_RTC_DRV_AMLOGIC_A4) += rtc-amlogic-a4.o
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obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o
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obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o
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obj-$(CONFIG_RTC_DRV_ASM9260) += rtc-asm9260.o
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474
drivers/rtc/rtc-amlogic-a4.c
Normal file
474
drivers/rtc/rtc-amlogic-a4.c
Normal file
@ -0,0 +1,474 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
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/*
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* Copyright (C) 2024 Amlogic, Inc. All rights reserved
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* Author: Yiting Deng <yiting.deng@amlogic.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/rtc.h>
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#include <linux/time64.h>
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/* rtc oscillator rate */
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#define OSC_32K 32768
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#define OSC_24M 24000000
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#define RTC_CTRL (0x0 << 2) /* Control RTC */
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#define RTC_ALRM0_EN BIT(0)
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#define RTC_OSC_SEL BIT(8)
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#define RTC_ENABLE BIT(12)
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#define RTC_COUNTER_REG (0x1 << 2) /* Program RTC counter initial value */
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#define RTC_ALARM0_REG (0x2 << 2) /* Program RTC alarm0 value */
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#define RTC_SEC_ADJUST_REG (0x6 << 2) /* Control second-based timing adjustment */
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#define RTC_MATCH_COUNTER GENMASK(18, 0)
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#define RTC_SEC_ADJUST_CTRL GENMASK(20, 19)
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#define RTC_ADJ_VALID BIT(23)
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#define RTC_INT_MASK (0x8 << 2) /* RTC interrupt mask */
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#define RTC_ALRM0_IRQ_MSK BIT(0)
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#define RTC_INT_CLR (0x9 << 2) /* Clear RTC interrupt */
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#define RTC_ALRM0_IRQ_CLR BIT(0)
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#define RTC_OSCIN_CTRL0 (0xa << 2) /* Control RTC clk from 24M */
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#define RTC_OSCIN_CTRL1 (0xb << 2) /* Control RTC clk from 24M */
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#define RTC_OSCIN_IN_EN BIT(31)
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#define RTC_OSCIN_OUT_CFG GENMASK(29, 28)
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#define RTC_OSCIN_OUT_N0M0 GENMASK(11, 0)
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#define RTC_OSCIN_OUT_N1M1 GENMASK(23, 12)
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#define RTC_INT_STATUS (0xc << 2) /* RTC interrupt status */
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#define RTC_ALRM0_IRQ_STATUS BIT(0)
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#define RTC_REAL_TIME (0xd << 2) /* RTC time value */
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#define RTC_OSCIN_OUT_32K_N0 0x2dc
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#define RTC_OSCIN_OUT_32K_N1 0x2db
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#define RTC_OSCIN_OUT_32K_M0 0x1
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#define RTC_OSCIN_OUT_32K_M1 0x2
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#define RTC_SWALLOW_SECOND 0x2
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#define RTC_INSERT_SECOND 0x3
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struct aml_rtc_config {
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bool gray_stored;
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};
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struct aml_rtc_data {
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struct regmap *map;
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struct rtc_device *rtc_dev;
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int irq;
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struct clk *rtc_clk;
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struct clk *sys_clk;
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int rtc_enabled;
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const struct aml_rtc_config *config;
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};
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static const struct regmap_config aml_rtc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = RTC_REAL_TIME,
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};
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static inline u32 gray_to_binary(u32 gray)
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{
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u32 bcd = gray;
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int size = sizeof(bcd) * 8;
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int i;
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for (i = 0; (1 << i) < size; i++)
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bcd ^= bcd >> (1 << i);
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return bcd;
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}
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static inline u32 binary_to_gray(u32 bcd)
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{
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return bcd ^ (bcd >> 1);
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}
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static int aml_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct aml_rtc_data *rtc = dev_get_drvdata(dev);
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u32 time_sec;
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/* if RTC disabled, read time failed */
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if (!rtc->rtc_enabled) {
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dev_err(dev, "RTC disabled, read time failed\n");
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return -EINVAL;
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}
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regmap_read(rtc->map, RTC_REAL_TIME, &time_sec);
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if (rtc->config->gray_stored)
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time_sec = gray_to_binary(time_sec);
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rtc_time64_to_tm(time_sec, tm);
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dev_dbg(dev, "%s: read time = %us\n", __func__, time_sec);
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return 0;
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}
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static int aml_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct aml_rtc_data *rtc = dev_get_drvdata(dev);
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u32 time_sec;
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/* if RTC disabled, first enable it */
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if (!rtc->rtc_enabled) {
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regmap_write_bits(rtc->map, RTC_CTRL, RTC_ENABLE, RTC_ENABLE);
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usleep_range(100, 200);
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rtc->rtc_enabled = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ENABLE);
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if (!rtc->rtc_enabled)
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return -EINVAL;
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}
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time_sec = rtc_tm_to_time64(tm);
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if (rtc->config->gray_stored)
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time_sec = binary_to_gray(time_sec);
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regmap_write(rtc->map, RTC_COUNTER_REG, time_sec);
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dev_dbg(dev, "%s: set time = %us\n", __func__, time_sec);
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return 0;
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}
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static int aml_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct aml_rtc_data *rtc = dev_get_drvdata(dev);
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time64_t alarm_sec;
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/* if RTC disabled, set alarm failed */
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if (!rtc->rtc_enabled) {
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dev_err(dev, "RTC disabled, set alarm failed\n");
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return -EINVAL;
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}
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regmap_update_bits(rtc->map, RTC_CTRL,
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RTC_ALRM0_EN, RTC_ALRM0_EN);
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regmap_update_bits(rtc->map, RTC_INT_MASK,
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RTC_ALRM0_IRQ_MSK, 0);
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alarm_sec = rtc_tm_to_time64(&alarm->time);
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if (rtc->config->gray_stored)
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alarm_sec = binary_to_gray(alarm_sec);
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regmap_write(rtc->map, RTC_ALARM0_REG, alarm_sec);
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dev_dbg(dev, "%s: alarm->enabled=%d alarm_set=%llds\n", __func__,
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alarm->enabled, alarm_sec);
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return 0;
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}
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static int aml_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct aml_rtc_data *rtc = dev_get_drvdata(dev);
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u32 alarm_sec;
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int alarm_enable;
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int alarm_mask;
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/* if RTC disabled, read alarm failed */
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if (!rtc->rtc_enabled) {
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dev_err(dev, "RTC disabled, read alarm failed\n");
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return -EINVAL;
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}
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regmap_read(rtc->map, RTC_ALARM0_REG, &alarm_sec);
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if (rtc->config->gray_stored)
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alarm_sec = gray_to_binary(alarm_sec);
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rtc_time64_to_tm(alarm_sec, &alarm->time);
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alarm_enable = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN);
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alarm_mask = regmap_test_bits(rtc->map, RTC_INT_MASK, RTC_ALRM0_IRQ_MSK);
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alarm->enabled = (alarm_enable && !alarm_mask) ? 1 : 0;
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dev_dbg(dev, "%s: alarm->enabled=%d alarm=%us\n", __func__,
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alarm->enabled, alarm_sec);
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return 0;
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}
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static int aml_rtc_read_offset(struct device *dev, long *offset)
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{
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struct aml_rtc_data *rtc = dev_get_drvdata(dev);
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u32 reg_val;
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long val;
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int sign, match_counter, enable;
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/* if RTC disabled, read offset failed */
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if (!rtc->rtc_enabled) {
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dev_err(dev, "RTC disabled, read offset failed\n");
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return -EINVAL;
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}
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regmap_read(rtc->map, RTC_SEC_ADJUST_REG, ®_val);
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enable = FIELD_GET(RTC_ADJ_VALID, reg_val);
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if (!enable) {
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val = 0;
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} else {
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sign = FIELD_GET(RTC_SEC_ADJUST_CTRL, reg_val);
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match_counter = FIELD_GET(RTC_MATCH_COUNTER, reg_val);
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val = 1000000000 / (match_counter + 1);
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if (sign == RTC_SWALLOW_SECOND)
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val = -val;
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}
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*offset = val;
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return 0;
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}
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static int aml_rtc_set_offset(struct device *dev, long offset)
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{
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struct aml_rtc_data *rtc = dev_get_drvdata(dev);
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int sign = 0;
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int match_counter = 0;
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int enable = 0;
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u32 reg_val;
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/* if RTC disabled, set offset failed */
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if (!rtc->rtc_enabled) {
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dev_err(dev, "RTC disabled, set offset failed\n");
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return -EINVAL;
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}
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if (offset) {
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enable = 1;
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sign = offset < 0 ? RTC_SWALLOW_SECOND : RTC_INSERT_SECOND;
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match_counter = 1000000000 / abs(offset) - 1;
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if (match_counter < 0 || match_counter > RTC_MATCH_COUNTER)
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return -EINVAL;
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}
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reg_val = FIELD_PREP(RTC_ADJ_VALID, enable) |
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FIELD_PREP(RTC_SEC_ADJUST_CTRL, sign) |
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FIELD_PREP(RTC_MATCH_COUNTER, match_counter);
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regmap_write(rtc->map, RTC_SEC_ADJUST_REG, reg_val);
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return 0;
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}
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static int aml_rtc_alarm_enable(struct device *dev, unsigned int enabled)
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{
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struct aml_rtc_data *rtc = dev_get_drvdata(dev);
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if (enabled) {
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regmap_update_bits(rtc->map, RTC_CTRL,
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RTC_ALRM0_EN, RTC_ALRM0_EN);
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regmap_update_bits(rtc->map, RTC_INT_MASK,
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RTC_ALRM0_IRQ_MSK, 0);
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} else {
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regmap_update_bits(rtc->map, RTC_INT_MASK,
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RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK);
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regmap_update_bits(rtc->map, RTC_CTRL,
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RTC_ALRM0_EN, 0);
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}
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return 0;
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}
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static const struct rtc_class_ops aml_rtc_ops = {
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.read_time = aml_rtc_read_time,
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.set_time = aml_rtc_set_time,
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.read_alarm = aml_rtc_read_alarm,
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.set_alarm = aml_rtc_set_alarm,
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.alarm_irq_enable = aml_rtc_alarm_enable,
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.read_offset = aml_rtc_read_offset,
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.set_offset = aml_rtc_set_offset,
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};
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static irqreturn_t aml_rtc_handler(int irq, void *data)
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{
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struct aml_rtc_data *rtc = (struct aml_rtc_data *)data;
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regmap_write(rtc->map, RTC_ALARM0_REG, 0);
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regmap_write(rtc->map, RTC_INT_CLR, RTC_ALRM0_IRQ_STATUS);
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rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
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return IRQ_HANDLED;
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}
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static void aml_rtc_init(struct aml_rtc_data *rtc)
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{
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u32 reg_val = 0;
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rtc->rtc_enabled = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ENABLE);
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if (!rtc->rtc_enabled) {
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if (clk_get_rate(rtc->rtc_clk) == OSC_24M) {
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/* select 24M oscillator */
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regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, RTC_OSC_SEL);
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/*
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* Set RTC oscillator to freq_out to freq_in/((N0*M0+N1*M1)/(M0+M1))
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* Enable clock_in gate of oscillator 24MHz
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* Set N0 to 733, N1 to 732
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*/
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reg_val = FIELD_PREP(RTC_OSCIN_IN_EN, 1)
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| FIELD_PREP(RTC_OSCIN_OUT_CFG, 1)
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| FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_N0)
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| FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_N1);
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regmap_write_bits(rtc->map, RTC_OSCIN_CTRL0, RTC_OSCIN_IN_EN
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| RTC_OSCIN_OUT_CFG | RTC_OSCIN_OUT_N0M0
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| RTC_OSCIN_OUT_N1M1, reg_val);
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/* Set M0 to 2, M1 to 3, so freq_out = 32768 Hz*/
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reg_val = FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_M0)
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| FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_M1);
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regmap_write_bits(rtc->map, RTC_OSCIN_CTRL1, RTC_OSCIN_OUT_N0M0
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| RTC_OSCIN_OUT_N1M1, reg_val);
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} else {
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/* select 32K oscillator */
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regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, 0);
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}
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}
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regmap_write_bits(rtc->map, RTC_INT_MASK,
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RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK);
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regmap_write_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN, 0);
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}
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static int aml_rtc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct aml_rtc_data *rtc;
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void __iomem *base;
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int ret = 0;
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rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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rtc->config = of_device_get_match_data(dev);
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if (!rtc->config)
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return -ENODEV;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return dev_err_probe(dev, PTR_ERR(base), "resource ioremap failed\n");
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rtc->map = devm_regmap_init_mmio(dev, base, &aml_rtc_regmap_config);
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if (IS_ERR(rtc->map))
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return dev_err_probe(dev, PTR_ERR(rtc->map), "regmap init failed\n");
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rtc->irq = platform_get_irq(pdev, 0);
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if (rtc->irq < 0)
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return rtc->irq;
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rtc->rtc_clk = devm_clk_get(dev, "osc");
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if (IS_ERR(rtc->rtc_clk))
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return dev_err_probe(dev, PTR_ERR(rtc->rtc_clk),
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"failed to find rtc clock\n");
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if (clk_get_rate(rtc->rtc_clk) != OSC_32K && clk_get_rate(rtc->rtc_clk) != OSC_24M)
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return dev_err_probe(dev, -EINVAL, "Invalid clock configuration\n");
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rtc->sys_clk = devm_clk_get_enabled(dev, "sys");
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if (IS_ERR(rtc->sys_clk))
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return dev_err_probe(dev, PTR_ERR(rtc->sys_clk),
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"failed to get_enable rtc sys clk\n");
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aml_rtc_init(rtc);
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device_init_wakeup(dev, 1);
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platform_set_drvdata(pdev, rtc);
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rtc->rtc_dev = devm_rtc_allocate_device(dev);
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if (IS_ERR(rtc->rtc_dev)) {
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ret = PTR_ERR(rtc->rtc_dev);
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goto err_clk;
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}
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ret = devm_request_irq(dev, rtc->irq, aml_rtc_handler,
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IRQF_ONESHOT, "aml-rtc alarm", rtc);
|
||||
if (ret) {
|
||||
dev_err_probe(dev, ret, "IRQ%d request failed, ret = %d\n",
|
||||
rtc->irq, ret);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
rtc->rtc_dev->ops = &aml_rtc_ops;
|
||||
rtc->rtc_dev->range_min = 0;
|
||||
rtc->rtc_dev->range_max = U32_MAX;
|
||||
|
||||
ret = devm_rtc_register_device(rtc->rtc_dev);
|
||||
if (ret) {
|
||||
dev_err_probe(&pdev->dev, ret, "Failed to register RTC device: %d\n", ret);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
err_clk:
|
||||
clk_disable_unprepare(rtc->sys_clk);
|
||||
device_init_wakeup(dev, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int aml_rtc_suspend(struct device *dev)
|
||||
{
|
||||
struct aml_rtc_data *rtc = dev_get_drvdata(dev);
|
||||
|
||||
if (device_may_wakeup(dev))
|
||||
enable_irq_wake(rtc->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aml_rtc_resume(struct device *dev)
|
||||
{
|
||||
struct aml_rtc_data *rtc = dev_get_drvdata(dev);
|
||||
|
||||
if (device_may_wakeup(dev))
|
||||
disable_irq_wake(rtc->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(aml_rtc_pm_ops,
|
||||
aml_rtc_suspend, aml_rtc_resume);
|
||||
|
||||
static void aml_rtc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct aml_rtc_data *rtc = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
clk_disable_unprepare(rtc->sys_clk);
|
||||
device_init_wakeup(&pdev->dev, 0);
|
||||
}
|
||||
|
||||
static const struct aml_rtc_config a5_rtc_config = {
|
||||
};
|
||||
|
||||
static const struct aml_rtc_config a4_rtc_config = {
|
||||
.gray_stored = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id aml_rtc_device_id[] = {
|
||||
{
|
||||
.compatible = "amlogic,a4-rtc",
|
||||
.data = &a4_rtc_config,
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,a5-rtc",
|
||||
.data = &a5_rtc_config,
|
||||
},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, aml_rtc_device_id);
|
||||
|
||||
static struct platform_driver aml_rtc_driver = {
|
||||
.probe = aml_rtc_probe,
|
||||
.remove = aml_rtc_remove,
|
||||
.driver = {
|
||||
.name = "aml-rtc",
|
||||
.pm = &aml_rtc_pm_ops,
|
||||
.of_match_table = aml_rtc_device_id,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(aml_rtc_driver);
|
||||
MODULE_DESCRIPTION("Amlogic RTC driver");
|
||||
MODULE_AUTHOR("Yiting Deng <yiting.deng@amlogic.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user