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soundwire: intel_auxdevice: add kernel parameter for mclk divider
Add a kernel parameter to work-around discrepancies between hardware and platform firmware, it's not unusual to see e.g. 38.4MHz listed in _DSD properties as the SoundWire clock source, but the hardware may be based on a 19.2 MHz mclk source. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20241004021850.9758-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -159,6 +159,7 @@ is applicable::
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SCSI Appropriate SCSI support is enabled.
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A lot of drivers have their options described inside
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the Documentation/scsi/ sub-directory.
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SDW SoundWire support is enabled.
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SECURITY Different security models are enabled.
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SELINUX SELinux support is enabled.
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SERIAL Serial support is enabled.
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@ -6060,6 +6060,10 @@
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non-zero "wait" parameter. See weight_single
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and weight_many.
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sdw_mclk_divider=[SDW]
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Specify the MCLK divider for Intel SoundWire buses in
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case the BIOS does not provide the clock rate properly.
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skew_tick= [KNL,EARLY] Offset the periodic timer tick per cpu to mitigate
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xtime_lock contention on larger systems, and/or RCU lock
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contention on all systems with CONFIG_MAXSMP set.
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@ -41,6 +41,10 @@ static int md_flags;
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module_param_named(sdw_md_flags, md_flags, int, 0444);
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MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
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static int mclk_divider;
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module_param_named(sdw_mclk_divider, mclk_divider, int, 0444);
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MODULE_PARM_DESC(sdw_mclk_divider, "SoundWire Intel mclk divider");
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struct wake_capable_part {
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const u16 mfg_id;
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const u16 part_id;
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@ -142,8 +146,12 @@ static int sdw_master_read_intel_prop(struct sdw_bus *bus)
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"intel-sdw-ip-clock",
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&prop->mclk_freq);
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/* the values reported by BIOS are the 2x clock, not the bus clock */
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prop->mclk_freq /= 2;
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if (mclk_divider)
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/* use kernel parameter for BIOS or board work-arounds */
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prop->mclk_freq /= mclk_divider;
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else
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/* the values reported by BIOS are the 2x clock, not the bus clock */
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prop->mclk_freq /= 2;
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fwnode_property_read_u32(link,
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"intel-quirk-mask",
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