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RISC-V: Fix the typo in Scountovf CSR name

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The counter overflow CSR name is "scountovf" not "sscountovf".

Fix the csr name.

Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-2-atishp@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Atish Patra 2024-04-20 08:17:17 -07:00 committed by Anup Patel
parent 9752fed8f6
commit d1927f64e0
2 changed files with 2 additions and 2 deletions
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2
arch/riscv/include/asm/csr.h
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@ -281,7 +281,7 @@
#define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER30H 0xc9e
#define CSR_HPMCOUNTER31H 0xc9f #define CSR_HPMCOUNTER31H 0xc9f
#define CSR_SSCOUNTOVF 0xda0 #define CSR_SCOUNTOVF 0xda0
#define CSR_SSTATUS 0x100 #define CSR_SSTATUS 0x100
#define CSR_SIE 0x104 #define CSR_SIE 0x104

2
drivers/perf/riscv_pmu_sbi.c
View File

@ -27,7 +27,7 @@
#define ALT_SBI_PMU_OVERFLOW(__ovl) \ #define ALT_SBI_PMU_OVERFLOW(__ovl) \
asm volatile(ALTERNATIVE_2( \ asm volatile(ALTERNATIVE_2( \
"csrr %0, " __stringify(CSR_SSCOUNTOVF), \ "csrr %0, " __stringify(CSR_SCOUNTOVF), \
"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
CONFIG_ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU, \