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drm/radeon/kms: add evergreen/cayman CS parser for async DMA (v2)
Allows us to use the DMA ring from userspace. DMA doesn't have a good NOP packet in which to embed the reloc idx, so userspace has to add a reloc for each buffer used and order them to match the command stream. v2: fix address bounds checking Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
cf4ccd016b
commit
d2ead3eaf8
@ -34,6 +34,8 @@
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#define MAX(a,b) (((a)>(b))?(a):(b))
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#define MIN(a,b) (((a)<(b))?(a):(b))
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int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc);
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static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc);
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@ -2815,6 +2817,455 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
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return 0;
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}
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/*
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* DMA
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*/
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#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
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#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
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#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
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#define GET_DMA_NEW(h) (((h) & 0x04000000) >> 26)
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#define GET_DMA_MISC(h) (((h) & 0x0700000) >> 20)
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/**
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* evergreen_dma_cs_parse() - parse the DMA IB
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* @p: parser structure holding parsing context.
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*
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* Parses the DMA IB from the CS ioctl and updates
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* the GPU addresses based on the reloc information and
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* checks for errors. (Evergreen-Cayman)
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* Returns 0 for success and an error on failure.
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**/
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int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
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{
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struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
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struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;
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u32 header, cmd, count, tiled, new_cmd, misc;
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volatile u32 *ib = p->ib.ptr;
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u32 idx, idx_value;
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u64 src_offset, dst_offset, dst2_offset;
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int r;
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do {
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if (p->idx >= ib_chunk->length_dw) {
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DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
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p->idx, ib_chunk->length_dw);
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return -EINVAL;
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}
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idx = p->idx;
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header = radeon_get_ib_value(p, idx);
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cmd = GET_DMA_CMD(header);
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count = GET_DMA_COUNT(header);
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tiled = GET_DMA_T(header);
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new_cmd = GET_DMA_NEW(header);
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misc = GET_DMA_MISC(header);
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switch (cmd) {
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case DMA_PACKET_WRITE:
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r = r600_dma_cs_next_reloc(p, &dst_reloc);
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if (r) {
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DRM_ERROR("bad DMA_PACKET_WRITE\n");
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return -EINVAL;
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}
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if (tiled) {
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dst_offset = ib[idx+1];
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dst_offset <<= 8;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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p->idx += count + 7;
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} else {
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dst_offset = ib[idx+1];
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dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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p->idx += count + 3;
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}
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if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
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dst_offset, radeon_bo_size(dst_reloc->robj));
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return -EINVAL;
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}
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break;
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case DMA_PACKET_COPY:
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r = r600_dma_cs_next_reloc(p, &src_reloc);
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if (r) {
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DRM_ERROR("bad DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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r = r600_dma_cs_next_reloc(p, &dst_reloc);
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if (r) {
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DRM_ERROR("bad DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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if (tiled) {
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idx_value = radeon_get_ib_value(p, idx + 2);
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if (new_cmd) {
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switch (misc) {
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case 0:
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/* L2T, frame to fields */
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if (idx_value & (1 << 31)) {
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DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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r = r600_dma_cs_next_reloc(p, &dst2_reloc);
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if (r) {
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DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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dst_offset = ib[idx+1];
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dst_offset <<= 8;
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dst2_offset = ib[idx+2];
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dst2_offset <<= 8;
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src_offset = ib[idx+8];
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src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
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if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
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src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
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return -EINVAL;
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}
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if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
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dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
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return -EINVAL;
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}
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if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
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dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
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return -EINVAL;
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}
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
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ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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p->idx += 10;
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break;
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case 1:
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/* L2T, T2L partial */
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if (p->family < CHIP_CAYMAN) {
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DRM_ERROR("L2T, T2L Partial is cayman only !\n");
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return -EINVAL;
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}
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/* detile bit */
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if (idx_value & (1 << 31)) {
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/* tiled src, linear dst */
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ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
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ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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} else {
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/* linear src, tiled dst */
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ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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}
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p->idx += 12;
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break;
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case 3:
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/* L2T, broadcast */
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if (idx_value & (1 << 31)) {
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DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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r = r600_dma_cs_next_reloc(p, &dst2_reloc);
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if (r) {
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DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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dst_offset = ib[idx+1];
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dst_offset <<= 8;
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dst2_offset = ib[idx+2];
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dst2_offset <<= 8;
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src_offset = ib[idx+8];
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src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
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if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
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src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
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return -EINVAL;
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}
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if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
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dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
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return -EINVAL;
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}
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if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
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dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
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return -EINVAL;
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}
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
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ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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p->idx += 10;
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break;
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case 4:
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/* L2T, T2L */
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/* detile bit */
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if (idx_value & (1 << 31)) {
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/* tiled src, linear dst */
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src_offset = ib[idx+1];
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src_offset <<= 8;
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ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
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dst_offset = ib[idx+7];
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dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
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ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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} else {
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/* linear src, tiled dst */
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src_offset = ib[idx+7];
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src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
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ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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dst_offset = ib[idx+1];
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dst_offset <<= 8;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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}
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if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
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src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
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return -EINVAL;
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}
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if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
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dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
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return -EINVAL;
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}
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p->idx += 9;
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break;
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case 5:
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/* T2T partial */
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if (p->family < CHIP_CAYMAN) {
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DRM_ERROR("L2T, T2L Partial is cayman only !\n");
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return -EINVAL;
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}
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ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
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ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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p->idx += 13;
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break;
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case 7:
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/* L2T, broadcast */
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if (idx_value & (1 << 31)) {
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DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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r = r600_dma_cs_next_reloc(p, &dst2_reloc);
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if (r) {
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DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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dst_offset = ib[idx+1];
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dst_offset <<= 8;
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dst2_offset = ib[idx+2];
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dst2_offset <<= 8;
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src_offset = ib[idx+8];
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src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
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if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
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src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
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return -EINVAL;
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}
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if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
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dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
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return -EINVAL;
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}
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if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
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dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
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return -EINVAL;
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}
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
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ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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p->idx += 10;
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break;
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default:
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DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
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return -EINVAL;
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}
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} else {
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switch (misc) {
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case 0:
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/* detile bit */
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if (idx_value & (1 << 31)) {
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/* tiled src, linear dst */
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src_offset = ib[idx+1];
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src_offset <<= 8;
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ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
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dst_offset = ib[idx+7];
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dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
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ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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} else {
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/* linear src, tiled dst */
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src_offset = ib[idx+7];
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src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
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ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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dst_offset = ib[idx+1];
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dst_offset <<= 8;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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}
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if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
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src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
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return -EINVAL;
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}
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if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
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dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
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return -EINVAL;
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}
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p->idx += 9;
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break;
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default:
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DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
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return -EINVAL;
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}
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}
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} else {
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if (new_cmd) {
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switch (misc) {
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case 0:
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/* L2L, byte */
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src_offset = ib[idx+2];
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src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
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dst_offset = ib[idx+1];
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dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
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if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
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dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n",
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src_offset + count, radeon_bo_size(src_reloc->robj));
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return -EINVAL;
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}
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if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n",
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dst_offset + count, radeon_bo_size(dst_reloc->robj));
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return -EINVAL;
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}
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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p->idx += 5;
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break;
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case 1:
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/* L2L, partial */
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if (p->family < CHIP_CAYMAN) {
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DRM_ERROR("L2L Partial is cayman only !\n");
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return -EINVAL;
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}
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ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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p->idx += 9;
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break;
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case 4:
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/* L2L, dw, broadcast */
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r = r600_dma_cs_next_reloc(p, &dst2_reloc);
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if (r) {
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DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
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return -EINVAL;
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}
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dst_offset = ib[idx+1];
|
||||
dst_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
|
||||
dst2_offset = ib[idx+2];
|
||||
dst2_offset |= ((u64)(ib[idx+5] & 0xff)) << 32;
|
||||
src_offset = ib[idx+3];
|
||||
src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
|
||||
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
|
||||
dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
|
||||
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
|
||||
dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n",
|
||||
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
|
||||
dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n",
|
||||
dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
|
||||
return -EINVAL;
|
||||
}
|
||||
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
|
||||
ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
|
||||
ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
|
||||
ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
|
||||
ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
|
||||
ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
|
||||
p->idx += 7;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
/* L2L, dw */
|
||||
src_offset = ib[idx+2];
|
||||
src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
|
||||
dst_offset = ib[idx+1];
|
||||
dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
|
||||
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
|
||||
dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
|
||||
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
|
||||
dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
|
||||
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
|
||||
return -EINVAL;
|
||||
}
|
||||
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
|
||||
ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
|
||||
ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
|
||||
ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
|
||||
p->idx += 5;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case DMA_PACKET_CONSTANT_FILL:
|
||||
r = r600_dma_cs_next_reloc(p, &dst_reloc);
|
||||
if (r) {
|
||||
DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
dst_offset = ib[idx+1];
|
||||
dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
|
||||
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
|
||||
dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
|
||||
dst_offset, radeon_bo_size(dst_reloc->robj));
|
||||
return -EINVAL;
|
||||
}
|
||||
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
|
||||
ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
|
||||
p->idx += 4;
|
||||
break;
|
||||
case DMA_PACKET_NOP:
|
||||
p->idx += 1;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
|
||||
#if 0
|
||||
for (r = 0; r < p->ib->length_dw; r++) {
|
||||
printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
|
||||
mdelay(1);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* vm parser */
|
||||
static bool evergreen_vm_reg_valid(u32 reg)
|
||||
{
|
||||
|
||||
@ -1204,7 +1204,7 @@ static struct radeon_asic evergreen_asic = {
|
||||
.ib_execute = &evergreen_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.cs_parse = &evergreen_dma_cs_parse,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
@ -1288,7 +1288,7 @@ static struct radeon_asic sumo_asic = {
|
||||
.ib_execute = &evergreen_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.cs_parse = &evergreen_dma_cs_parse,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
@ -1372,7 +1372,7 @@ static struct radeon_asic btc_asic = {
|
||||
.ib_execute = &evergreen_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.cs_parse = &evergreen_dma_cs_parse,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
@ -1486,7 +1486,7 @@ static struct radeon_asic cayman_asic = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.cs_parse = &evergreen_dma_cs_parse,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
@ -1496,7 +1496,7 @@ static struct radeon_asic cayman_asic = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.cs_parse = &evergreen_dma_cs_parse,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
@ -1611,7 +1611,7 @@ static struct radeon_asic trinity_asic = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.cs_parse = &evergreen_dma_cs_parse,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
@ -1621,7 +1621,7 @@ static struct radeon_asic trinity_asic = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.cs_parse = &evergreen_dma_cs_parse,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
|
||||
@ -431,6 +431,7 @@ u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
|
||||
int evergreen_irq_set(struct radeon_device *rdev);
|
||||
int evergreen_irq_process(struct radeon_device *rdev);
|
||||
extern int evergreen_cs_parse(struct radeon_cs_parser *p);
|
||||
extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
|
||||
extern void evergreen_pm_misc(struct radeon_device *rdev);
|
||||
extern void evergreen_pm_prepare(struct radeon_device *rdev);
|
||||
extern void evergreen_pm_finish(struct radeon_device *rdev);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user