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cxl/pci: Remove duplicate host_bridge->native_aer checking

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cxl_dport_init_ras_reporting() already checks host_bridge->native_aer
before invoking cxl_disable_rch_root_ints(), so
cxl_disable_rch_root_ints() does not need to check it again.

Signed-off-by: Li Ming <ming4.li@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240830061308.2327065-3-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Li Ming 2024-08-30 06:13:08 +00:00 committed by Dave Jiang
parent c8706cc15a
commit d75ccd4f2e
1 changed files with 6 additions and 11 deletions
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5
drivers/cxl/core/pci.c
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@ -800,14 +800,11 @@ static void cxl_dport_map_ras(struct cxl_dport *dport)
static void cxl_disable_rch_root_ints(struct cxl_dport *dport) static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
{ {
void __iomem *aer_base = dport->regs.dport_aer; void __iomem *aer_base = dport->regs.dport_aer;
struct pci_host_bridge *bridge;
u32 aer_cmd_mask, aer_cmd; u32 aer_cmd_mask, aer_cmd;
if (!aer_base) if (!aer_base)
return; return;
bridge = to_pci_host_bridge(dport->dport_dev);
/* /*
* Disable RCH root port command interrupts. * Disable RCH root port command interrupts.
* CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
@ -816,7 +813,6 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
* the root cmd register's interrupts is required. But, PCI spec * the root cmd register's interrupts is required. But, PCI spec
* shows these are disabled by default on reset. * shows these are disabled by default on reset.
*/ */
if (bridge->native_aer) {
aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
PCI_ERR_ROOT_CMD_NONFATAL_EN | PCI_ERR_ROOT_CMD_NONFATAL_EN |
PCI_ERR_ROOT_CMD_FATAL_EN); PCI_ERR_ROOT_CMD_FATAL_EN);
@ -824,7 +820,6 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
aer_cmd &= ~aer_cmd_mask; aer_cmd &= ~aer_cmd_mask;
writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
} }
}
/** /**
* cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport