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mmc: Add quirk MMC_QUIRK_BROKEN_CACHE_FLUSH for Micron eMMC Q2J54A
commit ed9009ad300c0f15a3ecfe9613547b1962bde02c upstream. Micron MTFC4GACAJCN eMMC supports cache but requires that flush cache operation be allowed only after a write has occurred. Otherwise, the cache flush command or subsequent commands will time out. Signed-off-by: Bean Huo <beanhuo@micron.com> Signed-off-by: Rafael Beims <rafael.beims@toradex.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231030224809.59245-1-beanhuo@iokpp.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -2389,8 +2389,10 @@ enum mmc_issued mmc_blk_mq_issue_rq(struct mmc_queue *mq, struct request *req)
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}
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ret = mmc_blk_cqe_issue_flush(mq, req);
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break;
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case REQ_OP_READ:
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case REQ_OP_WRITE:
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card->written_flag = true;
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fallthrough;
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case REQ_OP_READ:
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if (host->cqe_enabled)
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ret = mmc_blk_cqe_issue_rw_rq(mq, req);
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else
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@ -280,4 +280,8 @@ static inline int mmc_card_broken_sd_cache(const struct mmc_card *c)
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return c->quirks & MMC_QUIRK_BROKEN_SD_CACHE;
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}
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static inline int mmc_card_broken_cache_flush(const struct mmc_card *c)
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{
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return c->quirks & MMC_QUIRK_BROKEN_CACHE_FLUSH;
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}
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#endif
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@ -2081,13 +2081,17 @@ static int _mmc_flush_cache(struct mmc_host *host)
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{
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int err = 0;
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if (mmc_card_broken_cache_flush(host->card) && !host->card->written_flag)
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return 0;
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if (_mmc_cache_enabled(host)) {
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err = mmc_switch(host->card, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_FLUSH_CACHE, 1,
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CACHE_FLUSH_TIMEOUT_MS);
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if (err)
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pr_err("%s: cache flush error %d\n",
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mmc_hostname(host), err);
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pr_err("%s: cache flush error %d\n", mmc_hostname(host), err);
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else
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host->card->written_flag = false;
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}
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return err;
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@ -110,11 +110,12 @@ static const struct mmc_fixup __maybe_unused mmc_blk_fixups[] = {
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MMC_QUIRK_TRIM_BROKEN),
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/*
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* Micron MTFC4GACAJCN-1M advertises TRIM but it does not seems to
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* support being used to offload WRITE_ZEROES.
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* Micron MTFC4GACAJCN-1M supports TRIM but does not appear to support
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* WRITE_ZEROES offloading. It also supports caching, but the cache can
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* only be flushed after a write has occurred.
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*/
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MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc,
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MMC_QUIRK_TRIM_BROKEN),
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MMC_QUIRK_TRIM_BROKEN | MMC_QUIRK_BROKEN_CACHE_FLUSH),
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/*
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* Kingston EMMC04G-M627 advertises TRIM but it does not seems to
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@ -295,7 +295,9 @@ struct mmc_card {
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#define MMC_QUIRK_BROKEN_HPI (1<<13) /* Disable broken HPI support */
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#define MMC_QUIRK_BROKEN_SD_DISCARD (1<<14) /* Disable broken SD discard support */
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#define MMC_QUIRK_BROKEN_SD_CACHE (1<<15) /* Disable broken SD cache support */
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#define MMC_QUIRK_BROKEN_CACHE_FLUSH (1<<16) /* Don't flush cache until the write has occurred */
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bool written_flag; /* Indicates eMMC has been written since power on */
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bool reenable_cmdq; /* Re-enable Command Queue */
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unsigned int erase_size; /* erase size in sectors */
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