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dmaengine: fsl-edma: fix eDMAv4 channel allocation issue

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The eDMAv4 channel mux has a limitation where certain requests must use
even channels, while others must use odd numbers.

Add two flags (ARGS_EVEN_CH and ARGS_ODD_CH) to reflect this limitation.
The device tree source (dts) files need to be updated accordingly.

This issue was identified by the following commit:
commit a725990557 ("arm64: dts: imx93: Fix the dmas entries order")

Reverting channel orders triggered this problem.

Fixes: 72f5801a4e ("dmaengine: fsl-edma: integrate v3 support")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20231114154824.3617255-2-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Frank Li 2023-11-14 10:48:21 -05:00 committed by Vinod Koul
parent f60dfe0c56
commit dc51b4442d
1 changed files with 8 additions and 0 deletions
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8
drivers/dma/fsl-edma-main.c
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@ -24,6 +24,8 @@
#define ARGS_RX BIT(0)
#define ARGS_REMOTE BIT(1)
#define ARGS_MULTI_FIFO BIT(2)
#define ARGS_EVEN_CH BIT(3)
#define ARGS_ODD_CH BIT(4)
static void fsl_edma_synchronize(struct dma_chan *chan)
{
@ -157,6 +159,12 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO;
if ((dma_spec->args[2] & ARGS_EVEN_CH) && (i & 0x1))
continue;
if ((dma_spec->args[2] & ARGS_ODD_CH) && !(i & 0x1))
continue;
if (!b_chmux && i == dma_spec->args[0]) {
chan = dma_get_slave_channel(chan);
chan->device->privatecnt++;