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clk: renesas: Add family-specific clock driver for RZ/V2H(P)
Add family-specific clock driver for RZ/V2H(P) SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
Geert Uytterhoeven
parent
042859e80d
commit
dd22e56217
@ -228,6 +228,10 @@ config CLK_RZG2L
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bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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config CLK_RZV2H
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bool "RZ/V2H(P) family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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# Generic
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config CLK_RENESAS_CPG_MSSR
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bool "CPG/MSSR clock support" if COMPILE_TEST
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@ -46,6 +46,7 @@ obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
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obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o
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obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
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obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
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obj-$(CONFIG_CLK_RZV2H) += rzv2h-cpg.o
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# Generic
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obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
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684
drivers/clk/renesas/rzv2h-cpg.c
Normal file
684
drivers/clk/renesas/rzv2h-cpg.c
Normal file
@ -0,0 +1,684 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/V2H(P) Clock Pulse Generator
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*
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* Based on rzg2l-cpg.c
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*
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* Copyright (C) 2015 Glider bvba
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "rzv2h-cpg.h"
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#ifdef DEBUG
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#define WARN_DEBUG(x) WARN_ON(x)
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#else
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#define WARN_DEBUG(x) do { } while (0)
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#endif
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#define GET_CLK_ON_OFFSET(x) (0x600 + ((x) * 4))
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#define GET_CLK_MON_OFFSET(x) (0x800 + ((x) * 4))
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#define GET_RST_OFFSET(x) (0x900 + ((x) * 4))
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#define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4))
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#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
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#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
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#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
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#define SDIV(val) FIELD_GET(GENMASK(2, 0), (val))
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#define GET_MOD_CLK_ID(base, index, bit) \
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((base) + ((((index) * (16))) + (bit)))
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/**
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* struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
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*
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* @dev: CPG device
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* @base: CPG register block base address
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* @clks: Array containing all Core and Module Clocks
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* @num_core_clks: Number of Core Clocks in clks[]
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* @num_mod_clks: Number of Module Clocks in clks[]
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* @resets: Array of resets
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* @num_resets: Number of Module Resets in info->resets[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @rcdev: Reset controller entity
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*/
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struct rzv2h_cpg_priv {
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struct device *dev;
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void __iomem *base;
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struct clk **clks;
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unsigned int num_core_clks;
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unsigned int num_mod_clks;
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struct rzv2h_reset *resets;
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unsigned int num_resets;
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unsigned int last_dt_core_clk;
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struct reset_controller_dev rcdev;
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};
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#define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev)
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struct pll_clk {
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struct rzv2h_cpg_priv *priv;
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void __iomem *base;
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struct clk_hw hw;
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unsigned int conf;
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unsigned int type;
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};
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#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
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/**
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* struct mod_clock - Module clock
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*
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* @priv: CPG private data
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* @hw: handle between common and hardware-specific interfaces
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* @on_index: register offset
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* @on_bit: ON/MON bit
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* @mon_index: monitor register offset
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* @mon_bit: montor bit
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*/
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struct mod_clock {
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struct rzv2h_cpg_priv *priv;
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struct clk_hw hw;
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u8 on_index;
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u8 on_bit;
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s8 mon_index;
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u8 mon_bit;
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};
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#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
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static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pll_clk *pll_clk = to_pll(hw);
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struct rzv2h_cpg_priv *priv = pll_clk->priv;
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unsigned int clk1, clk2;
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u64 rate;
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if (!PLL_CLK_ACCESS(pll_clk->conf))
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return 0;
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clk1 = readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf));
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clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf));
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rate = mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1),
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16 + SDIV(clk2));
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return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1));
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}
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static const struct clk_ops rzv2h_cpg_pll_ops = {
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.recalc_rate = rzv2h_cpg_pll_clk_recalc_rate,
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};
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static struct clk * __init
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rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
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struct rzv2h_cpg_priv *priv,
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const struct clk_ops *ops)
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{
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void __iomem *base = priv->base;
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struct device *dev = priv->dev;
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struct clk_init_data init;
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const struct clk *parent;
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const char *parent_name;
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struct pll_clk *pll_clk;
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int ret;
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parent = priv->clks[core->parent];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return ERR_PTR(-ENOMEM);
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parent_name = __clk_get_name(parent);
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init.name = core->name;
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init.ops = ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll_clk->hw.init = &init;
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pll_clk->conf = core->conf;
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pll_clk->base = base;
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pll_clk->priv = priv;
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pll_clk->type = core->type;
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ret = devm_clk_hw_register(dev, &pll_clk->hw);
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if (ret)
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return ERR_PTR(ret);
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return pll_clk->hw.clk;
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}
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static struct clk
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*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
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void *data)
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{
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unsigned int clkidx = clkspec->args[1];
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struct rzv2h_cpg_priv *priv = data;
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struct device *dev = priv->dev;
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const char *type;
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struct clk *clk;
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switch (clkspec->args[0]) {
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case CPG_CORE:
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type = "core";
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if (clkidx > priv->last_dt_core_clk) {
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dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
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return ERR_PTR(-EINVAL);
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}
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clk = priv->clks[clkidx];
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break;
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case CPG_MOD:
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type = "module";
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if (clkidx >= priv->num_mod_clks) {
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dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
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return ERR_PTR(-EINVAL);
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}
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clk = priv->clks[priv->num_core_clks + clkidx];
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break;
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default:
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dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
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return ERR_PTR(-EINVAL);
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}
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if (IS_ERR(clk))
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dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
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PTR_ERR(clk));
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else
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dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
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clkspec->args[0], clkspec->args[1], clk,
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clk_get_rate(clk));
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return clk;
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}
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static void __init
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rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
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struct rzv2h_cpg_priv *priv)
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{
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struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
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unsigned int id = core->id, div = core->div;
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struct device *dev = priv->dev;
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const char *parent_name;
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struct clk_hw *clk_hw;
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WARN_DEBUG(id >= priv->num_core_clks);
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WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
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switch (core->type) {
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case CLK_TYPE_IN:
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clk = of_clk_get_by_name(priv->dev->of_node, core->name);
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break;
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case CLK_TYPE_FF:
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WARN_DEBUG(core->parent >= priv->num_core_clks);
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parent = priv->clks[core->parent];
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if (IS_ERR(parent)) {
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clk = parent;
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goto fail;
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}
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parent_name = __clk_get_name(parent);
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clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name,
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parent_name, CLK_SET_RATE_PARENT,
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core->mult, div);
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if (IS_ERR(clk_hw))
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clk = ERR_CAST(clk_hw);
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else
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clk = clk_hw->clk;
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break;
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case CLK_TYPE_PLL:
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clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops);
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break;
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default:
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goto fail;
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}
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if (IS_ERR_OR_NULL(clk))
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goto fail;
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dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
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priv->clks[id] = clk;
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return;
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fail:
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dev_err(dev, "Failed to register core clock %s: %ld\n",
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core->name, PTR_ERR(clk));
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}
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static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
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{
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struct mod_clock *clock = to_mod_clock(hw);
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unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);
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struct rzv2h_cpg_priv *priv = clock->priv;
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u32 bitmask = BIT(clock->on_bit);
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struct device *dev = priv->dev;
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u32 value;
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int error;
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dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
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enable ? "ON" : "OFF");
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value = bitmask << 16;
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if (enable)
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value |= bitmask;
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writel(value, priv->base + reg);
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if (!enable || clock->mon_index < 0)
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return 0;
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reg = GET_CLK_MON_OFFSET(clock->mon_index);
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bitmask = BIT(clock->mon_bit);
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error = readl_poll_timeout_atomic(priv->base + reg, value,
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value & bitmask, 0, 10);
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if (error)
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dev_err(dev, "Failed to enable CLK_ON %p\n",
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priv->base + reg);
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return error;
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}
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static int rzv2h_mod_clock_enable(struct clk_hw *hw)
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{
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return rzv2h_mod_clock_endisable(hw, true);
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}
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static void rzv2h_mod_clock_disable(struct clk_hw *hw)
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{
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rzv2h_mod_clock_endisable(hw, false);
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}
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static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
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{
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struct mod_clock *clock = to_mod_clock(hw);
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struct rzv2h_cpg_priv *priv = clock->priv;
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u32 bitmask;
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u32 offset;
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if (clock->mon_index >= 0) {
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offset = GET_CLK_MON_OFFSET(clock->mon_index);
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bitmask = BIT(clock->mon_bit);
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} else {
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offset = GET_CLK_ON_OFFSET(clock->on_index);
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bitmask = BIT(clock->on_bit);
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}
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return readl(priv->base + offset) & bitmask;
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}
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static const struct clk_ops rzv2h_mod_clock_ops = {
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.enable = rzv2h_mod_clock_enable,
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.disable = rzv2h_mod_clock_disable,
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.is_enabled = rzv2h_mod_clock_is_enabled,
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};
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static void __init
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rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
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struct rzv2h_cpg_priv *priv)
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{
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struct mod_clock *clock = NULL;
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struct device *dev = priv->dev;
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struct clk_init_data init;
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struct clk *parent, *clk;
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const char *parent_name;
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unsigned int id;
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int ret;
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id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit);
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WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
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WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
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WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
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parent = priv->clks[mod->parent];
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if (IS_ERR(parent)) {
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clk = parent;
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goto fail;
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}
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clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
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if (!clock) {
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clk = ERR_PTR(-ENOMEM);
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goto fail;
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}
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init.name = mod->name;
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init.ops = &rzv2h_mod_clock_ops;
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init.flags = CLK_SET_RATE_PARENT;
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if (mod->critical)
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init.flags |= CLK_IS_CRITICAL;
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parent_name = __clk_get_name(parent);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clock->on_index = mod->on_index;
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clock->on_bit = mod->on_bit;
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clock->mon_index = mod->mon_index;
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clock->mon_bit = mod->mon_bit;
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clock->priv = priv;
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clock->hw.init = &init;
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ret = devm_clk_hw_register(dev, &clock->hw);
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if (ret) {
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clk = ERR_PTR(ret);
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goto fail;
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}
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priv->clks[id] = clock->hw.clk;
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return;
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fail:
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dev_err(dev, "Failed to register module clock %s: %ld\n",
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mod->name, PTR_ERR(clk));
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}
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static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
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unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
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u32 mask = BIT(priv->resets[id].reset_bit);
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u8 monbit = priv->resets[id].mon_bit;
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u32 value = mask << 16;
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dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
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writel(value, priv->base + reg);
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reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
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mask = BIT(monbit);
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return readl_poll_timeout_atomic(priv->base + reg, value,
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value & mask, 10, 200);
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}
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static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
|
||||
struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
|
||||
u32 mask = BIT(priv->resets[id].reset_bit);
|
||||
u8 monbit = priv->resets[id].mon_bit;
|
||||
u32 value = (mask << 16) | mask;
|
||||
|
||||
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
|
||||
|
||||
writel(value, priv->base + reg);
|
||||
|
||||
reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
|
||||
mask = BIT(monbit);
|
||||
|
||||
return readl_poll_timeout_atomic(priv->base + reg, value,
|
||||
!(value & mask), 10, 200);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = rzv2h_cpg_assert(rcdev, id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return rzv2h_cpg_deassert(rcdev, id);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
|
||||
u8 monbit = priv->resets[id].mon_bit;
|
||||
|
||||
return !!(readl(priv->base + reg) & BIT(monbit));
|
||||
}
|
||||
|
||||
static const struct reset_control_ops rzv2h_cpg_reset_ops = {
|
||||
.reset = rzv2h_cpg_reset,
|
||||
.assert = rzv2h_cpg_assert,
|
||||
.deassert = rzv2h_cpg_deassert,
|
||||
.status = rzv2h_cpg_status,
|
||||
};
|
||||
|
||||
static int rzv2h_cpg_reset_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int id = reset_spec->args[0];
|
||||
u8 rst_index = id / 16;
|
||||
u8 rst_bit = id % 16;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < rcdev->nr_resets; i++) {
|
||||
if (rst_index == priv->resets[i].reset_index &&
|
||||
rst_bit == priv->resets[i].reset_bit)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_reset_controller_register(struct rzv2h_cpg_priv *priv)
|
||||
{
|
||||
priv->rcdev.ops = &rzv2h_cpg_reset_ops;
|
||||
priv->rcdev.of_node = priv->dev->of_node;
|
||||
priv->rcdev.dev = priv->dev;
|
||||
priv->rcdev.of_reset_n_cells = 1;
|
||||
priv->rcdev.of_xlate = rzv2h_cpg_reset_xlate;
|
||||
priv->rcdev.nr_resets = priv->num_resets;
|
||||
|
||||
return devm_reset_controller_register(priv->dev, &priv->rcdev);
|
||||
}
|
||||
|
||||
/**
|
||||
* struct rzv2h_cpg_pd - RZ/V2H power domain data structure
|
||||
* @priv: pointer to CPG private data structure
|
||||
* @genpd: generic PM domain
|
||||
*/
|
||||
struct rzv2h_cpg_pd {
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
struct generic_pm_domain genpd;
|
||||
};
|
||||
|
||||
static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
bool once = true;
|
||||
struct clk *clk;
|
||||
int error;
|
||||
int i = 0;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (once) {
|
||||
once = false;
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
of_node_put(clkspec.np);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
if (IS_ERR(clk)) {
|
||||
error = PTR_ERR(clk);
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk failed %d\n",
|
||||
error);
|
||||
goto fail_put;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail_put:
|
||||
clk_put(clk);
|
||||
|
||||
fail_destroy:
|
||||
pm_clk_destroy(dev);
|
||||
err:
|
||||
return error;
|
||||
}
|
||||
|
||||
static void rzv2h_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
if (!pm_clk_no_clocks(dev))
|
||||
pm_clk_destroy(dev);
|
||||
}
|
||||
|
||||
static void rzv2h_cpg_genpd_remove_simple(void *data)
|
||||
{
|
||||
pm_genpd_remove(data);
|
||||
}
|
||||
|
||||
static int __init rzv2h_cpg_add_pm_domains(struct rzv2h_cpg_priv *priv)
|
||||
{
|
||||
struct device *dev = priv->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct rzv2h_cpg_pd *pd;
|
||||
int ret;
|
||||
|
||||
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
pd->genpd.name = np->name;
|
||||
pd->priv = priv;
|
||||
pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
pd->genpd.attach_dev = rzv2h_cpg_attach_dev;
|
||||
pd->genpd.detach_dev = rzv2h_cpg_detach_dev;
|
||||
ret = pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd->genpd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return of_genpd_add_provider_simple(np, &pd->genpd);
|
||||
}
|
||||
|
||||
static void rzv2h_cpg_del_clk_provider(void *data)
|
||||
{
|
||||
of_clk_del_provider(data);
|
||||
}
|
||||
|
||||
static int __init rzv2h_cpg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct rzv2h_cpg_info *info;
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
unsigned int nclks, i;
|
||||
struct clk **clks;
|
||||
int error;
|
||||
|
||||
info = of_device_get_match_data(dev);
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = dev;
|
||||
|
||||
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
||||
clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
|
||||
info->num_resets, GFP_KERNEL);
|
||||
if (!priv->resets)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_set_drvdata(dev, priv);
|
||||
priv->clks = clks;
|
||||
priv->num_core_clks = info->num_total_core_clks;
|
||||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
priv->num_resets = info->num_resets;
|
||||
|
||||
for (i = 0; i < nclks; i++)
|
||||
clks[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
for (i = 0; i < info->num_core_clks; i++)
|
||||
rzv2h_cpg_register_core_clk(&info->core_clks[i], priv);
|
||||
|
||||
for (i = 0; i < info->num_mod_clks; i++)
|
||||
rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv);
|
||||
|
||||
error = of_clk_add_provider(np, rzv2h_cpg_clk_src_twocell_get, priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = devm_add_action_or_reset(dev, rzv2h_cpg_del_clk_provider, np);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = rzv2h_cpg_add_pm_domains(priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = rzv2h_cpg_reset_controller_register(priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rzv2h_cpg_match[] = {
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver rzv2h_cpg_driver = {
|
||||
.driver = {
|
||||
.name = "rzv2h-cpg",
|
||||
.of_match_table = rzv2h_cpg_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rzv2h_cpg_init(void)
|
||||
{
|
||||
return platform_driver_probe(&rzv2h_cpg_driver, rzv2h_cpg_probe);
|
||||
}
|
||||
|
||||
subsys_initcall(rzv2h_cpg_init);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas RZ/V2H CPG Driver");
|
||||
149
drivers/clk/renesas/rzv2h-cpg.h
Normal file
149
drivers/clk/renesas/rzv2h-cpg.h
Normal file
@ -0,0 +1,149 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Renesas RZ/V2H(P) Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __RENESAS_RZV2H_CPG_H__
|
||||
#define __RENESAS_RZV2H_CPG_H__
|
||||
|
||||
/**
|
||||
* Definitions of CPG Core Clocks
|
||||
*
|
||||
* These include:
|
||||
* - Clock outputs exported to DT
|
||||
* - External input clocks
|
||||
* - Internal CPG clocks
|
||||
*/
|
||||
struct cpg_core_clk {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int parent;
|
||||
unsigned int div;
|
||||
unsigned int mult;
|
||||
unsigned int type;
|
||||
unsigned int conf;
|
||||
};
|
||||
|
||||
enum clk_types {
|
||||
/* Generic */
|
||||
CLK_TYPE_IN, /* External Clock Input */
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_PLL,
|
||||
};
|
||||
|
||||
/* BIT(31) indicates if CLK1/2 are accessible or not */
|
||||
#define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16)))
|
||||
#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0)
|
||||
#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16))
|
||||
#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4))
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
{ .name = _name, .id = _id, .type = _type }
|
||||
#define DEF_BASE(_name, _id, _type, _parent...) \
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
#define DEF_PLL(_name, _id, _parent, _conf) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .conf = _conf)
|
||||
#define DEF_INPUT(_name, _id) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN)
|
||||
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
|
||||
|
||||
/**
|
||||
* struct rzv2h_mod_clk - Module Clocks definitions
|
||||
*
|
||||
* @name: handle between common and hardware-specific interfaces
|
||||
* @parent: id of parent clock
|
||||
* @critical: flag to indicate the clock is critical
|
||||
* @on_index: control register index
|
||||
* @on_bit: ON bit
|
||||
* @mon_index: monitor register index
|
||||
* @mon_bit: monitor bit
|
||||
*/
|
||||
struct rzv2h_mod_clk {
|
||||
const char *name;
|
||||
u16 parent;
|
||||
bool critical;
|
||||
u8 on_index;
|
||||
u8 on_bit;
|
||||
s8 mon_index;
|
||||
u8 mon_bit;
|
||||
};
|
||||
|
||||
#define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _monindex, _monbit) \
|
||||
{ \
|
||||
.name = (_name), \
|
||||
.parent = (_parent), \
|
||||
.critical = (_critical), \
|
||||
.on_index = (_onindex), \
|
||||
.on_bit = (_onbit), \
|
||||
.mon_index = (_monindex), \
|
||||
.mon_bit = (_monbit), \
|
||||
}
|
||||
|
||||
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
|
||||
DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
|
||||
DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
/**
|
||||
* struct rzv2h_reset - Reset definitions
|
||||
*
|
||||
* @reset_index: reset register index
|
||||
* @reset_bit: reset bit
|
||||
* @mon_index: monitor register index
|
||||
* @mon_bit: monitor bit
|
||||
*/
|
||||
struct rzv2h_reset {
|
||||
u8 reset_index;
|
||||
u8 reset_bit;
|
||||
u8 mon_index;
|
||||
u8 mon_bit;
|
||||
};
|
||||
|
||||
#define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) \
|
||||
{ \
|
||||
.reset_index = (_resindex), \
|
||||
.reset_bit = (_resbit), \
|
||||
.mon_index = (_monindex), \
|
||||
.mon_bit = (_monbit), \
|
||||
}
|
||||
|
||||
#define DEF_RST(_resindex, _resbit, _monindex, _monbit) \
|
||||
DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)
|
||||
|
||||
/**
|
||||
* struct rzv2h_cpg_info - SoC-specific CPG Description
|
||||
*
|
||||
* @core_clks: Array of Core Clock definitions
|
||||
* @num_core_clks: Number of entries in core_clks[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @num_total_core_clks: Total number of Core Clocks (exported + internal)
|
||||
*
|
||||
* @mod_clks: Array of Module Clock definitions
|
||||
* @num_mod_clks: Number of entries in mod_clks[]
|
||||
* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
|
||||
*
|
||||
* @resets: Array of Module Reset definitions
|
||||
* @num_resets: Number of entries in resets[]
|
||||
*/
|
||||
struct rzv2h_cpg_info {
|
||||
/* Core Clocks */
|
||||
const struct cpg_core_clk *core_clks;
|
||||
unsigned int num_core_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
unsigned int num_total_core_clks;
|
||||
|
||||
/* Module Clocks */
|
||||
const struct rzv2h_mod_clk *mod_clks;
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int num_hw_mod_clks;
|
||||
|
||||
/* Resets */
|
||||
const struct rzv2h_reset *resets;
|
||||
unsigned int num_resets;
|
||||
};
|
||||
|
||||
#endif /* __RENESAS_RZV2H_CPG_H__ */
|
||||
Loading…
x
Reference in New Issue
Block a user