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pwm: stm32: Implementation of the waveform callbacks
Convert the stm32 pwm driver to use the new callbacks for hardware programming. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/332d4f736d8360038d03f109c013441c655eea23.1726819463.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
This commit is contained in:
Uwe Kleine-König
Uwe Kleine-König
parent
eb18504ca5
commit
deaba9cff8
@ -51,6 +51,391 @@ static u32 active_channels(struct stm32_pwm *dev)
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return ccer & TIM_CCER_CCXE;
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}
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struct stm32_pwm_waveform {
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u32 ccer;
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u32 psc;
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u32 arr;
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u32 ccr;
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};
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static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const struct pwm_waveform *wf,
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void *_wfhw)
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{
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struct stm32_pwm_waveform *wfhw = _wfhw;
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
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unsigned int ch = pwm->hwpwm;
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unsigned long rate;
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u64 ccr, duty;
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int ret;
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if (wf->period_length_ns == 0) {
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*wfhw = (struct stm32_pwm_waveform){
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.ccer = 0,
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};
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return 0;
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}
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ret = clk_enable(priv->clk);
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if (ret)
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return ret;
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wfhw->ccer = TIM_CCER_CCxE(ch + 1);
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if (priv->have_complementary_output)
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wfhw->ccer = TIM_CCER_CCxNE(ch + 1);
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rate = clk_get_rate(priv->clk);
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if (active_channels(priv) & ~(1 << ch * 4)) {
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u64 arr;
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/*
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* Other channels are already enabled, so the configured PSC and
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* ARR must be used for this channel, too.
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*/
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ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
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if (ret)
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goto out;
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ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
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if (ret)
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goto out;
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/*
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* calculate the best value for ARR for the given PSC, refuse if
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* the resulting period gets bigger than the requested one.
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*/
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arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
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(u64)NSEC_PER_SEC * (wfhw->psc + 1));
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if (arr <= wfhw->arr) {
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/*
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* requested period is small than the currently
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* configured and unchangable period, report back the smallest
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* possible period, i.e. the current state; Initialize
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* ccr to anything valid.
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*/
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wfhw->ccr = 0;
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ret = 1;
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goto out;
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}
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} else {
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/*
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* .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
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* the calculations here won't overflow.
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* First we need to find the minimal value for prescaler such that
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*
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* period_ns * clkrate
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* ------------------------------ < max_arr + 1
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* NSEC_PER_SEC * (prescaler + 1)
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*
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* This equation is equivalent to
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*
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* period_ns * clkrate
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* ---------------------------- < prescaler + 1
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* NSEC_PER_SEC * (max_arr + 1)
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*
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* Using integer division and knowing that the right hand side is
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* integer, this is further equivalent to
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*
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* (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
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*/
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u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate,
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(u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
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u64 arr;
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wfhw->psc = min_t(u64, psc, MAX_TIM_PSC);
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arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
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(u64)NSEC_PER_SEC * (wfhw->psc + 1));
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if (!arr) {
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/*
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* requested period is too small, report back the smallest
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* possible period, i.e. ARR = 0. The only valid CCR
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* value is then zero, too.
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*/
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wfhw->arr = 0;
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wfhw->ccr = 0;
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ret = 1;
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goto out;
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}
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/*
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* ARR is limited intentionally to values less than
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* priv->max_arr to allow 100% duty cycle.
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*/
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wfhw->arr = min_t(u64, arr, priv->max_arr) - 1;
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}
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duty = mul_u64_u64_div_u64(wf->duty_length_ns, rate,
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(u64)NSEC_PER_SEC * (wfhw->psc + 1));
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duty = min_t(u64, duty, wfhw->arr + 1);
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if (wf->duty_length_ns && wf->duty_offset_ns &&
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wf->duty_length_ns + wf->duty_offset_ns >= wf->period_length_ns) {
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wfhw->ccer |= TIM_CCER_CCxP(ch + 1);
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if (priv->have_complementary_output)
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wfhw->ccer |= TIM_CCER_CCxNP(ch + 1);
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ccr = wfhw->arr + 1 - duty;
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} else {
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ccr = duty;
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}
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wfhw->ccr = min_t(u64, ccr, wfhw->arr + 1);
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dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x\n",
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pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
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rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr);
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out:
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clk_disable(priv->clk);
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return ret;
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}
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/*
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* This should be moved to lib/math/div64.c. Currently there are some changes
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* pending to mul_u64_u64_div_u64. Uwe will care for that when the dust settles.
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*/
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static u64 stm32_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b, u64 c)
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{
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u64 res = mul_u64_u64_div_u64(a, b, c);
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/* Those multiplications might overflow but it doesn't matter */
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u64 rem = a * b - c * res;
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if (rem)
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res += 1;
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return res;
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}
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static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const void *_wfhw,
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struct pwm_waveform *wf)
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{
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const struct stm32_pwm_waveform *wfhw = _wfhw;
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
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unsigned int ch = pwm->hwpwm;
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if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
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unsigned long rate = clk_get_rate(priv->clk);
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u64 ccr_ns;
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/* The result doesn't overflow for rate >= 15259 */
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wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1),
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NSEC_PER_SEC, rate);
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ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr,
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NSEC_PER_SEC, rate);
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if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) {
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wf->duty_length_ns =
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stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr),
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NSEC_PER_SEC, rate);
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wf->duty_offset_ns = ccr_ns;
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} else {
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wf->duty_length_ns = ccr_ns;
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wf->duty_offset_ns = 0;
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}
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dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]\n",
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pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate,
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wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns);
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} else {
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*wf = (struct pwm_waveform){
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.period_length_ns = 0,
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};
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}
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return 0;
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}
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static int stm32_pwm_read_waveform(struct pwm_chip *chip,
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struct pwm_device *pwm,
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void *_wfhw)
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{
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struct stm32_pwm_waveform *wfhw = _wfhw;
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
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unsigned int ch = pwm->hwpwm;
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int ret;
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ret = clk_enable(priv->clk);
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if (ret)
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return ret;
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ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer);
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if (ret)
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goto out;
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if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
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ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
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if (ret)
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goto out;
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ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
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if (ret)
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goto out;
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if (wfhw->arr == U32_MAX)
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wfhw->arr -= 1;
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ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr);
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if (ret)
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goto out;
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if (wfhw->ccr > wfhw->arr + 1)
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wfhw->ccr = wfhw->arr + 1;
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}
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out:
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clk_disable(priv->clk);
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return ret;
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}
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static int stm32_pwm_write_waveform(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const void *_wfhw)
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{
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const struct stm32_pwm_waveform *wfhw = _wfhw;
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
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unsigned int ch = pwm->hwpwm;
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int ret;
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ret = clk_enable(priv->clk);
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if (ret)
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return ret;
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if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
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u32 ccer, mask;
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unsigned int shift;
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u32 ccmr;
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ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
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if (ret)
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goto out;
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/* If there are other channels enabled, don't update PSC and ARR */
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if (ccer & ~TIM_CCER_CCxE(ch + 1) & TIM_CCER_CCXE) {
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u32 psc, arr;
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ret = regmap_read(priv->regmap, TIM_PSC, &psc);
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if (ret)
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goto out;
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if (psc != wfhw->psc) {
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ret = -EBUSY;
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goto out;
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}
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regmap_read(priv->regmap, TIM_ARR, &arr);
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if (ret)
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goto out;
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if (arr != wfhw->arr) {
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ret = -EBUSY;
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goto out;
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}
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} else {
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ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc);
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if (ret)
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goto out;
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ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr);
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if (ret)
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goto out;
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ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
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if (ret)
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goto out;
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}
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/* set polarity */
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mask = TIM_CCER_CCxP(ch + 1) | TIM_CCER_CCxNP(ch + 1);
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ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer);
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if (ret)
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goto out;
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ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr);
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if (ret)
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goto out;
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/* Configure output mode */
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shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
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ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
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mask = CCMR_CHANNEL_MASK << shift;
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if (ch < 2)
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ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
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else
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ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
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if (ret)
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goto out;
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ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
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if (ret)
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goto out;
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if (!(ccer & TIM_CCER_CCxE(ch + 1))) {
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mask = TIM_CCER_CCxE(ch + 1) | TIM_CCER_CCxNE(ch + 1);
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ret = clk_enable(priv->clk);
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if (ret)
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goto out;
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ccer = (ccer & ~mask) | (wfhw->ccer & mask);
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regmap_write(priv->regmap, TIM_CCER, ccer);
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/* Make sure that registers are updated */
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regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
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/* Enable controller */
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regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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}
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} else {
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/* disable channel */
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u32 mask, ccer;
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mask = TIM_CCER_CCxE(ch + 1);
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if (priv->have_complementary_output)
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mask |= TIM_CCER_CCxNE(ch + 1);
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ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
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if (ret)
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goto out;
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if (ccer & mask) {
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ccer = ccer & ~mask;
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ret = regmap_write(priv->regmap, TIM_CCER, ccer);
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if (ret)
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goto out;
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if (!(ccer & TIM_CCER_CCXE)) {
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/* When all channels are disabled, we can disable the controller */
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ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
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if (ret)
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goto out;
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}
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clk_disable(priv->clk);
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}
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}
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out:
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clk_disable(priv->clk);
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return ret;
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}
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#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
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#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
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#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
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@ -308,228 +693,13 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
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return ret;
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}
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static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
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u64 duty_ns, u64 period_ns)
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{
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unsigned long long prd, dty;
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unsigned long long prescaler;
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u32 ccmr, mask, shift;
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/*
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* .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
|
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* the calculations here won't overflow.
|
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* First we need to find the minimal value for prescaler such that
|
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*
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* period_ns * clkrate
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* ------------------------------ < max_arr + 1
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* NSEC_PER_SEC * (prescaler + 1)
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*
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* This equation is equivalent to
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*
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* period_ns * clkrate
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* ---------------------------- < prescaler + 1
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* NSEC_PER_SEC * (max_arr + 1)
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*
|
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* Using integer division and knowing that the right hand side is
|
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* integer, this is further equivalent to
|
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*
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* (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
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*/
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prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
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(u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
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if (prescaler > MAX_TIM_PSC)
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return -EINVAL;
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prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
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(u64)NSEC_PER_SEC * (prescaler + 1));
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if (!prd)
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return -EINVAL;
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/*
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* All channels share the same prescaler and counter so when two
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* channels are active at the same time we can't change them
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*/
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if (active_channels(priv) & ~(1 << ch * 4)) {
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u32 psc, arr;
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regmap_read(priv->regmap, TIM_PSC, &psc);
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regmap_read(priv->regmap, TIM_ARR, &arr);
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if ((psc != prescaler) || (arr != prd - 1))
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return -EBUSY;
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}
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regmap_write(priv->regmap, TIM_PSC, prescaler);
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regmap_write(priv->regmap, TIM_ARR, prd - 1);
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regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
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|
||||
/* Calculate the duty cycles */
|
||||
dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk),
|
||||
(u64)NSEC_PER_SEC * (prescaler + 1));
|
||||
|
||||
regmap_write(priv->regmap, TIM_CCRx(ch + 1), dty);
|
||||
|
||||
/* Configure output mode */
|
||||
shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
|
||||
ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
|
||||
mask = CCMR_CHANNEL_MASK << shift;
|
||||
|
||||
if (ch < 2)
|
||||
regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
|
||||
else
|
||||
regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
|
||||
|
||||
regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,
|
||||
enum pwm_polarity polarity)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
mask = TIM_CCER_CCxP(ch + 1);
|
||||
if (priv->have_complementary_output)
|
||||
mask |= TIM_CCER_CCxNP(ch + 1);
|
||||
|
||||
regmap_update_bits(priv->regmap, TIM_CCER, mask,
|
||||
polarity == PWM_POLARITY_NORMAL ? 0 : mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)
|
||||
{
|
||||
u32 mask;
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable channel */
|
||||
mask = TIM_CCER_CCxE(ch + 1);
|
||||
if (priv->have_complementary_output)
|
||||
mask |= TIM_CCER_CCxNE(ch + 1);
|
||||
|
||||
regmap_set_bits(priv->regmap, TIM_CCER, mask);
|
||||
|
||||
/* Make sure that registers are updated */
|
||||
regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
|
||||
|
||||
/* Enable controller */
|
||||
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
/* Disable channel */
|
||||
mask = TIM_CCER_CCxE(ch + 1);
|
||||
if (priv->have_complementary_output)
|
||||
mask |= TIM_CCER_CCxNE(ch + 1);
|
||||
|
||||
regmap_clear_bits(priv->regmap, TIM_CCER, mask);
|
||||
|
||||
/* When all channels are disabled, we can disable the controller */
|
||||
if (!active_channels(priv))
|
||||
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
|
||||
|
||||
clk_disable(priv->clk);
|
||||
}
|
||||
|
||||
static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
const struct pwm_state *state)
|
||||
{
|
||||
bool enabled;
|
||||
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
|
||||
int ret;
|
||||
|
||||
enabled = pwm->state.enabled;
|
||||
|
||||
if (!state->enabled) {
|
||||
if (enabled)
|
||||
stm32_pwm_disable(priv, pwm->hwpwm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (state->polarity != pwm->state.polarity)
|
||||
stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
|
||||
|
||||
ret = stm32_pwm_config(priv, pwm->hwpwm,
|
||||
state->duty_cycle, state->period);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!enabled && state->enabled)
|
||||
ret = stm32_pwm_enable(priv, pwm->hwpwm);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
const struct pwm_state *state)
|
||||
{
|
||||
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
|
||||
int ret;
|
||||
|
||||
/* protect common prescaler for all active channels */
|
||||
mutex_lock(&priv->lock);
|
||||
ret = stm32_pwm_apply(chip, pwm, state);
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_pwm_get_state(struct pwm_chip *chip,
|
||||
struct pwm_device *pwm, struct pwm_state *state)
|
||||
{
|
||||
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
|
||||
int ch = pwm->hwpwm;
|
||||
unsigned long rate;
|
||||
u32 ccer, psc, arr, ccr;
|
||||
u64 dty, prd;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
|
||||
ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
state->enabled = ccer & TIM_CCER_CCxE(ch + 1);
|
||||
state->polarity = (ccer & TIM_CCER_CCxP(ch + 1)) ?
|
||||
PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
|
||||
ret = regmap_read(priv->regmap, TIM_PSC, &psc);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = regmap_read(priv->regmap, TIM_ARR, &arr);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &ccr);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
rate = clk_get_rate(priv->clk);
|
||||
|
||||
prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);
|
||||
state->period = DIV_ROUND_UP_ULL(prd, rate);
|
||||
dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;
|
||||
state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
|
||||
|
||||
out:
|
||||
mutex_unlock(&priv->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct pwm_ops stm32pwm_ops = {
|
||||
.apply = stm32_pwm_apply_locked,
|
||||
.get_state = stm32_pwm_get_state,
|
||||
.sizeof_wfhw = sizeof(struct stm32_pwm_waveform),
|
||||
.round_waveform_tohw = stm32_pwm_round_waveform_tohw,
|
||||
.round_waveform_fromhw = stm32_pwm_round_waveform_fromhw,
|
||||
.read_waveform = stm32_pwm_read_waveform,
|
||||
.write_waveform = stm32_pwm_write_waveform,
|
||||
|
||||
.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user