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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-01-10 23:20:05 +00:00
spi: davinci: add support for interrupt mode
Add support for SPI interrupt mode operation. Define a per chip-select "io type" variable which specifies if the transfers on this chip-select should happen in interrupt mode or polled mode. Introduce a new function davinci_spi_process_events() to help consolidate the code between interrupt mode processing and polled mode processing. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
Brian Niebuhr
Sekhar Nori
parent
839c996ca8
commit
e0d205e991
@ -30,6 +30,7 @@ struct davinci_spi_platform_data {
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u8 version;
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u8 num_chipselect;
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u8 clk_internal;
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u8 intr_line;
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u8 use_dma;
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u8 *chip_sel;
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};
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@ -38,6 +39,9 @@ struct davinci_spi_config {
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u8 wdelay;
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u8 odd_parity;
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u8 parity_enable;
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#define SPI_IO_TYPE_INTR 0
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#define SPI_IO_TYPE_POLL 1
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u8 io_type;
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u8 timer_disable;
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u8 c2tdelay;
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u8 t2cdelay;
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@ -59,6 +59,9 @@
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#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
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#define SPIINT_MASKALL 0x0101035F
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#define SPIINT_MASKINT 0x0000015F
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#define SPI_INTLVL_1 0x000001FF
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#define SPI_INTLVL_0 0x00000000
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/* SPIDAT1 (upper 16 bit defines) */
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#define SPIDAT1_CSHOLD_MASK BIT(12)
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@ -132,10 +135,14 @@ struct davinci_spi {
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resource_size_t pbase;
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void __iomem *base;
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size_t region_size;
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u32 irq;
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struct completion done;
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const void *tx;
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void *rx;
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u8 *tmp_buf;
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int rcount;
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int wcount;
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struct davinci_spi_dma *dma_channels;
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struct davinci_spi_platform_data *pdata;
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@ -593,6 +600,43 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
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return 0;
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}
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/**
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* davinci_spi_process_events - check for and handle any SPI controller events
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* @davinci_spi: the controller data
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*
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* This function will check the SPIFLG register and handle any events that are
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* detected there
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*/
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static int davinci_spi_process_events(struct davinci_spi *davinci_spi)
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{
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u32 buf, status, errors = 0, data1_reg_val;
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buf = ioread32(davinci_spi->base + SPIBUF);
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if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
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davinci_spi->get_rx(buf & 0xFFFF, davinci_spi);
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davinci_spi->rcount--;
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}
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status = ioread32(davinci_spi->base + SPIFLG);
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if (unlikely(status & SPIFLG_ERROR_MASK)) {
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errors = status & SPIFLG_ERROR_MASK;
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goto out;
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}
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if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
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data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
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davinci_spi->wcount--;
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data1_reg_val &= ~0xFFFF;
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data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi);
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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}
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out:
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return errors;
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}
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/**
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* davinci_spi_bufs - functions which will handle transfer data
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* @spi: spi device on which data transfer to be done
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@ -606,18 +650,22 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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{
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struct davinci_spi *davinci_spi;
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int ret;
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int rcount, wcount;
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u32 tx_data, data1_reg_val;
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u32 errors = 0;
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struct davinci_spi_config *spicfg;
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struct davinci_spi_platform_data *pdata;
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davinci_spi = spi_master_get_devdata(spi->master);
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pdata = davinci_spi->pdata;
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spicfg = (struct davinci_spi_config *)spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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davinci_spi->tx = t->tx_buf;
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davinci_spi->rx = t->rx_buf;
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wcount = t->len / davinci_spi->bytes_per_word[spi->chip_select];
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rcount = wcount;
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davinci_spi->wcount = t->len /
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davinci_spi->bytes_per_word[spi->chip_select];
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davinci_spi->rcount = davinci_spi->wcount;
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ret = davinci_spi_bufs_prep(spi, davinci_spi);
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if (ret)
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@ -628,42 +676,32 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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/* Enable SPI */
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
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if (spicfg->io_type == SPI_IO_TYPE_INTR) {
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set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
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INIT_COMPLETION(davinci_spi->done);
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}
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/* start the transfer */
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wcount--;
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davinci_spi->wcount--;
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tx_data = davinci_spi->get_tx(davinci_spi);
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data1_reg_val &= 0xFFFF0000;
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data1_reg_val |= tx_data & 0xFFFF;
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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while (rcount > 0 || wcount > 0) {
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u32 buf, status;
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buf = ioread32(davinci_spi->base + SPIBUF);
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if (!(buf & SPIBUF_RXEMPTY_MASK)) {
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davinci_spi->get_rx(buf & 0xFFFF, davinci_spi);
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rcount--;
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}
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status = ioread32(davinci_spi->base + SPIFLG);
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if (unlikely(status & SPIFLG_ERROR_MASK)) {
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errors = status & SPIFLG_ERROR_MASK;
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break;
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}
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if (wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
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wcount--;
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tx_data = davinci_spi->get_tx(davinci_spi);
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data1_reg_val &= ~0xFFFF;
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data1_reg_val |= 0xFFFF & tx_data;
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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/* Wait for the transfer to complete */
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if (spicfg->io_type == SPI_IO_TYPE_INTR) {
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wait_for_completion_interruptible(&(davinci_spi->done));
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} else {
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while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) {
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errors = davinci_spi_process_events(davinci_spi);
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if (errors)
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break;
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cpu_relax();
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}
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}
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
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/*
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* Check for bit error, desync error,parity error,timeout error and
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* receive overflow errors
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@ -678,6 +716,32 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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return t->len;
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}
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/**
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* davinci_spi_irq - Interrupt handler for SPI Master Controller
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* @irq: IRQ number for this SPI Master
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* @context_data: structure for SPI Master controller davinci_spi
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*
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* ISR will determine that interrupt arrives either for READ or WRITE command.
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* According to command it will do the appropriate action. It will check
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* transfer length and if it is not zero then dispatch transfer command again.
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* If transfer length is zero then it will indicate the COMPLETION so that
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* davinci_spi_bufs function can go ahead.
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*/
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static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
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{
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struct davinci_spi *davinci_spi = context_data;
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int status;
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status = davinci_spi_process_events(davinci_spi);
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if (unlikely(status != 0))
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
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if ((!davinci_spi->rcount && !davinci_spi->wcount) || status)
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complete(&davinci_spi->done);
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return IRQ_HANDLED;
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}
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static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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{
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struct davinci_spi *davinci_spi;
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@ -866,11 +930,22 @@ static int davinci_spi_probe(struct platform_device *pdev)
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goto release_region;
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}
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davinci_spi->irq = platform_get_irq(pdev, 0);
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if (davinci_spi->irq <= 0) {
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ret = -EINVAL;
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goto unmap_io;
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}
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ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0,
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dev_name(&pdev->dev), davinci_spi);
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if (ret)
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goto unmap_io;
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/* Allocate tmp_buf for tx_buf */
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davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
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if (davinci_spi->tmp_buf == NULL) {
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ret = -ENOMEM;
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goto unmap_io;
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goto irq_free;
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}
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davinci_spi->bitbang.master = spi_master_get(master);
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@ -946,6 +1021,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
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davinci_spi->get_rx = davinci_spi_rx_buf_u8;
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davinci_spi->get_tx = davinci_spi_tx_buf_u8;
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init_completion(&davinci_spi->done);
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/* Reset In/OUT SPI module */
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iowrite32(0, davinci_spi->base + SPIGCR0);
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udelay(100);
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@ -967,6 +1044,11 @@ static int davinci_spi_probe(struct platform_device *pdev)
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clear_io_bits(davinci_spi->base + SPIGCR1,
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SPIGCR1_CLKMOD_MASK);
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if (pdata->intr_line)
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iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
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else
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iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
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iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
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/* master mode default */
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@ -987,6 +1069,8 @@ put_master:
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spi_master_put(master);
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free_tmp_buf:
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kfree(davinci_spi->tmp_buf);
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irq_free:
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free_irq(davinci_spi->irq, davinci_spi);
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unmap_io:
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iounmap(davinci_spi->base);
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release_region:
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@ -1020,6 +1104,7 @@ static int __exit davinci_spi_remove(struct platform_device *pdev)
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clk_put(davinci_spi->clk);
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spi_master_put(master);
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kfree(davinci_spi->tmp_buf);
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free_irq(davinci_spi->irq, davinci_spi);
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iounmap(davinci_spi->base);
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release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
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