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sh: Kill off MAX_DMA_ADDRESS leftovers.
We don't support the ISA DMA API, so this is only ever misused. The dma-sh case inadvertently broke the dreamcast case by testing the wrong variable for the total number of channels, so this fixes that up too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -40,23 +40,6 @@ config NR_ONCHIP_DMA_CHANNELS
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DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the
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DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the
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SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6.
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SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6.
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config NR_DMA_CHANNELS_BOOL
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depends on SH_DMA
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bool "Override default number of maximum DMA channels"
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help
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This allows you to forcibly update the maximum number of supported
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DMA channels for a given board. If this is unset, this will default
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to the number of channels that the on-chip DMAC has.
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config NR_DMA_CHANNELS
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int "Maximum number of DMA channels"
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depends on SH_DMA && NR_DMA_CHANNELS_BOOL
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default NR_ONCHIP_DMA_CHANNELS
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help
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This allows you to specify the maximum number of DMA channels to
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support. Setting this to a higher value allows for cascading DMACs
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with additional channels.
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config SH_DMABRG
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config SH_DMABRG
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bool "SH7760 DMABRG support"
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bool "SH7760 DMABRG support"
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depends on CPU_SUBTYPE_SH7760
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depends on CPU_SUBTYPE_SH7760
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@ -29,7 +29,7 @@ static ssize_t dma_show_devices(struct device *dev,
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ssize_t len = 0;
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ssize_t len = 0;
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int i;
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int i;
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for (i = 0; i < MAX_DMA_CHANNELS; i++) {
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for (i = 0; i < 16; i++) {
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struct dma_info *info = get_dma_info(i);
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struct dma_info *info = get_dma_info(i);
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struct dma_channel *channel = get_dma_channel(i);
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struct dma_channel *channel = get_dma_channel(i);
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@ -32,21 +32,21 @@
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#endif
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#endif
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static int dmte_irq_map[] __maybe_unused = {
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static int dmte_irq_map[] __maybe_unused = {
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#if (MAX_DMA_CHANNELS >= 4)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
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DMTE0_IRQ,
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DMTE0_IRQ,
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DMTE0_IRQ + 1,
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DMTE0_IRQ + 1,
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DMTE0_IRQ + 2,
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DMTE0_IRQ + 2,
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DMTE0_IRQ + 3,
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DMTE0_IRQ + 3,
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#endif
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#endif
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#if (MAX_DMA_CHANNELS >= 6)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
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DMTE4_IRQ,
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DMTE4_IRQ,
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DMTE4_IRQ + 1,
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DMTE4_IRQ + 1,
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#endif
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#endif
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#if (MAX_DMA_CHANNELS >= 8)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
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DMTE6_IRQ,
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DMTE6_IRQ,
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DMTE6_IRQ + 1,
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DMTE6_IRQ + 1,
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#endif
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#endif
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#if (MAX_DMA_CHANNELS >= 12)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
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DMTE8_IRQ,
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DMTE8_IRQ,
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DMTE9_IRQ,
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DMTE9_IRQ,
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DMTE10_IRQ,
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DMTE10_IRQ,
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@ -62,21 +62,21 @@ static int dmte_irq_map[] __maybe_unused = {
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/* DMA base address */
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/* DMA base address */
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static u32 dma_base_addr[] __maybe_unused = {
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static u32 dma_base_addr[] __maybe_unused = {
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#if (MAX_DMA_CHANNELS >= 4)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
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SH_DMAC_BASE0 + 0x00, /* channel 0 */
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SH_DMAC_BASE0 + 0x00, /* channel 0 */
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SH_DMAC_BASE0 + 0x10,
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SH_DMAC_BASE0 + 0x10,
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SH_DMAC_BASE0 + 0x20,
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SH_DMAC_BASE0 + 0x20,
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SH_DMAC_BASE0 + 0x30,
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SH_DMAC_BASE0 + 0x30,
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#endif
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#endif
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#if (MAX_DMA_CHANNELS >= 6)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
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SH_DMAC_BASE0 + 0x50,
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SH_DMAC_BASE0 + 0x50,
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SH_DMAC_BASE0 + 0x60,
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SH_DMAC_BASE0 + 0x60,
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#endif
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#endif
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#if (MAX_DMA_CHANNELS >= 8)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
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SH_DMAC_BASE1 + 0x00,
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SH_DMAC_BASE1 + 0x00,
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SH_DMAC_BASE1 + 0x10,
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SH_DMAC_BASE1 + 0x10,
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#endif
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#endif
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#if (MAX_DMA_CHANNELS >= 12)
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#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
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SH_DMAC_BASE1 + 0x20,
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SH_DMAC_BASE1 + 0x20,
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SH_DMAC_BASE1 + 0x30,
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SH_DMAC_BASE1 + 0x30,
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SH_DMAC_BASE1 + 0x50,
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SH_DMAC_BASE1 + 0x50,
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@ -17,14 +17,6 @@
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#include <linux/device.h>
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#include <linux/device.h>
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#include <asm-generic/dma.h>
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#include <asm-generic/dma.h>
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#ifdef CONFIG_NR_DMA_CHANNELS
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# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
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#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
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# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
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#else
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# define MAX_DMA_CHANNELS 0
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#endif
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/*
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/*
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* Read and write modes can mean drastically different things depending on the
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* Read and write modes can mean drastically different things depending on the
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* channel configuration. Consult your DMAC documentation and module
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* channel configuration. Consult your DMAC documentation and module
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@ -11,9 +11,7 @@
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#define __ASM_SH_DREAMCAST_DMA_H
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#define __ASM_SH_DREAMCAST_DMA_H
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/* Number of DMA channels */
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/* Number of DMA channels */
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#define ONCHIP_NR_DMA_CHANNELS 4
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#define G2_NR_DMA_CHANNELS 4
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#define G2_NR_DMA_CHANNELS 4
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#define PVR2_NR_DMA_CHANNELS 1
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/* Channels for cascading */
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/* Channels for cascading */
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#define PVR2_CASCADE_CHAN 2
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#define PVR2_CASCADE_CHAN 2
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