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spi: bcm-qspi: add support for 3-wire mode for half duplex transfer
This change configures the MSPI controller to use 3-wire interface when a slave device devictree nodes indicates this via the optional property. Signed-off-by: Kamal Dasu <kdasu@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211008203603.40915-4-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -103,6 +103,7 @@
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#define MSPI_MASTER_BIT BIT(7)
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#define MSPI_NUM_CDRAM 16
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#define MSPI_CDRAM_OUTP BIT(8)
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#define MSPI_CDRAM_CONT_BIT BIT(7)
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#define MSPI_CDRAM_BITSE_BIT BIT(6)
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#define MSPI_CDRAM_DT_BIT BIT(5)
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@ -122,6 +123,8 @@
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#define MSPI_SPCR3_DAM_8BYTE 0
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#define MSPI_SPCR3_DAM_16BYTE (BIT(2) | BIT(4))
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#define MSPI_SPCR3_DAM_32BYTE (BIT(3) | BIT(5))
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#define MSPI_SPCR3_HALFDUPLEX BIT(6)
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#define MSPI_SPCR3_HDOUTTYPE BIT(7)
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#define MSPI_SPCR3_DATA_REG_SZ BIT(8)
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#define MSPI_SPCR3_CPHARX BIT(9)
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@ -613,6 +616,9 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
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/* enable fastbr */
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spcr |= MSPI_SPCR3_FASTBR;
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if (xp->mode & SPI_3WIRE)
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spcr |= MSPI_SPCR3_HALFDUPLEX | MSPI_SPCR3_HDOUTTYPE;
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if (bcm_qspi_has_sysclk_108(qspi)) {
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/* SYSCLK_108 */
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spcr |= MSPI_SPCR3_SYSCLKSEL_108;
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@ -940,6 +946,10 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
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mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
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MSPI_CDRAM_BITSE_BIT);
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/* set 3wrire halfduplex mode data from master to slave */
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if ((spi->mode & SPI_3WIRE) && tp.trans->tx_buf)
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mspi_cdram |= MSPI_CDRAM_OUTP;
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if (has_bspi(qspi))
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mspi_cdram &= ~1;
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else
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@ -1480,7 +1490,8 @@ int bcm_qspi_probe(struct platform_device *pdev,
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qspi->master = master;
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master->bus_num = -1;
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master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
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master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD |
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SPI_3WIRE;
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master->setup = bcm_qspi_setup;
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master->transfer_one = bcm_qspi_transfer_one;
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master->mem_ops = &bcm_qspi_mem_ops;
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