mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-01-01 10:45:49 +00:00
A set of fixes for interrupt chip drivers:
- Unbreak the PLIC driver for Allwinner D1 systems
The recent conversion of the PLIC driver to a platform driver broke
Allwinnder D1 systems due to the deferred probing of platform drivers.
Due to that the only timer available on D1 systems cannot get an
interrupt, which causes the system to hang at boot. Other RISCV
platforms are not affected because they provide the architected SBI
timer which uses the built in core interrupt controller.
Cure this by probing PLIC early on D1 systems
- Cure a regression in ARM/GIC-V3 on 32-bit ARM systems caused by the
recent addition of a initialization function, which accesses system
registers before they are enabled. On 64-bit ARM they are enabled
prior to that by sheer luck.
Ensure they are enabled.
- Cure a use before check problem in the MSI library. The existing NULL
pointer check is too late.
- Cure a lock order inversion in the ARM/GIC-V4 driver
- Fix a IS_ERR() vs. NULL pointer check issue in the RISCV APLIC driver
- Plug a reference count leak in the ARM/GIC-V2 driver
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Merge tag 'irq-urgent-2024-08-25' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip
Merge fixes for interrupt chip drivers from tip to avoid a merge
conflict going forward:
"A set of fixes for interrupt chip drivers:
- Unbreak the PLIC driver for Allwinner D1 systems
The recent conversion of the PLIC driver to a platform driver broke
Allwinnder D1 systems due to the deferred probing of platform drivers.
Due to that the only timer available on D1 systems cannot get an
interrupt, which causes the system to hang at boot. Other RISCV
platforms are not affected because they provide the architected SBI
timer which uses the built in core interrupt controller.
Cure this by probing PLIC early on D1 systems
- Cure a regression in ARM/GIC-V3 on 32-bit ARM systems caused by the
recent addition of a initialization function, which accesses system
registers before they are enabled. On 64-bit ARM they are enabled
prior to that by sheer luck.
Ensure they are enabled.
- Cure a use before check problem in the MSI library. The existing NULL
pointer check is too late.
- Cure a lock order inversion in the ARM/GIC-V4 driver
- Fix a IS_ERR() vs. NULL pointer check issue in the RISCV APLIC driver
- Plug a reference count leak in the ARM/GIC-V2 driver"
* tag 'irq-urgent-2024-08-25' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/irq-msi-lib: Check for NULL ops in msi_lib_irq_domain_select()
irqchip/gic-v3: Init SRE before poking sysregs
irqchip/gic-v2m: Fix refcount leak in gicv2m_of_init()
irqchip/riscv-aplic: Fix an IS_ERR() vs NULL bug in probe()
irqchip/gic-v4: Fix ordering between vmapp and vpe locks
irqchip/sifive-plic: Probe plic driver early for Allwinner D1 platform
This commit is contained in:
Rafael J. Wysocki
commit
e9252c3768
@ -407,12 +407,12 @@ static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
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ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,
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&res, 0);
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if (ret) {
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of_node_put(child);
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if (ret)
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break;
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}
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}
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if (ret && child)
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of_node_put(child);
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if (!ret)
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ret = gicv2m_allocate_domains(parent);
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if (ret)
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@ -1329,12 +1329,6 @@ static void its_send_vmovp(struct its_vpe *vpe)
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return;
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}
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/*
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* Protect against concurrent updates of the mapping state on
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* individual VMs.
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*/
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guard(raw_spinlock_irqsave)(&vpe->its_vm->vmapp_lock);
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/*
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* Yet another marvel of the architecture. If using the
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* its_list "feature", we need to make sure that all ITSs
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@ -3824,7 +3818,14 @@ static int its_vpe_set_affinity(struct irq_data *d,
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* protect us, and that we must ensure nobody samples vpe->col_idx
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* during the update, hence the lock below which must also be
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* taken on any vLPI handling path that evaluates vpe->col_idx.
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*
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* Finally, we must protect ourselves against concurrent updates of
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* the mapping state on this VM should the ITS list be in use (see
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* the shortcut in its_send_vmovp() otherewise).
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*/
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if (its_list_map)
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raw_spin_lock(&vpe->its_vm->vmapp_lock);
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from = vpe_to_cpuid_lock(vpe, &flags);
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table_mask = gic_data_rdist_cpu(from)->vpe_table_mask;
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@ -3854,6 +3855,9 @@ static int its_vpe_set_affinity(struct irq_data *d,
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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vpe_to_cpuid_unlock(vpe, flags);
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if (its_list_map)
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raw_spin_unlock(&vpe->its_vm->vmapp_lock);
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return IRQ_SET_MASK_OK_DONE;
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}
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@ -1154,14 +1154,8 @@ static void gic_update_rdist_properties(void)
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gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
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}
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static void gic_cpu_sys_reg_init(void)
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static void gic_cpu_sys_reg_enable(void)
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{
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int i, cpu = smp_processor_id();
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u64 mpidr = gic_cpu_to_affinity(cpu);
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u64 need_rss = MPIDR_RS(mpidr);
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bool group0;
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u32 pribits;
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/*
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* Need to check that the SRE bit has actually been set. If
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* not, it means that SRE is disabled at EL2. We're going to
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@ -1172,6 +1166,16 @@ static void gic_cpu_sys_reg_init(void)
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if (!gic_enable_sre())
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pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
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}
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static void gic_cpu_sys_reg_init(void)
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{
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int i, cpu = smp_processor_id();
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u64 mpidr = gic_cpu_to_affinity(cpu);
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u64 need_rss = MPIDR_RS(mpidr);
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bool group0;
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u32 pribits;
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pribits = gic_get_pribits();
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group0 = gic_has_group0();
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@ -1333,6 +1337,7 @@ static int gic_check_rdist(unsigned int cpu)
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static int gic_starting_cpu(unsigned int cpu)
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{
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gic_cpu_sys_reg_enable();
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gic_cpu_init();
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if (gic_dist_supports_lpis())
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@ -1498,6 +1503,7 @@ static int gic_cpu_pm_notifier(struct notifier_block *self,
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if (cmd == CPU_PM_EXIT) {
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if (gic_dist_security_disabled())
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gic_enable_redist(true);
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gic_cpu_sys_reg_enable();
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gic_cpu_sys_reg_init();
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} else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
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gic_write_grpen1(0);
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@ -2070,6 +2076,7 @@ static int __init gic_init_bases(phys_addr_t dist_phys_base,
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gic_update_rdist_properties();
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gic_cpu_sys_reg_enable();
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gic_prio_init();
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gic_dist_init();
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gic_cpu_init();
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@ -128,6 +128,9 @@ int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec,
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const struct msi_parent_ops *ops = d->msi_parent_ops;
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u32 busmask = BIT(bus_token);
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if (!ops)
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return 0;
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if (fwspec->fwnode != d->fwnode || fwspec->param_count != 0)
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return 0;
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@ -135,6 +138,6 @@ int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec,
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if (bus_token == ops->bus_select_token)
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return 1;
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return ops && !!(ops->bus_select_mask & busmask);
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return !!(ops->bus_select_mask & busmask);
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}
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EXPORT_SYMBOL_GPL(msi_lib_irq_domain_select);
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@ -175,9 +175,9 @@ static int aplic_probe(struct platform_device *pdev)
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/* Map the MMIO registers */
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (!regs) {
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if (IS_ERR(regs)) {
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dev_err(dev, "failed map MMIO registers\n");
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return -ENOMEM;
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return PTR_ERR(regs);
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}
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/*
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@ -3,6 +3,7 @@
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* Copyright (C) 2017 SiFive
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* Copyright (C) 2018 Christoph Hellwig
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*/
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#define pr_fmt(fmt) "riscv-plic: " fmt
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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@ -63,7 +64,7 @@
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#define PLIC_QUIRK_EDGE_INTERRUPT 0
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struct plic_priv {
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struct device *dev;
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struct fwnode_handle *fwnode;
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struct cpumask lmask;
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struct irq_domain *irqdomain;
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void __iomem *regs;
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@ -378,8 +379,8 @@ static void plic_handle_irq(struct irq_desc *desc)
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int err = generic_handle_domain_irq(handler->priv->irqdomain,
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hwirq);
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if (unlikely(err)) {
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dev_warn_ratelimited(handler->priv->dev,
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"can't find mapping for hwirq %lu\n", hwirq);
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pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n",
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handler->priv->fwnode, hwirq);
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}
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}
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@ -408,7 +409,8 @@ static int plic_starting_cpu(unsigned int cpu)
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enable_percpu_irq(plic_parent_irq,
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irq_get_trigger_type(plic_parent_irq));
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else
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dev_warn(handler->priv->dev, "cpu%d: parent irq not available\n", cpu);
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pr_warn("%pfwP: cpu%d: parent irq not available\n",
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handler->priv->fwnode, cpu);
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plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
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return 0;
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@ -424,38 +426,36 @@ static const struct of_device_id plic_match[] = {
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{}
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};
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static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
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static int plic_parse_nr_irqs_and_contexts(struct fwnode_handle *fwnode,
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u32 *nr_irqs, u32 *nr_contexts)
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{
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struct device *dev = &pdev->dev;
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int rc;
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/*
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* Currently, only OF fwnode is supported so extend this
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* function for ACPI support.
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*/
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if (!is_of_node(dev->fwnode))
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if (!is_of_node(fwnode))
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return -EINVAL;
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rc = of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irqs);
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rc = of_property_read_u32(to_of_node(fwnode), "riscv,ndev", nr_irqs);
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if (rc) {
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dev_err(dev, "riscv,ndev property not available\n");
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pr_err("%pfwP: riscv,ndev property not available\n", fwnode);
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return rc;
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}
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*nr_contexts = of_irq_count(to_of_node(dev->fwnode));
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*nr_contexts = of_irq_count(to_of_node(fwnode));
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if (WARN_ON(!(*nr_contexts))) {
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dev_err(dev, "no PLIC context available\n");
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pr_err("%pfwP: no PLIC context available\n", fwnode);
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return -EINVAL;
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}
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return 0;
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}
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static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
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static int plic_parse_context_parent(struct fwnode_handle *fwnode, u32 context,
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u32 *parent_hwirq, int *parent_cpu)
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{
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struct device *dev = &pdev->dev;
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struct of_phandle_args parent;
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unsigned long hartid;
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int rc;
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@ -464,10 +464,10 @@ static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
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* Currently, only OF fwnode is supported so extend this
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* function for ACPI support.
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*/
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if (!is_of_node(dev->fwnode))
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if (!is_of_node(fwnode))
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return -EINVAL;
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rc = of_irq_parse_one(to_of_node(dev->fwnode), context, &parent);
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rc = of_irq_parse_one(to_of_node(fwnode), context, &parent);
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if (rc)
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return rc;
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@ -480,48 +480,55 @@ static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
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return 0;
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}
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static int plic_probe(struct platform_device *pdev)
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static int plic_probe(struct fwnode_handle *fwnode)
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{
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int error = 0, nr_contexts, nr_handlers = 0, cpu, i;
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struct device *dev = &pdev->dev;
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unsigned long plic_quirks = 0;
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struct plic_handler *handler;
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u32 nr_irqs, parent_hwirq;
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struct plic_priv *priv;
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irq_hw_number_t hwirq;
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void __iomem *regs;
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if (is_of_node(dev->fwnode)) {
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if (is_of_node(fwnode)) {
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const struct of_device_id *id;
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id = of_match_node(plic_match, to_of_node(dev->fwnode));
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id = of_match_node(plic_match, to_of_node(fwnode));
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if (id)
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plic_quirks = (unsigned long)id->data;
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regs = of_iomap(to_of_node(fwnode), 0);
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if (!regs)
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return -ENOMEM;
|
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} else {
|
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return -ENODEV;
|
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}
|
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|
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error = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts);
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error = plic_parse_nr_irqs_and_contexts(fwnode, &nr_irqs, &nr_contexts);
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if (error)
|
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return error;
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goto fail_free_regs;
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|
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
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if (!priv)
|
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return -ENOMEM;
|
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
error = -ENOMEM;
|
||||
goto fail_free_regs;
|
||||
}
|
||||
|
||||
priv->dev = dev;
|
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priv->fwnode = fwnode;
|
||||
priv->plic_quirks = plic_quirks;
|
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priv->nr_irqs = nr_irqs;
|
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priv->regs = regs;
|
||||
|
||||
priv->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(!priv->regs))
|
||||
return -EIO;
|
||||
|
||||
priv->prio_save = devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL);
|
||||
if (!priv->prio_save)
|
||||
return -ENOMEM;
|
||||
priv->prio_save = bitmap_zalloc(nr_irqs, GFP_KERNEL);
|
||||
if (!priv->prio_save) {
|
||||
error = -ENOMEM;
|
||||
goto fail_free_priv;
|
||||
}
|
||||
|
||||
for (i = 0; i < nr_contexts; i++) {
|
||||
error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu);
|
||||
error = plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu);
|
||||
if (error) {
|
||||
dev_warn(dev, "hwirq for context%d not found\n", i);
|
||||
pr_warn("%pfwP: hwirq for context%d not found\n", fwnode, i);
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -543,7 +550,7 @@ static int plic_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
if (cpu < 0) {
|
||||
dev_warn(dev, "Invalid cpuid for context %d\n", i);
|
||||
pr_warn("%pfwP: Invalid cpuid for context %d\n", fwnode, i);
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -554,7 +561,7 @@ static int plic_probe(struct platform_device *pdev)
|
||||
*/
|
||||
handler = per_cpu_ptr(&plic_handlers, cpu);
|
||||
if (handler->present) {
|
||||
dev_warn(dev, "handler already present for context %d.\n", i);
|
||||
pr_warn("%pfwP: handler already present for context %d.\n", fwnode, i);
|
||||
plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
|
||||
goto done;
|
||||
}
|
||||
@ -568,8 +575,8 @@ static int plic_probe(struct platform_device *pdev)
|
||||
i * CONTEXT_ENABLE_SIZE;
|
||||
handler->priv = priv;
|
||||
|
||||
handler->enable_save = devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32),
|
||||
sizeof(*handler->enable_save), GFP_KERNEL);
|
||||
handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32),
|
||||
sizeof(*handler->enable_save), GFP_KERNEL);
|
||||
if (!handler->enable_save)
|
||||
goto fail_cleanup_contexts;
|
||||
done:
|
||||
@ -581,7 +588,7 @@ static int plic_probe(struct platform_device *pdev)
|
||||
nr_handlers++;
|
||||
}
|
||||
|
||||
priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
|
||||
priv->irqdomain = irq_domain_add_linear(to_of_node(fwnode), nr_irqs + 1,
|
||||
&plic_irqdomain_ops, priv);
|
||||
if (WARN_ON(!priv->irqdomain))
|
||||
goto fail_cleanup_contexts;
|
||||
@ -619,13 +626,13 @@ static int plic_probe(struct platform_device *pdev)
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n",
|
||||
nr_irqs, nr_handlers, nr_contexts);
|
||||
pr_info("%pfwP: mapped %d interrupts with %d handlers for %d contexts.\n",
|
||||
fwnode, nr_irqs, nr_handlers, nr_contexts);
|
||||
return 0;
|
||||
|
||||
fail_cleanup_contexts:
|
||||
for (i = 0; i < nr_contexts; i++) {
|
||||
if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu))
|
||||
if (plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu))
|
||||
continue;
|
||||
if (parent_hwirq != RV_IRQ_EXT || cpu < 0)
|
||||
continue;
|
||||
@ -634,17 +641,37 @@ static int plic_probe(struct platform_device *pdev)
|
||||
handler->present = false;
|
||||
handler->hart_base = NULL;
|
||||
handler->enable_base = NULL;
|
||||
kfree(handler->enable_save);
|
||||
handler->enable_save = NULL;
|
||||
handler->priv = NULL;
|
||||
}
|
||||
return -ENOMEM;
|
||||
bitmap_free(priv->prio_save);
|
||||
fail_free_priv:
|
||||
kfree(priv);
|
||||
fail_free_regs:
|
||||
iounmap(regs);
|
||||
return error;
|
||||
}
|
||||
|
||||
static int plic_platform_probe(struct platform_device *pdev)
|
||||
{
|
||||
return plic_probe(pdev->dev.fwnode);
|
||||
}
|
||||
|
||||
static struct platform_driver plic_driver = {
|
||||
.driver = {
|
||||
.name = "riscv-plic",
|
||||
.of_match_table = plic_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = plic_probe,
|
||||
.probe = plic_platform_probe,
|
||||
};
|
||||
builtin_platform_driver(plic_driver);
|
||||
|
||||
static int __init plic_early_probe(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return plic_probe(&node->fwnode);
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user