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MediaTek soc driver updates for v6.8
This adds a refactoring of the MediaTek Smart Voltage Scaling (SVS) driver and the addition of support for MT8186 and MT8195 in it, and adds support for the MT8188 VDOSYS and resets in the MMSYS driver. -----BEGIN PGP SIGNATURE----- iJ4EABYKAEYWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCZXhDfCgcYW5nZWxvZ2lv YWNjaGluby5kZWxyZWdub0Bjb2xsYWJvcmEuY29tAAoJEJo2BM+tl4R4OrMA/1mb WUMKzPfmPNQ6aARR1laOJYPC3RaXPJMnt5OloSD7AQDkQV2XqqleSvKrhl6JcoYa 3UfhW/oGLx+dPQ+2+pKsDw== =rGbq -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWFbzcACgkQYKtH/8kJ Uie7hg//ZrPvNdvSNbqJLEuteK/U72HnJpPE5vfNif+JMVYc7qxRX/JPy+M1n2aA xcmWrlTo6SiR4ML9Fh7EFCMzPYDNweIaVOQTxSGhLkrLEgj7kZtSkB+hvpdkqnxB GbFEZW/g68S/z0nTI80iBxTr0p0v8AlADWEUYtBkyZ2JIex6cw3GsQ7WZiBRRCgj Y89BOT+/ct3cg8CLzQ45ooEDSk8alh/Bd4lj1i+utomyA6M+GckVHKcUsLt5Mg+T JwLf70g6Wb/HyX6Hsgq8obbRXdk7oGVqaCzbRwpYU++DPiFuG0YGJ9FZLBOdm9E9 Hb0vLLGmQhQvmxbOqzvQj2HozQQvEARRzhWO/2QeARDfNVnBRPsMfTM4G48B9tz6 Lz+3qn/j5034YEDfai5eSNWRYinP4/fPwK49L5mkVuHEomz7KrP9t8AdHHCxxgfd 7GPMntCRPFDQxKBYKk59wCmPYttteNmevtiorn/KJejdwDWmiO3X/x1Vl+KkxY3F VnPXjlrtcFqiVBrlyggviCGaEfSOzzgLRiNSHNDrHHFwQZJ2SHLuWxtPasY4MiZ9 TZz741J7UncrtTDT9HEPq3BJTg1n/inJ01JdHjLD1QtmEpMBL6bn8WzlwCOafr3Q 9K0NmdMXZNvVlkesHadP9zep19tb8WpAfRiqYVOWiMQElqF/rg4= =Q6Fw -----END PGP SIGNATURE----- Merge tag 'mtk-soc-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers MediaTek soc driver updates for v6.8 This adds a refactoring of the MediaTek Smart Voltage Scaling (SVS) driver and the addition of support for MT8186 and MT8195 in it, and adds support for the MT8188 VDOSYS and resets in the MMSYS driver. * tag 'mtk-soc-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (24 commits) soc: mediatek: mtk-svs: Constify runtime-immutable members of svs_bank soc: mediatek: mtk-svs: Use ULONG_MAX to compare floor frequency soc: mediatek: mtk-svs: Check if SVS mode is available in the beginning soc: mediatek: mtk-svs: Cleanup of svs_probe() function soc: mediatek: mtk-svs: Compress of_device_id entries soc: mediatek: mtk-svs: Remove redundant print in svs_get_efuse_data soc: mediatek: mtk-svs: Commonize MT8192 probe function for MT8186 soc: mediatek: mtk-svs: Drop supplementary svs per-bank pointer soc: mediatek: mtk-svs: Commonize efuse parse function for most SoCs soc: mediatek: mtk-svs: Move t-calibration-data retrieval to svs_probe() soc: mediatek: mtk-svs: Add SVS-Thermal coefficient to SoC platform data soc: mediatek: mtk-svs: Add a map to retrieve fused values soc: mediatek: mtk-svs: Change the thermal sensor device name soc: mediatek: mtk-svs: Reduce memory footprint of struct svs_bank soc: mediatek: mtk-svs: Build bank name string dynamically soc: mediatek: mtk-svs: Convert sw_id and type to enumerations soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflict soc: mediatek: Add MT8188 VDOSYS reset bit map soc: mediatek: Support reset bit mapping in mmsys driver soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys ... Link: https://lore.kernel.org/r/20231212114515.121695-2-angelogioacchino.delregno@collabora.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
e92c0b8b15
@ -3,6 +3,10 @@
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#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
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#define __SOC_MEDIATEK_MT8188_MMSYS_H
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include <dt-bindings/reset/mt8188-resets.h>
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#define MT8188_VDO0_SW0_RST_B 0x190
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#define MT8188_VDO0_OVL_MOUT_EN 0xf14
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#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
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#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
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@ -67,6 +71,136 @@
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#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18)
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#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19)
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#define MT8188_VDO1_SW0_RST_B 0x1d0
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#define MT8188_VDO1_HDR_TOP_CFG 0xd00
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#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30
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#define MT8188_VDO1_MIXER_IN1_PAD 0xd40
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#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c
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#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
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#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
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#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
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#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
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#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
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#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
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#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10
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#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
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#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
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#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
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#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18
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#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2)
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#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3)
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#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24
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#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
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#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28
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#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
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#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c
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#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
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#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30
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#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
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#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34
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#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
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#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
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#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
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#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
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#define MT8188_SOUT_TO_MIXER_IN1_SEL 1
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#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
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#define MT8188_SOUT_TO_MIXER_IN2_SEL 1
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#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
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#define MT8188_SOUT_TO_MIXER_IN3_SEL 1
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#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
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#define MT8188_SOUT_TO_MIXER_IN4_SEL 1
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#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
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#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
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#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58
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#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0
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#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
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#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0
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#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60
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#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0
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#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64
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#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0
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#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68
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#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
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static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
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[MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0),
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[MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2),
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[MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4),
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[MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6),
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[MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8),
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[MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10),
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[MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17),
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[MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19),
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[MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21),
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[MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22),
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[MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23),
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[MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24),
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[MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25),
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[MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26),
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[MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27),
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[MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28),
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[MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29),
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[MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30),
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[MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31),
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};
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static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
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[MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0),
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[MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1),
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[MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2),
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[MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3),
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[MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4),
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[MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5),
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[MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6),
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[MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7),
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[MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8),
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[MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9),
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[MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10),
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[MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11),
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[MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0),
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[MT8188_VDO1_RST_VPP_MERGE4] = MMSYS_RST_NR(1, 1),
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[MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 2),
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[MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 3),
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[MT8188_VDO1_RST_DISP_MUTEX] = MMSYS_RST_NR(1, 4),
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[MT8188_VDO1_RST_MDP_RDMA4] = MMSYS_RST_NR(1, 5),
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[MT8188_VDO1_RST_MDP_RDMA5] = MMSYS_RST_NR(1, 6),
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[MT8188_VDO1_RST_MDP_RDMA6] = MMSYS_RST_NR(1, 7),
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[MT8188_VDO1_RST_MDP_RDMA7] = MMSYS_RST_NR(1, 8),
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[MT8188_VDO1_RST_DP_INTF1_MMCK] = MMSYS_RST_NR(1, 9),
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[MT8188_VDO1_RST_DPI0_MM_CK] = MMSYS_RST_NR(1, 10),
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[MT8188_VDO1_RST_DPI1_MM_CK] = MMSYS_RST_NR(1, 11),
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[MT8188_VDO1_RST_MERGE0_DL_ASYNC] = MMSYS_RST_NR(1, 13),
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[MT8188_VDO1_RST_MERGE1_DL_ASYNC] = MMSYS_RST_NR(1, 14),
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[MT8188_VDO1_RST_MERGE2_DL_ASYNC] = MMSYS_RST_NR(1, 15),
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[MT8188_VDO1_RST_MERGE3_DL_ASYNC] = MMSYS_RST_NR(1, 16),
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[MT8188_VDO1_RST_MERGE4_DL_ASYNC] = MMSYS_RST_NR(1, 17),
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[MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 18),
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[MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 19),
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[MT8188_VDO1_RST_PADDING0] = MMSYS_RST_NR(1, 20),
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[MT8188_VDO1_RST_PADDING1] = MMSYS_RST_NR(1, 21),
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[MT8188_VDO1_RST_PADDING2] = MMSYS_RST_NR(1, 22),
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[MT8188_VDO1_RST_PADDING3] = MMSYS_RST_NR(1, 23),
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[MT8188_VDO1_RST_PADDING4] = MMSYS_RST_NR(1, 24),
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[MT8188_VDO1_RST_PADDING5] = MMSYS_RST_NR(1, 25),
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[MT8188_VDO1_RST_PADDING6] = MMSYS_RST_NR(1, 26),
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[MT8188_VDO1_RST_PADDING7] = MMSYS_RST_NR(1, 27),
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[MT8188_VDO1_RST_DISP_RSZ0] = MMSYS_RST_NR(1, 28),
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[MT8188_VDO1_RST_DISP_RSZ1] = MMSYS_RST_NR(1, 29),
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[MT8188_VDO1_RST_DISP_RSZ2] = MMSYS_RST_NR(1, 30),
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[MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31),
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[MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0),
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[MT8188_VDO1_RST_HDR_GFX_FE0] = MMSYS_RST_NR(2, 1),
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[MT8188_VDO1_RST_HDR_VDO_BE] = MMSYS_RST_NR(2, 2),
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[MT8188_VDO1_RST_HDR_VDO_FE1] = MMSYS_RST_NR(2, 16),
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[MT8188_VDO1_RST_HDR_GFX_FE1] = MMSYS_RST_NR(2, 17),
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[MT8188_VDO1_RST_DISP_MIXER] = MMSYS_RST_NR(2, 18),
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[MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 19),
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[MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 20),
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[MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 21),
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[MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 22),
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[MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
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};
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static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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@ -146,4 +280,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
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},
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};
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static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
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{
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DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
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MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
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}, {
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DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
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MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
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}, {
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DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
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MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
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}, {
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DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN1_SEL
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}, {
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DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN2_SEL
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}, {
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DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN3_SEL
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}, {
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DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN4_SEL
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}, {
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DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
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MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
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MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
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}, {
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DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
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}, {
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DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
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}, {
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DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
|
||||
MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
|
||||
MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
|
||||
MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
|
||||
MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
|
||||
}, {
|
||||
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
|
||||
MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
|
||||
MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
|
||||
MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
|
||||
MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
|
||||
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8188_MERGE4_SOUT_TO_DPI1_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
|
||||
MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
|
||||
MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
|
||||
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
|
||||
MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
|
||||
|
||||
@ -87,6 +87,29 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
|
||||
.clk_driver = "clk-mt8188-vdo0",
|
||||
.routes = mmsys_mt8188_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
|
||||
.sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
|
||||
.rst_tb = mmsys_mt8188_vdo0_rst_tb,
|
||||
.num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
|
||||
.clk_driver = "clk-mt8188-vdo1",
|
||||
.routes = mmsys_mt8188_vdo1_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
|
||||
.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
|
||||
.rst_tb = mmsys_mt8188_vdo1_rst_tb,
|
||||
.num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
|
||||
.vsync_len = 1,
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8188_vppsys0_driver_data = {
|
||||
.clk_driver = "clk-mt8188-vpp0",
|
||||
.is_vppsys = true,
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8188_vppsys1_driver_data = {
|
||||
.clk_driver = "clk-mt8188-vpp1",
|
||||
.is_vppsys = true,
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
|
||||
@ -169,6 +192,10 @@ void mtk_mmsys_ddp_connect(struct device *dev,
|
||||
if (cur == routes[i].from_comp && next == routes[i].to_comp)
|
||||
mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
|
||||
routes[i].val, NULL);
|
||||
|
||||
if (mmsys->data->vsync_len)
|
||||
mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0),
|
||||
mmsys->data->vsync_len, NULL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
|
||||
|
||||
@ -302,6 +329,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
|
||||
u32 offset;
|
||||
u32 reg;
|
||||
|
||||
if (mmsys->data->rst_tb) {
|
||||
if (id >= mmsys->data->num_resets) {
|
||||
dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
|
||||
id, mmsys->data->num_resets);
|
||||
return -EINVAL;
|
||||
}
|
||||
id = mmsys->data->rst_tb[id];
|
||||
}
|
||||
|
||||
offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
|
||||
id = id % MMSYS_SW_RESET_PER_REG;
|
||||
reg = mmsys->data->sw0_rst_offset + offset;
|
||||
@ -429,6 +465,9 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
|
||||
{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
|
||||
{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
|
||||
{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
|
||||
{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
|
||||
{ .compatible = "mediatek,mt8188-vppsys0", .data = &mt8188_vppsys0_driver_data },
|
||||
{ .compatible = "mediatek,mt8188-vppsys1", .data = &mt8188_vppsys1_driver_data },
|
||||
{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
|
||||
/* "mediatek,mt8195-mmsys" compatible is deprecated */
|
||||
{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
|
||||
|
||||
@ -78,6 +78,8 @@
|
||||
#define DSI_SEL_IN_RDMA 0x1
|
||||
#define DSI_SEL_IN_MASK 0x1
|
||||
|
||||
#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
|
||||
|
||||
struct mtk_mmsys_routes {
|
||||
u32 from_comp;
|
||||
u32 to_comp;
|
||||
@ -86,13 +88,43 @@ struct mtk_mmsys_routes {
|
||||
u32 val;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mtk_mmsys_driver_data - Settings of the mmsys
|
||||
* @clk_driver: Clock driver name that the mmsys is using
|
||||
* (defined in drivers/clk/mediatek/clk-*.c).
|
||||
* @routes: Routing table of the mmsys.
|
||||
* It provides mux settings from one module to another.
|
||||
* @num_routes: Array size of the routes.
|
||||
* @sw0_rst_offset: Register offset for the reset control.
|
||||
* @num_resets: Number of reset bits that are defined
|
||||
* @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
|
||||
* or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
|
||||
* @vsync_len: VSYNC length of the MIXER.
|
||||
* VSYNC is usually triggered by the connector, so its length is a
|
||||
* fixed value when the frame rate is decided, but ETHDR and
|
||||
* MIXER generate their own VSYNC due to hardware design, therefore
|
||||
* MIXER has to sync with ETHDR by adjusting VSYNC length.
|
||||
* On MT8195, there is no such setting so we use the gap between
|
||||
* falling edge and rising edge of SOF (Start of Frame) signal to
|
||||
* do the job, but since MT8188, VSYNC_LEN setting is introduced to
|
||||
* solve the problem and is given 0x40 (ticks) as the default value.
|
||||
* Please notice that this value has to be set to 1 (minimum) if
|
||||
* ETHDR is bypassed, otherwise MIXER could wait too long and causing
|
||||
* underflow.
|
||||
*
|
||||
* Each MMSYS (multi-media system) may have different settings, they may use
|
||||
* different clock sources, mux settings, reset control ...etc., and these
|
||||
* differences are all stored here.
|
||||
*/
|
||||
struct mtk_mmsys_driver_data {
|
||||
const char *clk_driver;
|
||||
const struct mtk_mmsys_routes *routes;
|
||||
const unsigned int num_routes;
|
||||
const u16 sw0_rst_offset;
|
||||
const u8 *rst_tb;
|
||||
const u32 num_resets;
|
||||
const bool is_vppsys;
|
||||
const u8 vsync_len;
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
@ -133,6 +133,30 @@
|
||||
#define MT8188_MUTEX_MOD_DISP_POSTMASK0 24
|
||||
#define MT8188_MUTEX_MOD2_DISP_PWM0 33
|
||||
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6
|
||||
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING0 8
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING1 9
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING2 10
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING3 11
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING4 12
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING5 13
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING6 14
|
||||
#define MT8188_MUTEX_MOD_DISP1_PADDING7 15
|
||||
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20
|
||||
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21
|
||||
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22
|
||||
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23
|
||||
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24
|
||||
#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30
|
||||
#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39
|
||||
|
||||
#define MT8195_MUTEX_MOD_DISP_OVL0 0
|
||||
#define MT8195_MUTEX_MOD_DISP_WDMA0 1
|
||||
#define MT8195_MUTEX_MOD_DISP_RDMA0 2
|
||||
@ -264,6 +288,7 @@
|
||||
#define MT8183_MUTEX_SOF_DPI0 2
|
||||
#define MT8188_MUTEX_SOF_DSI0 1
|
||||
#define MT8188_MUTEX_SOF_DP_INTF0 3
|
||||
#define MT8188_MUTEX_SOF_DP_INTF1 4
|
||||
#define MT8195_MUTEX_SOF_DSI0 1
|
||||
#define MT8195_MUTEX_SOF_DSI1 2
|
||||
#define MT8195_MUTEX_SOF_DP_INTF0 3
|
||||
@ -275,6 +300,7 @@
|
||||
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
|
||||
#define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
|
||||
#define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
|
||||
#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7)
|
||||
#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
|
||||
#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
|
||||
#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
|
||||
@ -445,6 +471,29 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
||||
[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
|
||||
[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
|
||||
[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
|
||||
[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
|
||||
[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
|
||||
[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
|
||||
[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
|
||||
[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
|
||||
[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
|
||||
[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
|
||||
[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
|
||||
[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
|
||||
[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
|
||||
[DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
|
||||
[DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
|
||||
[DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
|
||||
[DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
|
||||
[DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
|
||||
[DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
|
||||
[DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
|
||||
[DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
|
||||
[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
|
||||
[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
|
||||
[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
|
||||
[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
|
||||
[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
|
||||
};
|
||||
|
||||
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
||||
@ -605,6 +654,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
|
||||
MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
|
||||
[MUTEX_SOF_DP_INTF0] =
|
||||
MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
|
||||
[MUTEX_SOF_DP_INTF1] =
|
||||
MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
|
||||
};
|
||||
|
||||
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -62,6 +62,14 @@ enum mtk_ddp_comp_id {
|
||||
DDP_COMPONENT_OVL_2L1,
|
||||
DDP_COMPONENT_OVL_2L2,
|
||||
DDP_COMPONENT_OVL1,
|
||||
DDP_COMPONENT_PADDING0,
|
||||
DDP_COMPONENT_PADDING1,
|
||||
DDP_COMPONENT_PADDING2,
|
||||
DDP_COMPONENT_PADDING3,
|
||||
DDP_COMPONENT_PADDING4,
|
||||
DDP_COMPONENT_PADDING5,
|
||||
DDP_COMPONENT_PADDING6,
|
||||
DDP_COMPONENT_PADDING7,
|
||||
DDP_COMPONENT_POSTMASK0,
|
||||
DDP_COMPONENT_PWM0,
|
||||
DDP_COMPONENT_PWM1,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user