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mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase

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The clock-phase settings for the SDMMC controller in the SoCFPGA
platforms reside in a register in the System Manager. Add a method
to access that register through the syscon interface.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20221114230217.202634-4-dinguyen@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Dinh Nguyen 2022-11-14 17:02:15 -06:00 committed by Ulf Hansson
parent ccfa2466a4
commit ef87bd81cb
1 changed files with 40 additions and 1 deletions
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41
drivers/mmc/host/dw_mmc-pltfm.c
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@ -17,10 +17,16 @@
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/of.h>
#include <linux/mfd/altera-sysmgr.h>
#include <linux/regmap.h>
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \
((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
int dw_mci_pltfm_register(struct platform_device *pdev,
const struct dw_mci_drv_data *drv_data)
{
@ -62,9 +68,42 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = {
};
EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
static int dw_mci_socfpga_priv_init(struct dw_mci *host)
{
struct device_node *np = host->dev->of_node;
struct regmap *sys_mgr_base_addr;
u32 clk_phase[2] = {0}, reg_offset, reg_shift;
int i, rc, hs_timing;
rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
if (rc < 0)
return 0;
sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
if (IS_ERR(sys_mgr_base_addr)) {
dev_warn(host->dev, "clk-phase-sd-hs was specified, but failed to find altr,sys-mgr regmap!\n");
return 0;
}
of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
for (i = 0; i < ARRAY_SIZE(clk_phase); i++)
clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP;
hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift);
regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);
return 0;
}
static const struct dw_mci_drv_data socfpga_drv_data = {
.init = dw_mci_socfpga_priv_init,
};
static const struct of_device_id dw_mci_pltfm_match[] = {
{ .compatible = "snps,dw-mshc", },
{ .compatible = "altr,socfpga-dw-mshc", },
{ .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, },
{ .compatible = "img,pistachio-dw-mshc", },
{},
};