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Qualcomm Arm64 DeviceTree changes for v6.13

Browse Source 
Introduce descriptions of the 8cx Gen3-based Microsoft Surface Pro 9 5G,
 X Elite based Dell XPS 13 9345, the QCS9100 platform and the "Ride"
 development boards thereon, and the SM7325 platform and the Nothing
 Phone 1.
 
 MSM8998 gains support for HDMI. The Lenovo Miix 630 gains support for
 volume keys, audio and sensor DSPs, touchscreen, and its specific WiFi
 calibration variant.
 
 On QCM6490, Fairphone FP5 gains a thermistor adjacent to UFS/RAM, while
 the IDP gains UFS and WiFi support. For QCS6490 changes to Rb3Gen2
 enables WiFi, Venus, PCIe, SD-card, and volume keys. Adreno speedbins
 are adjusted and PMU nodes' compatibles for the two clusters are
 corrected.
 
 The DB845C/RB3 and QRB5165 RB5 vision mezzanines are converted to
 DeviceTree overlays, and both gains CMA heap for libcamera to use.
 
 SA8775P gains GPI DMA support, support for controlling download mode
 (bootloader-assisted ramdump support), additional UARTs, and qcrypto
 support. The "Ride" development board gains WiFi and Bluetooth support.
 
 On SC8280XP (8cx Gen3) another UART is described, used in the
 Microsoft Surface 9 5G. The WiFi/BT combo chip's power management unit
 is described on the CRD and Lenovo ThinkPad X13s.
 
 On SDM630/660 the GPU SMMU and clock controller is added, as is the
 A2Noc and LPASS SMMU, and the DSP-based WiFi device. GPU, modem DSP and
 WiFi is then enabled on the Inforce 6560 development board.
 
 On SM8450 Hardware Development Kit, the WCN6855 is modelled to enable
 WiFi and Bluetooth. A "global" interrupt is defined on SM8450 PCIe RC
 controller, to enable hotplug.
 
 On X Elite, USB Type-C controllers are marked as usb-role-switch
 capable, the GICv3 ITS is enabled for PCIe. TCSR region is described and
 wired up to allow setting and cleaning the download mode
 (bootloader-assisted ramdump) flag, and residency numbers for C4/C5 are
 updated.
 
 USB role switch is enabled on Lenovo ThinkPad T14s and the ASUS Vivobook
 S15. The T14s also gains support for a second source trackpad. The
 Microsoft Surface Laptop gains LID switch and the USB Type-A connector
 attached to the multiport controller is enabled. The CRD has its HID
 device power supplies described.
 
 Application SMMU is flagged as DMA coherent across QDU1000, SC7180,
 SC8180X, SC8280XP, SDM670, SDM845, SM8150, SM8350, SM8450, and X1E80100.
 
 In addition to this, the effort to improve style and binding compliance
 continued.
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Merge tag 'qcom-arm64-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree changes for v6.13

Introduce descriptions of the 8cx Gen3-based Microsoft Surface Pro 9 5G,
X Elite based Dell XPS 13 9345, the QCS9100 platform and the "Ride"
development boards thereon, and the SM7325 platform and the Nothing
Phone 1.

MSM8998 gains support for HDMI. The Lenovo Miix 630 gains support for
volume keys, audio and sensor DSPs, touchscreen, and its specific WiFi
calibration variant.

On QCM6490, Fairphone FP5 gains a thermistor adjacent to UFS/RAM, while
the IDP gains UFS and WiFi support. For QCS6490 changes to Rb3Gen2
enables WiFi, Venus, PCIe, SD-card, and volume keys. Adreno speedbins
are adjusted and PMU nodes' compatibles for the two clusters are
corrected.

The DB845C/RB3 and QRB5165 RB5 vision mezzanines are converted to
DeviceTree overlays, and both gains CMA heap for libcamera to use.

SA8775P gains GPI DMA support, support for controlling download mode
(bootloader-assisted ramdump support), additional UARTs, and qcrypto
support. The "Ride" development board gains WiFi and Bluetooth support.

On SC8280XP (8cx Gen3) another UART is described, used in the
Microsoft Surface 9 5G. The WiFi/BT combo chip's power management unit
is described on the CRD and Lenovo ThinkPad X13s.

On SDM630/660 the GPU SMMU and clock controller is added, as is the
A2Noc and LPASS SMMU, and the DSP-based WiFi device. GPU, modem DSP and
WiFi is then enabled on the Inforce 6560 development board.

On SM8450 Hardware Development Kit, the WCN6855 is modelled to enable
WiFi and Bluetooth. A "global" interrupt is defined on SM8450 PCIe RC
controller, to enable hotplug.

On X Elite, USB Type-C controllers are marked as usb-role-switch
capable, the GICv3 ITS is enabled for PCIe. TCSR region is described and
wired up to allow setting and cleaning the download mode
(bootloader-assisted ramdump) flag, and residency numbers for C4/C5 are
updated.

USB role switch is enabled on Lenovo ThinkPad T14s and the ASUS Vivobook
S15. The T14s also gains support for a second source trackpad. The
Microsoft Surface Laptop gains LID switch and the USB Type-A connector
attached to the multiport controller is enabled. The CRD has its HID
device power supplies described.

Application SMMU is flagged as DMA coherent across QDU1000, SC7180,
SC8180X, SC8280XP, SDM670, SDM845, SM8150, SM8350, SM8450, and X1E80100.

In addition to this, the effort to improve style and binding compliance
continued.

* tag 'qcom-arm64-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (120 commits)
  arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add cma heap for libcamera softisp support
  arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add cma heap for libcamera softisp support
  arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Drop redundant clock-lanes from camera@1a
  arm64: dts: qcom: sc8280xp-x13s: Drop redundant clock-lanes from camera@10
  arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso
  arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Convert mezzanine riser to dtbo
  arm64: dts: qcom: sm8450-hdk: model the PMU of the on-board wcn6855
  arm64: dts: qcom: sc8280xp-x13s: model the PMU of the on-board wcn6855
  arm64: dts: qcom: sc8280xp-crd: enable bluetooth
  arm64: dts: qcom: sc8280xp-crd: model the PMU of the on-board wcn6855
  arm64: dts: qcom: qcs9100: Add support for the QCS9100 Ride and Ride Rev3 boards
  dt-bindings: arm: qcom: Document qcs9100-ride and qcs9100-ride Rev3
  arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers
  arm64: dts: qcom: x1e80100-crd: describe HID supplies
  arm64: dts: qcom: msm8998-lenovo-miix-630: add WiFi calibration variant
  arm64: dts: qcom: msm8998-clamshell: enable resin/VolDown
  arm64: dts: qcom: msm8998-lenovo-miix-630: enable VolumeUp button
  arm64: dts: qcom: msm8998-lenovo-miix-630: enable aDSP and SLPI
  arm64: dts: qcom: msm8998-lenovo-miix-630: enable touchscreen
  arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes
  ...

Link: https://lore.kernel.org/r/20241105164901.7787-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-11-12 22:45:36 +01:00
commit f50f6052c3
98 changed files with 8315 additions and 2947 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -202,6 +202,7 @@ properties:
- qcom,kryo560
- qcom,kryo570
- qcom,kryo660
- qcom,kryo670
- qcom,kryo685
- qcom,kryo780
- qcom,oryon

16
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -45,6 +45,7 @@ description: |
qcs8550
qcm2290
qcm6490
qcs9100
qdu1000
qrb2210
qrb4210
@ -76,6 +77,7 @@ description: |
sm6375
sm7125
sm7225
sm7325
sm8150
sm8250
sm8350
@ -821,6 +823,7 @@ properties:
- items:
- enum:
- lenovo,thinkpad-x13s
- microsoft,arcata
- qcom,sc8280xp-crd
- qcom,sc8280xp-qrd
- const: qcom,sc8280xp
@ -912,6 +915,13 @@ properties:
- qcom,sa8775p-ride-r3
- const: qcom,sa8775p
- items:
- enum:
- qcom,qcs9100-ride
- qcom,qcs9100-ride-r3
- const: qcom,qcs9100
- const: qcom,sa8775p
- items:
- enum:
- google,cheza
@ -989,6 +999,11 @@ properties:
- fairphone,fp4
- const: qcom,sm7225
- items:
- enum:
- nothing,spacewar
- const: qcom,sm7325
- items:
- enum:
- microsoft,surface-duo
@ -1058,6 +1073,7 @@ properties:
- items:
- enum:
- asus,vivobook-s15
- dell,xps13-9345
- lenovo,yoga-slim7x
- microsoft,romulus13
- microsoft,romulus15

62
Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml Normal file
View File

@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SA8775P
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SA8775p.
See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
properties:
compatible:
enum:
- qcom,sa8775p-camcc
clocks:
items:
- description: Camera AHB clock from GCC
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
power-domains:
maxItems: 1
description: MMCX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
clock-controller@ade0000 {
compatible = "qcom,sa8775p-camcc";
reg = <0x0ade0000 0x20000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

79
Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml Normal file
View File

@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SA8775P
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SA8775P.
See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
properties:
compatible:
enum:
- qcom,sa8775p-dispcc0
- qcom,sa8775p-dispcc1
clocks:
items:
- description: GCC AHB clock source
- description: Board XO source
- description: Board XO_AO source
- description: Sleep clock source
- description: Link clock from DP0 PHY
- description: VCO DIV clock from DP0 PHY
- description: Link clock from DP1 PHY
- description: VCO DIV clock from DP1 PHY
- description: Byte clock from DSI0 PHY
- description: Pixel clock from DSI0 PHY
- description: Byte clock from DSI1 PHY
- description: Pixel clock from DSI1 PHY
power-domains:
maxItems: 1
description: MMCX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
clock-controller@af00000 {
compatible = "qcom,sa8775p-dispcc0";
reg = <0x0af00000 0x20000>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&dp_phy0 0>,
<&dp_phy0 1>,
<&dp_phy1 2>,
<&dp_phy1 3>,
<&dsi_phy0 0>,
<&dsi_phy0 1>,
<&dsi_phy1 2>,
<&dsi_phy1 3>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

62
Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml Normal file
View File

@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on SA8775P
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SA8775P.
See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h
properties:
compatible:
enum:
- qcom,sa8775p-videocc
clocks:
items:
- description: Video AHB clock from GCC
- description: Board XO source
- description: Board active XO source
- description: Sleep Clock source
power-domains:
maxItems: 1
description: MMCX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
videocc: clock-controller@abf0000 {
compatible = "qcom,sa8775p-videocc";
reg = <0x0abf0000 0x10000>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -1047,6 +1047,8 @@ patternProperties:
description: Nokia
"^nordic,.*":
description: Nordic Semiconductor
"^nothing,.*":
description: Nothing Technology Limited
"^novatek,.*":
description: Novatek
"^novtech,.*":

2
arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi
View File

@ -25,7 +25,7 @@ psci {
};
};
&CPU_SLEEP_0 {
&cpu_sleep_0 {
compatible = "qcom,idle-state-spc", "arm,idle-state";
};

11
arch/arm64/boot/dts/qcom/Makefile
View File

@ -112,10 +112,15 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
qrb5165-rb5-vision-mezzanine-dtbs := qrb5165-rb5.dtb qrb5165-rb5-vision-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
@ -191,6 +196,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb
dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb
@ -207,6 +213,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
@ -235,6 +244,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
@ -271,6 +281,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb

10
arch/arm64/boot/dts/qcom/ipq5018.dtsi
View File

@ -31,27 +31,27 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;

18
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -31,47 +31,47 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;

26
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -34,12 +34,12 @@ cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -47,12 +47,12 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -60,12 +60,12 @@ CPU1: cpu@1 {
#cooling-cells = <2>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -73,12 +73,12 @@ CPU2: cpu@2 {
#cooling-cells = <2>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -86,7 +86,7 @@ CPU3: cpu@3 {
#cooling-cells = <2>;
};
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@ -1015,10 +1015,10 @@ cpu_alert: cpu-passive {
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

18
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -32,39 +32,39 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
enable-method = "psci";
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;

52
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -34,12 +34,12 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -47,12 +47,12 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -60,12 +60,12 @@ CPU1: cpu@1 {
#cooling-cells = <2>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -73,12 +73,12 @@ CPU2: cpu@2 {
#cooling-cells = <2>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@ -86,7 +86,7 @@ CPU3: cpu@3 {
#cooling-cells = <2>;
};
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@ -234,7 +234,7 @@ rng: rng@e3000 {
};
mdio: mdio@90000 {
compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
reg = <0x00090000 0x64>;
#address-cells = <1>;
#size-cells = <0>;
@ -863,10 +863,10 @@ cpu0_alert: cpu-passive {
cooling-maps {
map0 {
trip = <&cpu0_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -891,10 +891,10 @@ cpu1_alert: cpu-passive {
cooling-maps {
map0 {
trip = <&cpu1_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -919,10 +919,10 @@ cpu2_alert: cpu-passive {
cooling-maps {
map0 {
trip = <&cpu2_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -947,10 +947,10 @@ cpu3_alert: cpu-passive {
cooling-maps {
map0 {
trip = <&cpu3_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

2
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt86518.dts
View File

@ -57,7 +57,7 @@ &sound {
widgets = "Speaker", "Speaker",
"Headphone", "Headphones";
pin-switches = "Speaker", "Headphones";
audio-routing = "Speaker", "Speaker Amp OUT",
audio-routing = "Speaker", "Speaker Amp OUT",
"Speaker Amp IN", "HPH_R",
"Headphones", "Headphones Switch OUTL",
"Headphones", "Headphones Switch OUTR",

100
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -133,67 +133,67 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,acc = <&cpu0_acc>;
qcom,saw = <&cpu0_saw>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,acc = <&cpu1_acc>;
qcom,saw = <&cpu1_saw>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,acc = <&cpu2_acc>;
qcom,saw = <&cpu2_saw>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,acc = <&cpu3_acc>;
qcom,saw = <&cpu3_saw>;
};
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@ -202,7 +202,7 @@ L2_0: l2-cache {
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x40000002>;
@ -215,7 +215,7 @@ CPU_SLEEP_0: cpu-sleep-0 {
domain-idle-states {
CLUSTER_RET: cluster-retention {
cluster_ret: cluster-retention {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000012>;
entry-latency-us = <500>;
@ -223,7 +223,7 @@ CLUSTER_RET: cluster-retention {
min-residency-us = <2000>;
};
CLUSTER_PWRDN: cluster-gdhs {
cluster_pwrdn: cluster-gdhs {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000032>;
entry-latency-us = <2000>;
@ -273,33 +273,33 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>;
};
};
@ -823,7 +823,7 @@ debug0: debug@850000 {
reg = <0x00850000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
cpu = <&cpu0>;
status = "disabled";
};
@ -832,7 +832,7 @@ debug1: debug@852000 {
reg = <0x00852000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
cpu = <&cpu1>;
status = "disabled";
};
@ -841,7 +841,7 @@ debug2: debug@854000 {
reg = <0x00854000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
cpu = <&cpu2>;
status = "disabled";
};
@ -850,7 +850,7 @@ debug3: debug@856000 {
reg = <0x00856000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
cpu = <&cpu3>;
status = "disabled";
};
@ -864,7 +864,7 @@ cti12: cti@858000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
cpu = <&cpu0>;
arm,cs-dev-assoc = <&etm0>;
status = "disabled";
@ -879,7 +879,7 @@ cti13: cti@859000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
cpu = <&cpu1>;
arm,cs-dev-assoc = <&etm1>;
status = "disabled";
@ -894,7 +894,7 @@ cti14: cti@85a000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
cpu = <&cpu2>;
arm,cs-dev-assoc = <&etm2>;
status = "disabled";
@ -909,7 +909,7 @@ cti15: cti@85b000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
cpu = <&cpu3>;
arm,cs-dev-assoc = <&etm3>;
status = "disabled";
@ -923,7 +923,7 @@ etm0: etm@85c000 {
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU0>;
cpu = <&cpu0>;
status = "disabled";
@ -944,7 +944,7 @@ etm1: etm@85d000 {
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU1>;
cpu = <&cpu1>;
status = "disabled";
@ -965,7 +965,7 @@ etm2: etm@85e000 {
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU2>;
cpu = <&cpu2>;
status = "disabled";
@ -986,7 +986,7 @@ etm3: etm@85f000 {
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU3>;
cpu = <&cpu3>;
status = "disabled";
@ -2644,10 +2644,10 @@ cpu0_1_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu0_1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2673,10 +2673,10 @@ cpu2_3_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu2_3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

110
arch/arm64/boot/dts/qcom/msm8939.dtsi
View File

@ -42,122 +42,122 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@100 {
cpu0: cpu@100 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x100>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
L2_1: l2-cache {
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@101 {
cpu1: cpu@101 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x101>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
};
CPU2: cpu@102 {
cpu2: cpu@102 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x102>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
};
CPU3: cpu@103 {
cpu3: cpu@103 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x103>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
};
CPU4: cpu@0 {
cpu4: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x0>;
qcom,acc = <&acc4>;
qcom,saw = <&saw4>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU5: cpu@1 {
cpu5: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x1>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,acc = <&acc5>;
qcom,saw = <&saw5>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
};
CPU6: cpu@2 {
cpu6: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,acc = <&acc6>;
qcom,saw = <&saw6>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
};
CPU7: cpu@3 {
cpu7: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x3>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,acc = <&acc7>;
qcom,saw = <&saw7>;
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
};
idle-states {
CPU_SLEEP_0: cpu-sleep-0 {
cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
entry-latency-us = <130>;
exit-latency-us = <150>;
@ -182,19 +182,19 @@ cpu-map {
/* LITTLE (efficiency) cluster */
cluster0 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
@ -202,19 +202,19 @@ core3 {
/* Boot CPU is cluster 1 core 0 */
cluster1 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
};
@ -2318,10 +2318,10 @@ cpu0_crit: trip1 {
cooling-maps {
map0 {
trip = <&cpu0_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2348,10 +2348,10 @@ cpu1_crit: trip1 {
cooling-maps {
map0 {
trip = <&cpu1_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2378,10 +2378,10 @@ cpu2_crit: trip1 {
cooling-maps {
map0 {
trip = <&cpu2_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2408,10 +2408,10 @@ cpu3_crit: trip1 {
cooling-maps {
map0 {
trip = <&cpu3_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2438,10 +2438,10 @@ cpu4567_crit: trip1 {
cooling-maps {
map0 {
trip = <&cpu4567_alert>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

68
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -38,125 +38,125 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU4: cpu@100 {
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
CPU5: cpu@101 {
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
CPU6: cpu@102 {
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
CPU7: cpu@103 {
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
L2_0: l2-cache-0 {
l2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
L2_1: l2-cache-1 {
l2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
@ -1985,7 +1985,7 @@ cpu0_crit: crit {
cooling-maps {
map0 {
trip = <&cpu0_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2009,7 +2009,7 @@ cpu1_crit: crit {
cooling-maps {
map0 {
trip = <&cpu1_alert>;
cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2033,7 +2033,7 @@ cpu2_crit: crit {
cooling-maps {
map0 {
trip = <&cpu2_alert>;
cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2057,7 +2057,7 @@ cpu3_crit: crit {
cooling-maps {
map0 {
trip = <&cpu3_alert>;
cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2079,7 +2079,7 @@ cpu4_crit: crit {
cooling-maps {
map0 {
trip = <&cpu4_alert>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2101,7 +2101,7 @@ cpu5_crit: crit {
cooling-maps {
map0 {
trip = <&cpu5_alert>;
cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2123,7 +2123,7 @@ cpu6_crit: crit {
cooling-maps {
map0 {
trip = <&cpu6_alert>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2145,7 +2145,7 @@ cpu7_crit: crit {
cooling-maps {
map0 {
trip = <&cpu7_alert>;
cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

34
arch/arm64/boot/dts/qcom/msm8976.dtsi
View File

@ -31,7 +31,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@ -42,7 +42,7 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
@ -53,7 +53,7 @@ CPU1: cpu@1 {
#cooling-cells = <2>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
@ -64,7 +64,7 @@ CPU2: cpu@2 {
#cooling-cells = <2>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
@ -75,7 +75,7 @@ CPU3: cpu@3 {
#cooling-cells = <2>;
};
CPU4: cpu@100 {
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
@ -86,7 +86,7 @@ CPU4: cpu@100 {
#cooling-cells = <2>;
};
CPU5: cpu@101 {
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x101>;
@ -97,7 +97,7 @@ CPU5: cpu@101 {
#cooling-cells = <2>;
};
CPU6: cpu@102 {
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x102>;
@ -108,7 +108,7 @@ CPU6: cpu@102 {
#cooling-cells = <2>;
};
CPU7: cpu@103 {
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x103>;
@ -122,37 +122,37 @@ CPU7: cpu@103 {
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -1193,7 +1193,7 @@ opp-600000000 {
apps_iommu: iommu@1ee0000 {
compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
reg = <0x01ee0000 0x3000>;
ranges = <0 0x01e20000 0x20000>;
ranges = <0 0x01e20000 0x20000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;

12
arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts
View File

@ -91,27 +91,27 @@ key-vol-up {
};
};
&CPU0 {
&cpu0 {
enable-method = "spin-table";
};
&CPU1 {
&cpu1 {
enable-method = "spin-table";
};
&CPU2 {
&cpu2 {
enable-method = "spin-table";
};
&CPU3 {
&cpu3 {
enable-method = "spin-table";
};
&CPU4 {
&cpu4 {
enable-method = "spin-table";
};
&CPU5 {
&cpu5 {
enable-method = "spin-table";
};

4
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View File

@ -175,7 +175,7 @@ &blsp2_uart2 {
};
&pm8994_spmi_regulators {
VDD_APC0: s8 {
s8 {
regulator-min-microvolt = <680000>;
regulator-max-microvolt = <1180000>;
regulator-always-on;
@ -183,7 +183,7 @@ VDD_APC0: s8 {
};
/* APC1 is 3-phase, but quoting downstream, s11 is "the gang leader" */
VDD_APC1: s11 {
s11 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1225000>;
regulator-always-on;

4
arch/arm64/boot/dts/qcom/msm8992.dtsi
View File

@ -6,8 +6,8 @@
#include "msm8994.dtsi"
/* 8992 only features 2 A57 cores. */
/delete-node/ &CPU6;
/delete-node/ &CPU7;
/delete-node/ &cpu6;
/delete-node/ &cpu7;
/delete-node/ &cpu6_map;
/delete-node/ &cpu7_map;

52
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -43,114 +43,114 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU4: cpu@100 {
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&l2_1>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU5: cpu@101 {
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
CPU6: cpu@102 {
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
CPU7: cpu@103 {
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
cpu6_map: core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
cpu7_map: core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};

54
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -43,90 +43,90 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU2: cpu@100 {
cpu2: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&l2_1>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU3: cpu@101 {
cpu3: cpu@101 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
};
cluster1 {
core0 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core1 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
};
@ -134,7 +134,7 @@ core1 {
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x00000004>;
@ -2829,7 +2829,7 @@ debug@3810000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
cpu = <&cpu0>;
};
etm@3840000 {
@ -2839,7 +2839,7 @@ etm@3840000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU0>;
cpu = <&cpu0>;
out-ports {
port {
@ -2858,7 +2858,7 @@ debug@3910000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
cpu = <&cpu1>;
};
etm@3940000 {
@ -2868,7 +2868,7 @@ etm@3940000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU1>;
cpu = <&cpu1>;
out-ports {
port {
@ -2923,7 +2923,7 @@ debug@3a10000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
cpu = <&cpu2>;
};
etm@3a40000 {
@ -2933,7 +2933,7 @@ etm@3a40000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU2>;
cpu = <&cpu2>;
out-ports {
port {
@ -2952,7 +2952,7 @@ debug@3b10000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
cpu = <&cpu3>;
};
etm@3b40000 {
@ -2962,7 +2962,7 @@ etm@3b40000 {
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU3>;
cpu = <&cpu3>;
out-ports {
port {

38
arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
View File

@ -61,36 +61,36 @@ cts-pins {
* not advertised as enabled in ACPI, and enabling it in DT can cause boot
* hangs.
*/
&CPU0 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
&cpu0 {
cpu-idle-states = <&little_cpu_sleep_1>;
};
&CPU1 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
&cpu1 {
cpu-idle-states = <&little_cpu_sleep_1>;
};
&CPU2 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
&cpu2 {
cpu-idle-states = <&little_cpu_sleep_1>;
};
&CPU3 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_1>;
&cpu3 {
cpu-idle-states = <&little_cpu_sleep_1>;
};
&CPU4 {
cpu-idle-states = <&BIG_CPU_SLEEP_1>;
&cpu4 {
cpu-idle-states = <&big_cpu_sleep_1>;
};
&CPU5 {
cpu-idle-states = <&BIG_CPU_SLEEP_1>;
&cpu5 {
cpu-idle-states = <&big_cpu_sleep_1>;
};
&CPU6 {
cpu-idle-states = <&BIG_CPU_SLEEP_1>;
&cpu6 {
cpu-idle-states = <&big_cpu_sleep_1>;
};
&CPU7 {
cpu-idle-states = <&BIG_CPU_SLEEP_1>;
&cpu7 {
cpu-idle-states = <&big_cpu_sleep_1>;
};
/*
@ -128,6 +128,12 @@ pm8005_s1: s1 { /* VDD_GFX supply */
};
};
&pm8998_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&qusb2phy {
status = "okay";

68
arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts
View File

@ -3,12 +3,45 @@
/dts-v1/;
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "msm8998-clamshell.dtsi"
/ {
model = "Lenovo Miix 630";
compatible = "lenovo,miix-630", "qcom,msm8998";
chassis-type = "convertible";
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-0 = <&vol_up_pin_a>;
pinctrl-names = "default";
key-vol-up {
label = "Volume Up";
gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&blsp1_i2c5 {
clock-frequency = <400000>;
status = "okay";
touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&i2c5_hid_active>;
pinctrl-names = "default";
};
};
&blsp1_i2c6 {
@ -27,11 +60,46 @@ keyboard@3a {
};
};
&pm8998_gpios {
vol_up_pin_a: vol-up-active-state {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
};
&remoteproc_adsp {
firmware-name = "qcom/msm8998/LENOVO/81F1/qcadsp8998.mbn";
status = "okay";
};
&remoteproc_mss {
firmware-name = "qcom/msm8998/LENOVO/81F1/qcdsp1v28998.mbn",
"qcom/msm8998/LENOVO/81F1/qcdsp28998.mbn";
};
&remoteproc_slpi {
firmware-name = "qcom/msm8998/LENOVO/81F1/qcslpi8998.mbn";
status = "okay";
};
&sdhc2 {
cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
};
&tlmm {
i2c5_hid_active: i2c5-hid-active-state {
pins = "gpio125";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
&wifi {
qcom,ath10k-calibration-variant = "Lenovo_Miix630";
};

220
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -136,130 +136,130 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
next-level-cache = <&l2_0>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
next-level-cache = <&l2_0>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x3>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
next-level-cache = <&l2_0>;
};
CPU4: cpu@100 {
cpu4: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
next-level-cache = <&l2_1>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU5: cpu@101 {
cpu5: cpu@101 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
next-level-cache = <&l2_1>;
};
CPU6: cpu@102 {
cpu6: cpu@102 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
next-level-cache = <&l2_1>;
};
CPU7: cpu@103 {
cpu7: cpu@103 {
device_type = "cpu";
compatible = "qcom,kryo280";
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
next-level-cache = <&l2_1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -267,7 +267,7 @@ core3 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-retention";
/* CPU Retention (C2D), L2 Active */
@ -277,7 +277,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
min-residency-us = <504>;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-power-collapse";
/* CPU + L2 Power Collapse (C3, D4) */
@ -288,7 +288,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-retention";
/* CPU Retention (C2D), L2 Active */
@ -298,7 +298,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
min-residency-us = <1302>;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-power-collapse";
/* CPU + L2 Power Collapse (C3, D4) */
@ -1415,6 +1415,34 @@ blsp2_spi6_default: blsp2-spi6-default-state {
drive-strength = <6>;
bias-disable;
};
hdmi_cec_default: hdmi-cec-default-state {
pins = "gpio31";
function = "hdmi_cec";
drive-strength = <2>;
bias-pull-up;
};
hdmi_ddc_default: hdmi-ddc-default-state {
pins = "gpio32", "gpio33";
function = "hdmi_ddc";
drive-strength = <2>;
bias-pull-up;
};
hdmi_hpd_default: hdmi-hpd-default-state {
pins = "gpio34";
function = "hdmi_hot";
drive-strength = <16>;
bias-pull-down;
};
hdmi_hpd_sleep: hdmi-hpd-sleep-state {
pins = "gpio34";
function = "hdmi_hot";
drive-strength = <2>;
bias-pull-down;
};
};
remoteproc_mss: remoteproc@4080000 {
@ -1846,7 +1874,7 @@ etm1: etm@7840000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU0>;
cpu = <&cpu0>;
out-ports {
port {
@ -1866,7 +1894,7 @@ etm2: etm@7940000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU1>;
cpu = <&cpu1>;
out-ports {
port {
@ -1886,7 +1914,7 @@ etm3: etm@7a40000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU2>;
cpu = <&cpu2>;
out-ports {
port {
@ -1906,7 +1934,7 @@ etm4: etm@7b40000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU3>;
cpu = <&cpu3>;
out-ports {
port {
@ -2040,7 +2068,7 @@ etm5: etm@7c40000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU4>;
cpu = <&cpu4>;
out-ports {
port {
@ -2059,7 +2087,7 @@ etm6: etm@7d40000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU5>;
cpu = <&cpu5>;
out-ports {
port {
@ -2078,7 +2106,7 @@ etm7: etm@7e40000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU6>;
cpu = <&cpu6>;
out-ports {
port {
@ -2097,7 +2125,7 @@ etm8: etm@7f40000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU7>;
cpu = <&cpu7>;
out-ports {
port {
@ -2766,7 +2794,7 @@ mmcc: clock-controller@c8c0000 {
<&mdss_dsi0_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_dsi1_phy 0>,
<0>,
<&mdss_hdmi_phy 0>,
<0>,
<0>,
<&gcc GCC_MMSS_GPLL0_DIV_CLK>;
@ -2871,6 +2899,14 @@ dpu_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
port@2 {
reg = <2>;
dpu_intf3_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
@ -3026,6 +3062,96 @@ mdss_dsi1_phy: phy@c996400 {
status = "disabled";
};
mdss_hdmi: hdmi-tx@c9a0000 {
compatible = "qcom,hdmi-tx-8998";
reg = <0x0c9a0000 0x50c>,
<0x00780000 0x6220>,
<0x0c9e0000 0x2c>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
interrupt-parent = <&mdss>;
interrupts = <8>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_HDMI_CLK>,
<&mmcc MDSS_HDMI_DP_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MNOC_AHB_CLK>,
<&mmcc MISC_AHB_CLK>;
clock-names =
"mdp_core",
"iface",
"core",
"alt_iface",
"extp",
"bus",
"mnoc",
"iface_mmss";
phys = <&mdss_hdmi_phy>;
#sound-dai-cells = <1>;
pinctrl-0 = <&hdmi_hpd_default>,
<&hdmi_ddc_default>,
<&hdmi_cec_default>;
pinctrl-1 = <&hdmi_hpd_sleep>,
<&hdmi_ddc_default>,
<&hdmi_cec_default>;
pinctrl-names = "default", "sleep";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&dpu_intf3_out>;
};
};
port@1 {
reg = <1>;
hdmi_out: endpoint {
};
};
};
};
mdss_hdmi_phy: hdmi-phy@c9a0600 {
compatible = "qcom,hdmi-phy-8998";
reg = <0x0c9a0600 0x18b>,
<0x0c9a0a00 0x38>,
<0x0c9a0c00 0x38>,
<0x0c9a0e00 0x38>,
<0x0c9a1000 0x38>,
<0x0c9a1200 0x0e8>;
reg-names = "hdmi_pll",
"hdmi_tx_l0",
"hdmi_tx_l1",
"hdmi_tx_l2",
"hdmi_tx_l3",
"hdmi_phy";
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&gcc GCC_HDMI_CLKREF_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface",
"ref",
"xo";
status = "disabled";
};
};
venus: video-codec@cc00000 {

68
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View File

@ -42,7 +42,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
@ -50,18 +50,18 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
@ -69,13 +69,13 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
@ -83,13 +83,13 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
@ -97,34 +97,34 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
};
domain-idle-states {
CLUSTER_SLEEP: cluster-sleep-0 {
cluster_sleep: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000043>;
entry-latency-us = <800>;
@ -136,7 +136,7 @@ CLUSTER_SLEEP: cluster-sleep-0 {
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep-0 {
cpu_sleep: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -174,34 +174,34 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_sleep>;
};
CLUSTER_PD: power-domain-cpu-cluster {
cluster_pd: power-domain-cpu-cluster {
#power-domain-cells = <0>;
power-domains = <&mpm>;
domain-idle-states = <&CLUSTER_SLEEP>;
domain-idle-states = <&cluster_sleep>;
};
};
@ -2067,7 +2067,7 @@ lmh_cluster: lmh@f550800 {
compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh";
reg = <0x0 0x0f550800 0x0 0x400>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU0>;
cpus = <&cpu0>;
qcom,lmh-temp-arm-millicelsius = <65000>;
qcom,lmh-temp-low-millicelsius = <94500>;
qcom,lmh-temp-high-millicelsius = <95000>;

40
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -207,6 +207,20 @@ active-config0 {
};
};
mem-thermal {
polling-delay-passive = <0>;
thermal-sensors = <&pm7250b_adc_tm 2>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pm8008-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pm8008>;
@ -679,6 +693,9 @@ &ipa {
};
&pm7250b_adc {
pinctrl-0 = <&pm7250b_adc_default>;
pinctrl-names = "default";
channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
@ -694,6 +711,14 @@ channel@4f {
qcom,pre-scaling = <1 1>;
label = "conn_therm";
};
channel@53 {
reg = <ADC5_GPIO2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "mem_therm";
};
};
&pm7250b_adc_tm {
@ -712,6 +737,21 @@ conn-therm@1 {
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
mem-therm@2 {
reg = <2>;
io-channels = <&pm7250b_adc ADC5_GPIO2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm7250b_gpios {
pm7250b_adc_default: adc-default-state {
pins = "gpio12";
function = PMIC_GPIO_FUNC_NORMAL;
bias-high-impedance;
};
};
&pm7325_gpios {

30
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@ -499,6 +499,14 @@ vreg_bob_3p296: bob {
};
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/qcm6490/a660_zap.mbn";
};
&mdss {
status = "okay";
};
@ -694,6 +702,25 @@ &uart5 {
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p952>;
vcc-max-microamp = <800000>;
vccq-supply = <&vreg_l9b_1p2>;
vccq-max-microamp = <900000>;
vccq2-supply = <&vreg_l9b_1p2>;
vccq2-max-microamp = <900000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
status = "okay";
};
&usb_1 {
status = "okay";
};
@ -720,4 +747,7 @@ &usb_1_qmpphy {
&wifi {
memory-region = <&wlan_fw_mem>;
qcom,ath11k-calibration-variant = "Qualcomm_qcm6490idp";
status = "okay";
};

68
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -36,13 +36,13 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@100 {
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
@ -50,13 +50,13 @@ CPU0: cpu@100 {
power-domain-names = "cpr";
};
CPU1: cpu@101 {
cpu1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
@ -64,13 +64,13 @@ CPU1: cpu@101 {
power-domain-names = "cpr";
};
CPU2: cpu@102 {
cpu2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x102>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
@ -78,13 +78,13 @@ CPU2: cpu@102 {
power-domain-names = "cpr";
};
CPU3: cpu@103 {
cpu3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x103>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
@ -92,7 +92,7 @@ CPU3: cpu@103 {
power-domain-names = "cpr";
};
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@ -101,7 +101,7 @@ L2_0: l2-cache {
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -1679,10 +1679,10 @@ cluster_crit: cluster-crit {
cooling-maps {
map0 {
trip = <&cluster_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -1712,10 +1712,10 @@ cpu0_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -1745,10 +1745,10 @@ cpu1_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -1778,10 +1778,10 @@ cpu2_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -1811,10 +1811,10 @@ cpu3_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

127
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View File

@ -9,6 +9,7 @@
#define PM7250B_SID 8
#define PM7250B_SID1 9
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
#include "pm7250b.dtsi"
@ -153,6 +154,20 @@ debug_vm_mem: debug-vm@d0600000 {
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&kypd_vol_up_n>;
pinctrl-names = "default";
key-volume-up {
label = "Volume Up";
gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
linux,can-disable;
};
};
pmic-glink {
compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink";
@ -557,6 +572,14 @@ &gpi_dma1 {
status = "okay";
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/qcs6490/a660_zap.mbn";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@ -598,6 +621,7 @@ lt9611_out: endpoint {
};
&i2c1 {
clock-frequency = <100000>;
status = "okay";
typec-mux@1c {
@ -684,10 +708,56 @@ &mdss_edp_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-names = "default";
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>,
<0x208 &apps_smmu 0x1c84 0x1>,
<0x210 &apps_smmu 0x1c85 0x1>,
<0x218 &apps_smmu 0x1c86 0x1>,
<0x300 &apps_smmu 0x1c87 0x1>,
<0x400 &apps_smmu 0x1c88 0x1>,
<0x500 &apps_smmu 0x1c89 0x1>,
<0x501 &apps_smmu 0x1c90 0x1>;
status = "okay";
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
status = "okay";
};
&pm7325_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <1>;
bias-pull-up;
input-enable;
};
};
&pmk8350_rtc {
status = "okay";
};
&pon_pwrkey {
status = "okay";
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
@ -707,7 +777,7 @@ &remoteproc_cdsp {
};
&remoteproc_mpss {
firmware-name = "qcom/qcs6490/modem.mdt";
firmware-name = "qcom/qcs6490/modem.mbn";
status = "okay";
};
@ -716,6 +786,18 @@ &remoteproc_wpss {
status = "okay";
};
&sdhc_2 {
pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
vmmc-supply = <&vreg_l9c_2p96>;
vqmmc-supply = <&vreg_l6c_2p96>;
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
@ -790,8 +872,15 @@ &ufs_mem_phy {
status = "okay";
};
&venus {
status = "okay";
};
&wifi {
memory-region = <&wlan_fw_mem>;
qcom,ath11k-calibration-variant = "Qualcomm_rb3gen2";
status = "okay";
};
/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
@ -812,6 +901,21 @@ lt9611_rst_pin: lt9611-rst-state {
};
};
&sdc2_clk {
bias-disable;
drive-strength = <16>;
};
&sdc2_cmd {
bias-pull-up;
drive-strength = <10>;
};
&sdc2_data {
bias-pull-up;
drive-strength = <10>;
};
&tlmm {
lt9611_irq_pin: lt9611-irq-state {
pins = "gpio24";
@ -819,4 +923,25 @@ lt9611_irq_pin: lt9611-irq-state {
drive-strength = <2>;
bias-disable;
};
pcie1_reset_n: pcie1-reset-n-state {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
output-low;
bias-disable;
};
pcie1_wake_n: pcie1-wake-n-state {
pins = "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
sd_cd: sd-cd-state {
pins = "gpio91";
function = "gpio";
bias-pull-up;
};
};

2
arch/arm64/boot/dts/qcom/qcs8550.dtsi
View File

@ -154,7 +154,7 @@ adspslpi_mem: adspslpi-region@9ea00000 {
no-map;
};
mpss_dsm_mem: mpss_dsm_region@d4d00000 {
mpss_dsm_mem: mpss-dsm-region@d4d00000 {
reg = <0x0 0xd4d00000 0x0 0x3300000>;
no-map;
};

11
arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "sa8775p-ride-r3.dts"
/ {
model = "Qualcomm QCS9100 Ride Rev3";
compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";
};

11
arch/arm64/boot/dts/qcom/qcs9100-ride.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "sa8775p-ride.dts"
/ {
model = "Qualcomm QCS9100 Ride";
compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p";
};

89
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -25,22 +25,22 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -48,76 +48,76 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
};
@ -126,7 +126,7 @@ core3 {
idle-states {
entry-method = "psci";
CPU_OFF: cpu-sleep-0 {
cpu_off: cpu-sleep-0 {
compatible = "arm,idle-state";
entry-latency-us = <274>;
exit-latency-us = <480>;
@ -137,7 +137,7 @@ CPU_OFF: cpu-sleep-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
entry-latency-us = <584>;
exit-latency-us = <2332>;
@ -145,7 +145,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
arm,psci-suspend-param = <0x41000044>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
entry-latency-us = <2893>;
exit-latency-us = <4023>;
@ -187,33 +187,33 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
domain-idle-states = <&cluster_sleep_0 &cluster_sleep_1>;
};
};
@ -921,7 +921,7 @@ usb_1_hsphy: phy@88e3000 {
reg = <0x0 0x088e3000 0x0 0x120>;
#phy-cells = <0>;
clocks =<&gcc GCC_USB2_CLKREF_EN>;
clocks = <&gcc GCC_USB2_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
@ -1412,6 +1412,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
intc: interrupt-controller@17200000 {
@ -1498,7 +1499,7 @@ apps_rsc: rsc@17a00000 {
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 0>;
label = "apps_rsc";
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

14
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
View File

@ -24,7 +24,7 @@ chosen {
};
clocks {
clk40M: can-clk {
clk40m: can-clk {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
@ -188,23 +188,23 @@ vph_pwr: regulator-vph-pwr {
};
};
&CPU_PD0 {
&cpu_pd0 {
/delete-property/ power-domains;
};
&CPU_PD1 {
&cpu_pd1 {
/delete-property/ power-domains;
};
&CPU_PD2 {
&cpu_pd2 {
/delete-property/ power-domains;
};
&CPU_PD3 {
&cpu_pd3 {
/delete-property/ power-domains;
};
/delete-node/ &CLUSTER_PD;
/delete-node/ &cluster_pd;
&gpi_dma0 {
status = "okay";
@ -541,7 +541,7 @@ can@0 {
compatible = "microchip,mcp2518fd";
reg = <0>;
interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk40M>;
clocks = <&clk40m>;
spi-max-frequency = <10000000>;
vdd-supply = <&vdc_5v>;
xceiver-supply = <&vdc_5v>;

4
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -25,7 +25,7 @@ chosen {
};
clocks {
clk40M: can-clk {
clk40m: can-clk {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
@ -537,7 +537,7 @@ can@0 {
compatible = "microchip,mcp2518fd";
reg = <0>;
interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk40M>;
clocks = <&clk40m>;
spi-max-frequency = <10000000>;
vdd-supply = <&vdc_5v>;
xceiver-supply = <&vdc_5v>;

19
arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dts → arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso
View File

@ -4,8 +4,21 @@
*/
/dts-v1/;
/plugin/;
#include "qrb5165-rb5.dts"
#include <dt-bindings/clock/qcom,camcc-sm8250.h>
#include <dt-bindings/gpio/gpio.h>
/ {
reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
reusable;
linux,cma-default;
};
};
};
&camcc {
status = "okay";
@ -33,6 +46,9 @@ &cci1 {
};
&cci1_i2c0 {
#address-cells = <1>;
#size-cells = <0>;
camera@1a {
compatible = "sony,imx577";
reg = <0x1a>;
@ -52,7 +68,6 @@ camera@1a {
port {
imx577_ep: endpoint {
clock-lanes = <1>;
link-frequencies = /bits/ 64 <600000000>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csiphy2_ep>;

4
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -32,7 +32,7 @@ chosen {
};
/* Fixed crystal oscillator dedicated to MCP2518FD */
clk40M: can-clock {
clk40m: can-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
@ -1118,7 +1118,7 @@ &spi0 {
can@0 {
compatible = "microchip,mcp2518fd";
reg = <0>;
clocks = <&clk40M>;
clocks = <&clk40m>;
interrupts-extended = <&tlmm 15 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <10000000>;
vdd-supply = <&vdc_5v>;

121
arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
View File

@ -27,6 +27,83 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
vreg_conn_1p8: vreg_conn_1p8 {
compatible = "regulator-fixed";
regulator-name = "vreg_conn_1p8";
startup-delay-us = <4000>;
enable-active-high;
gpio = <&pmm8654au_1_gpios 4 GPIO_ACTIVE_HIGH>;
};
vreg_conn_pa: vreg_conn_pa {
compatible = "regulator-fixed";
regulator-name = "vreg_conn_pa";
startup-delay-us = <4000>;
enable-active-high;
gpio = <&pmm8654au_1_gpios 6 GPIO_ACTIVE_HIGH>;
};
wcn6855-pmu {
compatible = "qcom,wcn6855-pmu";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
vddio-supply = <&vreg_conn_pa>;
vddaon-supply = <&vreg_l2c>;
vddpmu-supply = <&vreg_conn_1p8>;
vddrfa0p95-supply = <&vreg_l2c>;
vddrfa1p3-supply = <&vreg_l6e>;
vddrfa1p9-supply = <&vreg_s5a>;
vddpcie1p3-supply = <&vreg_l6e>;
vddpcie1p9-supply = <&vreg_s5a>;
bt-enable-gpios = <&pmm8654au_1_gpios 8 GPIO_ACTIVE_HIGH>;
wlan-enable-gpios = <&pmm8654au_1_gpios 7 GPIO_ACTIVE_HIGH>;
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo7 {
regulator-name = "vreg_pmu_rfa_1p7";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
};
&apps_rsc {
@ -453,6 +530,20 @@ &pmm8654au_1_gpios {
"USB2_PWR_EN",
"USB2_FAULT";
wlan_en_state: wlan-en-state {
pins = "gpio7";
function = "normal";
output-low;
bias-pull-down;
};
bt_en_state: bt-en-state {
pins = "gpio8";
function = "normal";
output-low;
bias-pull-down;
};
usb2_en_state: usb2-en-state {
pins = "gpio9";
function = "normal";
@ -702,6 +793,25 @@ &pcie1_phy {
status = "okay";
};
&pcieport0 {
wifi@0 {
compatible = "pci17cb,1101";
reg = <0x10000 0x0 0x0 0x0 0x0>;
qcom,ath11k-calibration-variant = "QC_SA8775P_Ride";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
};
};
&remoteproc_adsp {
firmware-name = "qcom/sa8775p/adsp.mbn";
status = "okay";
@ -744,6 +854,17 @@ &uart17 {
pinctrl-0 = <&qup_uart17_default>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "qcom,wcn6855-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
};
};
&ufs_mem_hc {

701
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View File

File diff suppressed because it is too large Load Diff

84
arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi
View File

@ -6,82 +6,82 @@
* by Qualcomm firmware.
*/
&CPU0 {
&cpu0 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU1 {
&cpu1 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU2 {
&cpu2 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU3 {
&cpu3 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU4 {
&cpu4 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU5 {
&cpu5 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU6 {
&cpu6 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU7 {
&cpu7 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
/delete-node/ &domain_idle_states;
&idle_states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x40003444>;
@ -92,15 +92,15 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
};
/delete-node/ &CPU_PD0;
/delete-node/ &CPU_PD1;
/delete-node/ &CPU_PD2;
/delete-node/ &CPU_PD3;
/delete-node/ &CPU_PD4;
/delete-node/ &CPU_PD5;
/delete-node/ &CPU_PD6;
/delete-node/ &CPU_PD7;
/delete-node/ &CLUSTER_PD;
/delete-node/ &cpu_pd0;
/delete-node/ &cpu_pd1;
/delete-node/ &cpu_pd2;
/delete-node/ &cpu_pd3;
/delete-node/ &cpu_pd4;
/delete-node/ &cpu_pd5;
/delete-node/ &cpu_pd6;
/delete-node/ &cpu_pd7;
/delete-node/ &cluster_pd;
&apps_rsc {
/delete-property/ power-domains;

8
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
View File

@ -53,14 +53,14 @@ skin-temp-crit {
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

8
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@ -71,14 +71,14 @@ skin-temp-crit {
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

8
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
View File

@ -78,14 +78,14 @@ skin-temp-crit {
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

366
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -77,28 +77,28 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -106,206 +106,206 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -313,7 +313,7 @@ core7 {
idle_states: idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-down";
arm,psci-suspend-param = <0x40000003>;
@ -323,7 +323,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@ -333,7 +333,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-down";
arm,psci-suspend-param = <0x40000003>;
@ -343,7 +343,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@ -355,27 +355,24 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
};
domain_idle_states: domain-idle-states {
CLUSTER_SLEEP_PC: cluster-sleep-0 {
cluster_sleep_pc: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "cluster-l3-power-collapse";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
exit-latency-us = <3048>;
min-residency-us = <6118>;
};
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
cluster_sleep_cx_ret: cluster-sleep-1 {
compatible = "domain-idle-state";
idle-state-name = "cluster-cx-retention";
arm,psci-suspend-param = <0x41001244>;
entry-latency-us = <3638>;
exit-latency-us = <4562>;
min-residency-us = <8467>;
};
CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
cluster_aoss_sleep: cluster-sleep-2 {
compatible = "domain-idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x4100b244>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
@ -583,59 +580,59 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu0 {
cpu_pd0: cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD1: cpu1 {
cpu_pd1: cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD2: cpu2 {
cpu_pd2: cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD3: cpu3 {
cpu_pd3: cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD4: cpu4 {
cpu_pd4: cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD5: cpu5 {
cpu_pd5: cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD6: cpu6 {
cpu_pd6: cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD7: cpu7 {
cpu_pd7: cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CLUSTER_PD: cpu-cluster0 {
cluster_pd: cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_PC
&CLUSTER_SLEEP_CX_RET
&CLUSTER_AOSS_SLEEP>;
domain-idle-states = <&cluster_sleep_pc
&cluster_sleep_cx_ret
&cluster_aoss_sleep>;
};
};
@ -2546,7 +2543,7 @@ etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -2566,7 +2563,7 @@ etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -2586,7 +2583,7 @@ etm@7240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07240000 0 0x1000>;
cpu = <&CPU2>;
cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -2606,7 +2603,7 @@ etm@7340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07340000 0 0x1000>;
cpu = <&CPU3>;
cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -2626,7 +2623,7 @@ etm@7440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07440000 0 0x1000>;
cpu = <&CPU4>;
cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -2646,7 +2643,7 @@ etm@7540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07540000 0 0x1000>;
cpu = <&CPU5>;
cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -2666,7 +2663,7 @@ etm@7640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07640000 0 0x1000>;
cpu = <&CPU6>;
cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -2686,7 +2683,7 @@ etm@7740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3625,6 +3622,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
intc: interrupt-controller@17a00000 {
@ -3734,7 +3732,7 @@ apps_rsc: rsc@18200000 {
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
rpmhcc: clock-controller {
compatible = "qcom,sc7180-rpmh-clk";
@ -4063,21 +4061,21 @@ cpu0_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4111,21 +4109,21 @@ cpu1_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4159,21 +4157,21 @@ cpu2_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4207,21 +4205,21 @@ cpu3_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4255,21 +4253,21 @@ cpu4_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4303,21 +4301,21 @@ cpu5_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4351,13 +4349,13 @@ cpu6_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4391,13 +4389,13 @@ cpu7_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4431,13 +4429,13 @@ cpu8_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu8_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu8_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4471,13 +4469,13 @@ cpu9_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu9_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu9_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

10
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View File

@ -29,7 +29,7 @@
/ {
cpus {
domain_idle_states: domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x40003444>;
entry-latency-us = <2752>;
@ -52,8 +52,12 @@ venus_mem: memory@8b200000 {
};
};
&CLUSTER_PD {
domain-idle-states = <&CLUSTER_SLEEP_0>;
&cluster_pd {
domain-idle-states = <&cluster_sleep_0>;
};
&gpu {
status = "okay";
};
&lpass_aon {

397
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -193,15 +193,15 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@ -209,12 +209,12 @@ CPU0: cpu@0 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -222,15 +222,15 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@ -238,23 +238,23 @@ CPU1: cpu@100 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@ -262,23 +262,23 @@ CPU2: cpu@200 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@ -286,23 +286,23 @@ CPU3: cpu@300 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
operating-points-v2 = <&cpu4_opp_table>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
@ -310,23 +310,23 @@ CPU4: cpu@400 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
operating-points-v2 = <&cpu4_opp_table>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
@ -334,23 +334,23 @@ CPU5: cpu@500 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
operating-points-v2 = <&cpu4_opp_table>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
@ -358,23 +358,23 @@ CPU6: cpu@600 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 2>;
enable-method = "psci";
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
operating-points-v2 = <&cpu7_opp_table>;
capacity-dmips-mhz = <1985>;
dynamic-power-coefficient = <552>;
@ -382,46 +382,46 @@ CPU7: cpu@700 {
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -429,7 +429,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-down";
arm,psci-suspend-param = <0x40000003>;
@ -439,7 +439,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@ -449,7 +449,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-down";
arm,psci-suspend-param = <0x40000003>;
@ -459,7 +459,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@ -471,7 +471,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
};
domain_idle_states: domain-idle-states {
CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
cluster_sleep_apss_off: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
@ -479,7 +479,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
min-residency-us = <6118>;
};
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
cluster_sleep_cx_ret: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41001344>;
entry-latency-us = <3263>;
@ -487,7 +487,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
min-residency-us = <8467>;
};
CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 {
cluster_sleep_llcc_off: cluster-sleep-2 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100b344>;
entry-latency-us = <3638>;
@ -845,8 +845,13 @@ wlan_smp2p_in: wlan-wpss-to-ap {
};
};
pmu {
compatible = "arm,armv8-pmuv3";
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-a78 {
compatible = "arm,cortex-a78-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
@ -854,57 +859,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>;
domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>;
};
};
@ -2318,7 +2323,7 @@ pcie1_phy: phy@1c0e000 {
status = "disabled";
};
ufs_mem_hc: ufs@1d84000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
@ -2718,7 +2723,7 @@ slimbam: dma-controller@3a84000 {
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,controlled-remotely;
num-channels = <31>;
num-channels = <31>;
qcom,ee = <1>;
qcom,num-ees = <2>;
iommus = <&apps_smmu 0x1826 0x0>;
@ -2823,6 +2828,8 @@ gpu: gpu@3d00000 {
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
status = "disabled";
gpu_zap_shader: zap-shader {
memory-region = <&gpu_zap_mem>;
};
@ -2834,14 +2841,14 @@ opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1804000>;
opp-supported-hw = <0x07>;
opp-supported-hw = <0x17>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <4068000>;
opp-supported-hw = <0x07>;
opp-supported-hw = <0x17>;
};
/* Only applicable for SKUs which has 550Mhz as Fmax */
@ -2856,14 +2863,14 @@ opp-550000000-1 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
opp-supported-hw = <0x06>;
opp-supported-hw = <0x16>;
};
opp-608000000 {
opp-hz = /bits/ 64 <608000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <8368000>;
opp-supported-hw = <0x06>;
opp-supported-hw = <0x16>;
};
opp-700000000 {
@ -3278,7 +3285,7 @@ etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3298,7 +3305,7 @@ etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3318,7 +3325,7 @@ etm@7240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07240000 0 0x1000>;
cpu = <&CPU2>;
cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3338,7 +3345,7 @@ etm@7340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07340000 0 0x1000>;
cpu = <&CPU3>;
cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3358,7 +3365,7 @@ etm@7440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07440000 0 0x1000>;
cpu = <&CPU4>;
cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3378,7 +3385,7 @@ etm@7540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07540000 0 0x1000>;
cpu = <&CPU5>;
cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3398,7 +3405,7 @@ etm@7640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07640000 0 0x1000>;
cpu = <&CPU6>;
cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3418,7 +3425,7 @@ etm@7740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -6057,7 +6064,7 @@ apps_rsc: rsc@18200000 {
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
@ -6177,17 +6184,17 @@ cpu0_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6220,17 +6227,17 @@ cpu1_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6263,17 +6270,17 @@ cpu2_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6306,17 +6313,17 @@ cpu3_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6349,17 +6356,17 @@ cpu4_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6392,17 +6399,17 @@ cpu5_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6435,17 +6442,17 @@ cpu6_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6478,17 +6485,17 @@ cpu7_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6521,17 +6528,17 @@ cpu8_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu8_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu8_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6564,17 +6571,17 @@ cpu9_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu9_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu9_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6607,17 +6614,17 @@ cpu10_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu10_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu10_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6650,17 +6657,17 @@ cpu11_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu11_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu11_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

166
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -42,28 +42,28 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -71,207 +71,207 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-unified;
cache-level = <2>;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -279,7 +279,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <355>;
@ -288,7 +288,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <2411>;
@ -299,7 +299,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
cluster_sleep_apss_off: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <3300>;
@ -307,7 +307,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
min-residency-us = <6000>;
};
CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
cluster_sleep_aoss_sleep: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100a344>;
entry-latency-us = <3263>;
@ -541,57 +541,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
};
};
@ -3662,7 +3662,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
remoteproc_adsp: remoteproc@17300000 {
@ -3790,7 +3790,7 @@ apps_rsc: rsc@18200000 {
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
label = "apps_rsc";
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
@ -3868,7 +3868,7 @@ lmh@18350800 {
compatible = "qcom,sc8180x-lmh";
reg = <0 0x18350800 0 0x400>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU4>;
cpus = <&cpu4>;
qcom,lmh-temp-arm-millicelsius = <65000>;
qcom,lmh-temp-low-millicelsius = <94500>;
qcom,lmh-temp-high-millicelsius = <95000>;
@ -3880,7 +3880,7 @@ lmh@18358800 {
compatible = "qcom,sc8180x-lmh";
reg = <0 0x18358800 0 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU0>;
cpus = <&cpu0>;
qcom,lmh-temp-arm-millicelsius = <65000>;
qcom,lmh-temp-low-millicelsius = <94500>;
qcom,lmh-temp-high-millicelsius = <95000>;

169
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@ -20,6 +20,7 @@ aliases {
i2c4 = &i2c4;
i2c21 = &i2c21;
serial0 = &uart17;
serial1 = &uart2;
};
backlight: backlight {
@ -260,6 +261,70 @@ usb1_sbu_mux: endpoint {
};
};
};
wcn6855-pmu {
compatible = "qcom,wcn6855-pmu";
pinctrl-0 = <&bt_en>, <&wlan_en>;
pinctrl-names = "default";
wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
vddio-supply = <&vreg_s10b>;
vddaon-supply = <&vreg_s12b>;
vddpmu-supply = <&vreg_s12b>;
vddpmumx-supply = <&vreg_s12b>;
vddpmucx-supply = <&vreg_s12b>;
vddrfa0p95-supply = <&vreg_s12b>;
vddrfa1p3-supply = <&vreg_s11b>;
vddrfa1p9-supply = <&vreg_s1c>;
vddpcie1p3-supply = <&vreg_s11b>;
vddpcie1p9-supply = <&vreg_s1c>;
regulators {
vreg_pmu_rfa_cmn_0p8: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn_0p8";
};
vreg_pmu_aon_0p8: ldo1 {
regulator-name = "vreg_pmu_aon_0p8";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p8: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p8";
};
vreg_pmu_btcmx_0p8: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p8";
};
vreg_pmu_pcie_1p8: ldo5 {
regulator-name = "vreg_pmu_pcie_1p8";
};
vreg_pmu_pcie_0p9: ldo6 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_rfa_0p8: ldo7 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo8 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo9 {
regulator-name = "vreg_pmu_rfa_1p7";
};
};
};
};
&apps_rsc {
@ -269,6 +334,15 @@ regulators-0 {
vdd-l3-l5-supply = <&vreg_s11b>;
vreg_s10b: smps10 {
regulator-name = "vreg_s10b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
regulator-boot-on;
};
vreg_s11b: smps11 {
regulator-name = "vreg_s11b";
regulator-min-microvolt = <1272000>;
@ -276,6 +350,13 @@ vreg_s11b: smps11 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s12b: smps12 {
regulator-name = "vreg_s12b";
regulator-min-microvolt = <984000>;
regulator-max-microvolt = <984000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b: ldo3 {
regulator-name = "vreg_l3b";
regulator-min-microvolt = <1200000>;
@ -304,6 +385,13 @@ regulators-1 {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vreg_s1c: smps1 {
regulator-name = "vreg_s1c";
regulator-min-microvolt = <1888000>;
regulator-max-microvolt = <1888000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <1800000>;
@ -583,6 +671,25 @@ &pcie4_phy {
status = "okay";
};
&pcie4_port0 {
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
qcom,ath11k-calibration-variant = "QC_8280XP_CRD";
};
};
&pmc8280c_lpg {
status = "okay";
};
@ -643,6 +750,26 @@ &sdc2 {
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "qcom,wcn6855-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
};
};
&uart17 {
compatible = "qcom,geni-debug-uart";
@ -788,6 +915,13 @@ hastings_reg_en: hastings-reg-en-state {
&tlmm {
gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
bt_en: bt-en-state {
pins = "gpio133";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
edp_reg_en: edp-reg-en-state {
pins = "gpio25";
function = "gpio";
@ -981,6 +1115,34 @@ reset-n-pins {
};
};
uart2_default: uart2-default-state {
cts-pins {
pins = "gpio121";
function = "qup2";
bias-bus-hold;
};
rts-pins {
pins = "gpio122";
function = "qup2";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio124";
function = "qup2";
bias-pull-up;
};
tx-pins {
pins = "gpio123";
function = "qup2";
drive-strength = <2>;
bias-disable;
};
};
usb0_sbu_default: usb0-sbu-state {
oe-n-pins {
pins = "gpio101";
@ -1030,4 +1192,11 @@ mode-pins {
output-high;
};
};
wlan_en: wlan-en-state {
pins = "gpio134";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};

120
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -346,18 +346,18 @@ skin-temp-crit {
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -400,6 +400,70 @@ usb1_sbu_mux: endpoint {
};
};
};
wcn6855-pmu {
compatible = "qcom,wcn6855-pmu";
pinctrl-0 = <&bt_default>, <&wlan_en>;
pinctrl-names = "default";
wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
vddio-supply = <&vreg_s10b>;
vddaon-supply = <&vreg_s12b>;
vddpmu-supply = <&vreg_s12b>;
vddpmumx-supply = <&vreg_s12b>;
vddpmucx-supply = <&vreg_s12b>;
vddrfa0p95-supply = <&vreg_s12b>;
vddrfa1p3-supply = <&vreg_s11b>;
vddrfa1p9-supply = <&vreg_s1c>;
vddpcie1p3-supply = <&vreg_s11b>;
vddpcie1p9-supply = <&vreg_s1c>;
regulators {
vreg_pmu_rfa_cmn_0p8: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn_0p8";
};
vreg_pmu_aon_0p8: ldo1 {
regulator-name = "vreg_pmu_aon_0p8";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p8: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p8";
};
vreg_pmu_btcmx_0p8: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p8";
};
vreg_pmu_pcie_1p8: ldo5 {
regulator-name = "vreg_pmu_pcie_1p8";
};
vreg_pmu_pcie_0p9: ldo6 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_rfa_0p8: ldo7 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo8 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo9 {
regulator-name = "vreg_pmu_rfa_1p7";
};
};
};
};
&apps_rsc {
@ -426,7 +490,6 @@ vreg_s11b: smps11 {
regulator-min-microvolt = <1272000>;
regulator-max-microvolt = <1272000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_s12b: smps12 {
@ -434,7 +497,6 @@ vreg_s12b: smps12 {
regulator-min-microvolt = <984000>;
regulator-max-microvolt = <984000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l1b: ldo1 {
@ -633,7 +695,6 @@ camera@10 {
port {
ov5675_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <450000000>;
remote-endpoint = <&csiphy0_lanes01_ep>;
@ -927,6 +988,16 @@ wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
qcom,ath11k-calibration-variant = "LE_X13S";
};
};
@ -1258,20 +1329,16 @@ &uart2 {
bluetooth {
compatible = "qcom,wcn6855-bt";
vddio-supply = <&vreg_s10b>;
vddbtcxmx-supply = <&vreg_s12b>;
vddrfacmn-supply = <&vreg_s12b>;
vddrfa0p8-supply = <&vreg_s12b>;
vddrfa1p2-supply = <&vreg_s11b>;
vddrfa1p7-supply = <&vreg_s1c>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
max-speed = <3200000>;
enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&bt_default>;
pinctrl-names = "default";
};
};
@ -1761,4 +1828,11 @@ reset-pins {
bias-disable;
};
};
wlan_en: wlan-en-state {
pins = "gpio134";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};

1032
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts Normal file
View File

File diff suppressed because it is too large Load Diff

211
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -44,7 +44,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a78c";
reg = <0x0 0x0>;
@ -52,19 +52,19 @@ CPU0: cpu@0 {
enable-method = "psci";
capacity-dmips-mhz = <981>;
dynamic-power-coefficient = <549>;
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -72,7 +72,7 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a78c";
reg = <0x0 0x100>;
@ -80,22 +80,22 @@ CPU1: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <981>;
dynamic-power-coefficient = <549>;
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
next-level-cache = <&l2_100>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a78c";
reg = <0x0 0x200>;
@ -103,22 +103,22 @@ CPU2: cpu@200 {
enable-method = "psci";
capacity-dmips-mhz = <981>;
dynamic-power-coefficient = <549>;
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
next-level-cache = <&l2_200>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a78c";
reg = <0x0 0x300>;
@ -126,22 +126,22 @@ CPU3: cpu@300 {
enable-method = "psci";
capacity-dmips-mhz = <981>;
dynamic-power-coefficient = <549>;
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
next-level-cache = <&l2_300>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-x1c";
reg = <0x0 0x400>;
@ -149,22 +149,22 @@ CPU4: cpu@400 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <590>;
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD4>;
next-level-cache = <&l2_400>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-x1c";
reg = <0x0 0x500>;
@ -172,22 +172,22 @@ CPU5: cpu@500 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <590>;
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD5>;
next-level-cache = <&l2_500>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-x1c";
reg = <0x0 0x600>;
@ -195,22 +195,22 @@ CPU6: cpu@600 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <590>;
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD6>;
next-level-cache = <&l2_600>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x1c";
reg = <0x0 0x700>;
@ -218,53 +218,53 @@ CPU7: cpu@700 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <590>;
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD7>;
next-level-cache = <&l2_700>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -272,7 +272,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -282,7 +282,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -294,7 +294,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <3263>;
@ -593,57 +593,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&cluster_sleep_0>;
};
};
@ -1007,6 +1007,24 @@ spi18: spi@888000 {
status = "disabled";
};
uart18: serial@888000 {
compatible = "qcom,geni-uart";
reg = <0 0x00888000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
operating-points-v2 = <&qup_opp_table_100mhz>;
power-domains = <&rpmhpd SC8280XP_CX>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
interconnect-names = "qup-core", "qup-config";
pinctrl-0 = <&qup_uart18_default>;
pinctrl-names = "default";
status = "disabled";
};
i2c19: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0088c000 0 0x4000>;
@ -2294,7 +2312,7 @@ pcie2a_phy: phy@1c24000 {
status = "disabled";
};
ufs_mem_hc: ufs@1d84000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
@ -2360,7 +2378,7 @@ ufs_mem_phy: phy@1d87000 {
status = "disabled";
};
ufs_card_hc: ufs@1da4000 {
ufs_card_hc: ufshc@1da4000 {
compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01da4000 0 0x3000>;
@ -4871,6 +4889,36 @@ cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
bias-pull-down;
};
};
qup_uart18_default: qup-uart18-default-state {
cts-pins {
pins = "gpio66";
function = "qup18";
drive-strength = <2>;
bias-disable;
};
rts-pins {
pins = "gpio67";
function = "qup18";
drive-strength = <2>;
bias-disable;
};
tx-pins {
pins = "gpio68";
function = "qup18";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio69";
function = "qup18";
drive-strength = <2>;
bias-disable;
};
};
};
apps_smmu: iommu@15000000 {
@ -5008,6 +5056,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
intc: interrupt-controller@17a00000 {
@ -5111,7 +5160,7 @@ apps_rsc: rsc@18200000 {
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
label = "apps_rsc";
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

32
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
View File

@ -104,12 +104,20 @@ vreg_l10a_1p8: vreg-l10a-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_l10a_1p8";
regulator-min-microvolt = <1804000>;
regulator-max-microvolt = <1896000>;
regulator-max-microvolt = <1804000>;
regulator-always-on;
regulator-boot-on;
};
};
&adreno_gpu {
status = "okay";
};
&adreno_gpu_zap {
firmware-name = "qcom/sda660/a512_zap.mbn";
};
&adsp_pil {
firmware-name = "qcom/sda660/adsp.mbn";
};
@ -244,6 +252,11 @@ &qusb2phy1 {
vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
};
&remoteproc_mss {
firmware-name = "qcom/sda660/mba.mbn", "qcom/sda660/modem.mbn";
status = "okay";
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm660-regulators";
@ -283,6 +296,11 @@ vreg_l1a_1p225: l1 {
regulator-allow-set-load;
};
vreg_l5a_0p8: l5 {
regulator-min-microvolt = <848000>;
regulator-max-microvolt = <848000>;
};
vreg_l6a_1p3: l6 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1368000>;
@ -481,3 +499,15 @@ &usb3_qmpphy {
vdda-pll-supply = <&vreg_l10a_1p8>;
status = "okay";
};
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.8-xo-supply = <&vreg_l9a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l6a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l19a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l8b_3p3>;
qcom,ath10k-calibration-variant = "Inforce_IFC6560";
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts
View File

@ -40,7 +40,7 @@ framebuffer@90001000 {
};
reserved-memory {
other_ext_region@0 {
other-ext-region@0 {
no-map;
reg = <0x00 0x84500000 0x00 0x2300000>;
};

190
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -49,170 +49,170 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@100 {
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
cpu-idle-states = <&perf_cpu_sleep_0
&perf_cpu_sleep_1
&perf_cluster_sleep_0
&perf_cluster_sleep_1
&perf_cluster_sleep_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&l2_1>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@101 {
cpu1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
cpu-idle-states = <&perf_cpu_sleep_0
&perf_cpu_sleep_1
&perf_cluster_sleep_0
&perf_cluster_sleep_1
&perf_cluster_sleep_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
CPU2: cpu@102 {
cpu2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
cpu-idle-states = <&perf_cpu_sleep_0
&perf_cpu_sleep_1
&perf_cluster_sleep_0
&perf_cluster_sleep_1
&perf_cluster_sleep_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
CPU3: cpu@103 {
cpu3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
cpu-idle-states = <&perf_cpu_sleep_0
&perf_cpu_sleep_1
&perf_cluster_sleep_0
&perf_cluster_sleep_1
&perf_cluster_sleep_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
CPU4: cpu@0 {
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
cpu-idle-states = <&pwr_cpu_sleep_0
&pwr_cpu_sleep_1
&pwr_cluster_sleep_0
&pwr_cluster_sleep_1
&pwr_cluster_sleep_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU5: cpu@1 {
cpu5: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
cpu-idle-states = <&pwr_cpu_sleep_0
&pwr_cpu_sleep_1
&pwr_cluster_sleep_0
&pwr_cluster_sleep_1
&pwr_cluster_sleep_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU6: cpu@2 {
cpu6: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
cpu-idle-states = <&pwr_cpu_sleep_0
&pwr_cpu_sleep_1
&pwr_cluster_sleep_0
&pwr_cluster_sleep_1
&pwr_cluster_sleep_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU7: cpu@3 {
cpu7: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
cpu-idle-states = <&pwr_cpu_sleep_0
&pwr_cpu_sleep_1
&pwr_cluster_sleep_0
&pwr_cluster_sleep_1
&pwr_cluster_sleep_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
cluster1 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
};
@ -220,7 +220,7 @@ core3 {
idle-states {
entry-method = "psci";
PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
pwr_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "pwr-retention";
arm,psci-suspend-param = <0x40000002>;
@ -229,7 +229,7 @@ PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
min-residency-us = <200>;
};
PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
pwr_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "pwr-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -239,7 +239,7 @@ PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
local-timer-stop;
};
PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
perf_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "perf-retention";
arm,psci-suspend-param = <0x40000002>;
@ -248,7 +248,7 @@ PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
min-residency-us = <200>;
};
PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
perf_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "perf-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -258,7 +258,7 @@ PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
local-timer-stop;
};
PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
pwr_cluster_sleep_0: cluster-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-dynamic-retention";
arm,psci-suspend-param = <0x400000F2>;
@ -268,7 +268,7 @@ PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
local-timer-stop;
};
PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
pwr_cluster_sleep_1: cluster-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-retention";
arm,psci-suspend-param = <0x400000F3>;
@ -278,7 +278,7 @@ PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
local-timer-stop;
};
PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
pwr_cluster_sleep_2: cluster-sleep-0-2 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-retention";
arm,psci-suspend-param = <0x400000F4>;
@ -288,7 +288,7 @@ PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
local-timer-stop;
};
PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
perf_cluster_sleep_0: cluster-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-dynamic-retention";
arm,psci-suspend-param = <0x400000F2>;
@ -298,7 +298,7 @@ PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
local-timer-stop;
};
PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
perf_cluster_sleep_1: cluster-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-retention";
arm,psci-suspend-param = <0x400000F3>;
@ -308,7 +308,7 @@ PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
local-timer-stop;
};
PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
perf_cluster_sleep_2: cluster-sleep-1-2 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-retention";
arm,psci-suspend-param = <0x400000F4>;
@ -665,8 +665,6 @@ anoc2_smmu: iommu@16c0000 {
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
a2noc: interconnect@1704000 {
@ -1150,6 +1148,10 @@ opp-160000000 {
opp-supported-hw = <0xff>;
};
};
adreno_gpu_zap: zap-shader {
memory-region = <&zap_shader_region>;
};
};
kgsl_smmu: iommu@5040000 {
@ -1186,8 +1188,6 @@ kgsl_smmu: iommu@5040000 {
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gpucc: clock-controller@5065000 {
@ -1203,7 +1203,6 @@ gpucc: clock-controller@5065000 {
clock-names = "xo",
"gcc_gpu_gpll0_clk",
"gcc_gpu_gpll0_div_clk";
status = "disabled";
};
lpass_smmu: iommu@5100000 {
@ -1233,8 +1232,6 @@ lpass_smmu: iommu@5100000 {
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sram@290000 {
@ -2415,6 +2412,33 @@ intc: interrupt-controller@17a00000 {
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0x18800000 0x800000>;
reg-names = "membase";
memory-region = <&wlan_msa_mem>;
clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>;
clock-names = "cxo_ref_clk_pin";
interrupts =
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&anoc2_smmu 0x1a00>,
<&anoc2_smmu 0x1a01>;
qcom,snoc-host-cap-8bit-quirk;
qcom,no-msa-ready-indicator;
status = "disabled";
};
};
sound: sound {

26
arch/arm64/boot/dts/qcom/sdm632.dtsi
View File

@ -14,10 +14,10 @@ cpu0-thermal {
cooling-maps {
map0 {
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -42,40 +42,40 @@ cpu7-thermal {
/*
* SDM632 uses Kryo 250 instead of Cortex A53
* CPU0-3 are efficiency cores, CPU4-7 are performance cores
* cpu0-3 are efficiency cores, cpu4-7 are performance cores
*/
&CPU0 {
&cpu0 {
compatible = "qcom,kryo250";
};
&CPU1 {
&cpu1 {
compatible = "qcom,kryo250";
};
&CPU2 {
&cpu2 {
compatible = "qcom,kryo250";
};
&CPU3 {
&cpu3 {
compatible = "qcom,kryo250";
};
&CPU4 {
&cpu4 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
&CPU5 {
&cpu5 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
&CPU6 {
&cpu6 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
&CPU7 {
&cpu7 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};

16
arch/arm64/boot/dts/qcom/sdm660.dtsi
View File

@ -85,49 +85,49 @@ opp-160000000 {
};
};
&CPU0 {
&cpu0 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <1024>;
/delete-property/ operating-points-v2;
};
&CPU1 {
&cpu1 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <1024>;
/delete-property/ operating-points-v2;
};
&CPU2 {
&cpu2 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <1024>;
/delete-property/ operating-points-v2;
};
&CPU3 {
&cpu3 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <1024>;
/delete-property/ operating-points-v2;
};
&CPU4 {
&cpu4 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <640>;
/delete-property/ operating-points-v2;
};
&CPU5 {
&cpu5 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <640>;
/delete-property/ operating-points-v2;
};
&CPU6 {
&cpu6 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <640>;
/delete-property/ operating-points-v2;
};
&CPU7 {
&cpu7 {
compatible = "qcom,kryo260";
capacity-dmips-mhz = <640>;
/delete-property/ operating-points-v2;

159
arch/arm64/boot/dts/qcom/sdm670.dtsi
View File

@ -32,7 +32,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x0>;
@ -43,15 +43,15 @@ CPU0: cpu@0 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
cache-level = <2>;
cache-unified;
L3_0: l3-cache {
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -59,7 +59,7 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x100>;
@ -70,18 +70,18 @@ CPU1: cpu@100 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
next-level-cache = <&L2_100>;
L2_100: l2-cache {
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x200>;
@ -92,18 +92,18 @@ CPU2: cpu@200 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
next-level-cache = <&L2_200>;
L2_200: l2-cache {
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x300>;
@ -114,18 +114,18 @@ CPU3: cpu@300 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
next-level-cache = <&L2_300>;
L2_300: l2-cache {
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x400>;
@ -136,18 +136,18 @@ CPU4: cpu@400 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
next-level-cache = <&L2_400>;
L2_400: l2-cache {
next-level-cache = <&l2_400>;
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x500>;
@ -158,18 +158,18 @@ CPU5: cpu@500 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
next-level-cache = <&L2_500>;
L2_500: l2-cache {
next-level-cache = <&l2_500>;
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x600>;
@ -180,18 +180,18 @@ CPU6: cpu@600 {
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
next-level-cache = <&L2_600>;
L2_600: l2-cache {
next-level-cache = <&l2_600>;
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo360";
reg = <0x0 0x700>;
@ -202,49 +202,49 @@ CPU7: cpu@700 {
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
next-level-cache = <&L2_700>;
L2_700: l2-cache {
next-level-cache = <&l2_700>;
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -252,7 +252,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -262,7 +262,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -274,7 +274,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3263>;
@ -429,57 +429,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&cluster_sleep_0>;
};
};
@ -1737,6 +1737,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
gladiator_noc: interconnect@17900000 {
@ -1762,7 +1763,7 @@ apps_rsc: rsc@179c0000 {
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

74
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View File

@ -164,7 +164,7 @@ &cpus {
};
&cpu_idle_states {
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-down";
arm,psci-suspend-param = <0x40000003>;
@ -174,7 +174,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@ -184,7 +184,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-down";
arm,psci-suspend-param = <0x40000003>;
@ -194,7 +194,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@ -204,7 +204,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x400000F4>;
@ -215,68 +215,68 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
};
&CPU0 {
&cpu0 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU1 {
&cpu1 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU2 {
&cpu2 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU3 {
&cpu3 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU4 {
&cpu4 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU5 {
&cpu5 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU6 {
&cpu6 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU7 {
&cpu7 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
&lmh_cluster0 {

21
arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dts → arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
View File

@ -4,8 +4,21 @@
*/
/dts-v1/;
/plugin/;
#include "sdm845-db845c.dts"
#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/gpio/gpio.h>
/ {
reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
reusable;
linux,cma-default;
};
};
};
&camss {
vdda-phy-supply = <&vreg_l1a_0p875>;
@ -28,6 +41,9 @@ &cci {
};
&cci_i2c0 {
#address-cells = <1>;
#size-cells = <0>;
camera@10 {
compatible = "ovti,ov8856";
reg = <0x10>;
@ -65,6 +81,9 @@ ov8856_ep: endpoint {
};
&cci_i2c1 {
#address-cells = <1>;
#size-cells = <0>;
camera@60 {
compatible = "ovti,ov7251";

4
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@ -31,7 +31,7 @@ chosen {
};
/* Fixed crystal oscillator dedicated to MCP2517FD */
clk40M: can-clock {
clk40m: can-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
@ -863,7 +863,7 @@ &spi0 {
can@0 {
compatible = "microchip,mcp2517fd";
reg = <0>;
clocks = <&clk40M>;
clocks = <&clk40m>;
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <10000000>;
vdd-supply = <&vdc_5v>;

179
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -91,7 +91,7 @@ cpus: cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x0>;
@ -103,16 +103,16 @@ CPU0: cpu@0 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -120,7 +120,7 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x100>;
@ -132,19 +132,19 @@ CPU1: cpu@100 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
#cooling-cells = <2>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x200>;
@ -156,19 +156,19 @@ CPU2: cpu@200 {
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
#cooling-cells = <2>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x300>;
@ -181,18 +181,18 @@ CPU3: cpu@300 {
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
next-level-cache = <&L2_300>;
L2_300: l2-cache {
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x400>;
@ -204,19 +204,19 @@ CPU4: cpu@400 {
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
#cooling-cells = <2>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
next-level-cache = <&l2_400>;
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x500>;
@ -228,19 +228,19 @@ CPU5: cpu@500 {
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
#cooling-cells = <2>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
next-level-cache = <&l2_500>;
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x600>;
@ -252,19 +252,19 @@ CPU6: cpu@600 {
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
#cooling-cells = <2>;
next-level-cache = <&L2_600>;
L2_600: l2-cache {
next-level-cache = <&l2_600>;
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo385";
reg = <0x0 0x700>;
@ -276,50 +276,50 @@ CPU7: cpu@700 {
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
#cooling-cells = <2>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
next-level-cache = <&l2_700>;
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -327,7 +327,7 @@ core7 {
cpu_idle_states: idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -337,7 +337,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -349,7 +349,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3263>;
@ -717,57 +717,57 @@ psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&cluster_sleep_0>;
};
};
@ -3615,7 +3615,7 @@ etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3635,7 +3635,7 @@ etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3655,7 +3655,7 @@ etm@7240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07240000 0 0x1000>;
cpu = <&CPU2>;
cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3675,7 +3675,7 @@ etm@7340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07340000 0 0x1000>;
cpu = <&CPU3>;
cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3695,7 +3695,7 @@ etm@7440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07440000 0 0x1000>;
cpu = <&CPU4>;
cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3715,7 +3715,7 @@ etm@7540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07540000 0 0x1000>;
cpu = <&CPU5>;
cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3735,7 +3735,7 @@ etm@7640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07640000 0 0x1000>;
cpu = <&CPU6>;
cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3755,7 +3755,7 @@ etm@7740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3959,7 +3959,7 @@ lmh_cluster1: lmh@17d70800 {
compatible = "qcom,sdm845-lmh";
reg = <0 0x17d70800 0 0x400>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU4>;
cpus = <&cpu4>;
qcom,lmh-temp-arm-millicelsius = <65000>;
qcom,lmh-temp-low-millicelsius = <94500>;
qcom,lmh-temp-high-millicelsius = <95000>;
@ -3971,7 +3971,7 @@ lmh_cluster0: lmh@17d78800 {
compatible = "qcom,sdm845-lmh";
reg = <0 0x17d78800 0 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU0>;
cpus = <&cpu0>;
qcom,lmh-temp-arm-millicelsius = <65000>;
qcom,lmh-temp-low-millicelsius = <94500>;
qcom,lmh-temp-high-millicelsius = <95000>;
@ -5159,6 +5159,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
anoc_1_tbu: tbu@150c5000 {
@ -5277,7 +5278,7 @@ apps_rsc: rsc@179c0000 {
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

90
arch/arm64/boot/dts/qcom/sdx75.dtsi
View File

@ -43,25 +43,25 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -69,85 +69,85 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
};
@ -155,7 +155,7 @@ core3 {
idle-states {
entry-method = "psci";
CPU_OFF: cpu-sleep-0 {
cpu_off: cpu-sleep-0 {
compatible = "arm,idle-state";
entry-latency-us = <235>;
exit-latency-us = <428>;
@ -164,7 +164,7 @@ CPU_OFF: cpu-sleep-0 {
local-timer-stop;
};
CPU_RAIL_OFF: cpu-rail-sleep-1 {
cpu_rail_off: cpu-rail-sleep-1 {
compatible = "arm,idle-state";
entry-latency-us = <800>;
exit-latency-us = <750>;
@ -176,7 +176,7 @@ CPU_RAIL_OFF: cpu-rail-sleep-1 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <1050>;
@ -184,7 +184,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
min-residency-us = <5309>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41001344>;
entry-latency-us = <2761>;
@ -192,7 +192,7 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
min-residency-us = <8467>;
};
CLUSTER_SLEEP_2: cluster-sleep-2 {
cluster_sleep_2: cluster-sleep-2 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100b344>;
entry-latency-us = <2793>;
@ -235,33 +235,33 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off &cpu_rail_off>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off &cpu_rail_off>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off &cpu_rail_off>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
power-domains = <&cluster_pd>;
domain-idle-states = <&cpu_off &cpu_rail_off>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
domain-idle-states = <&cluster_sleep_0 &cluster_sleep_1 &cluster_sleep_2>;
};
};
@ -1444,7 +1444,7 @@ apps_rsc: rsc@17a00000 {
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 3>,

16
arch/arm64/boot/dts/qcom/sm4250.dtsi
View File

@ -5,34 +5,34 @@
#include "sm6115.dtsi"
&CPU0 {
&cpu0 {
compatible = "qcom,kryo240";
};
&CPU1 {
&cpu1 {
compatible = "qcom,kryo240";
};
&CPU2 {
&cpu2 {
compatible = "qcom,kryo240";
};
&CPU3 {
&cpu3 {
compatible = "qcom,kryo240";
};
&CPU4 {
&cpu4 {
compatible = "qcom,kryo240";
};
&CPU5 {
&cpu5 {
compatible = "qcom,kryo240";
};
&CPU6 {
&cpu6 {
compatible = "qcom,kryo240";
};
&CPU7 {
&cpu7 {
compatible = "qcom,kryo240";
};

160
arch/arm64/boot/dts/qcom/sm4450.dtsi
View File

@ -46,25 +46,25 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
L3_0: l3-cache {
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -72,178 +72,178 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_100>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_200>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_300>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_400>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_500>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_600>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_700>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -251,7 +251,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <800>;
@ -260,7 +260,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <600>;
@ -271,7 +271,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <1050>;
@ -279,7 +279,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
min-residency-us = <5309>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41003344>;
entry-latency-us = <1561>;
@ -309,57 +309,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
};
};
@ -579,7 +579,7 @@ apps_rsc: rsc@17a00000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 0>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

154
arch/arm64/boot/dts/qcom/sm6115.dtsi
View File

@ -40,7 +40,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x0>;
@ -48,18 +48,18 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x1>;
@ -67,13 +67,13 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x2>;
@ -81,13 +81,13 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x3>;
@ -95,13 +95,13 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
};
CPU4: cpu@100 {
cpu4: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x100>;
@ -109,18 +109,18 @@ CPU4: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
L2_1: l2-cache {
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU5: cpu@101 {
cpu5: cpu@101 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x101>;
@ -128,13 +128,13 @@ CPU5: cpu@101 {
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
enable-method = "psci";
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
};
CPU6: cpu@102 {
cpu6: cpu@102 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x102>;
@ -142,13 +142,13 @@ CPU6: cpu@102 {
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
enable-method = "psci";
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
};
CPU7: cpu@103 {
cpu7: cpu@103 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x103>;
@ -156,46 +156,46 @@ CPU7: cpu@103 {
capacity-dmips-mhz = <1638>;
dynamic-power-coefficient = <282>;
enable-method = "psci";
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -203,7 +203,7 @@ core3 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -213,7 +213,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -225,7 +225,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
cluster_0_sleep_0: cluster-sleep-0-0 {
/* GDHS */
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x40000022>;
@ -234,7 +234,7 @@ CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
min-residency-us = <782>;
};
CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
cluster_0_sleep_1: cluster-sleep-0-1 {
/* Power Collapse */
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
@ -243,7 +243,7 @@ CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
min-residency-us = <7376>;
};
CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
cluster_1_sleep_0: cluster-sleep-1-0 {
/* GDHS */
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x40000042>;
@ -252,7 +252,7 @@ CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
min-residency-us = <660>;
};
CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
cluster_1_sleep_1: cluster-sleep-1-1 {
/* Power Collapse */
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
@ -306,62 +306,62 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_0_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_0_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_0_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_0_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_1_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_1_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_1_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_1_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_0_PD: power-domain-cpu-cluster0 {
cluster_0_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>;
};
CLUSTER_1_PD: power-domain-cpu-cluster1 {
cluster_1_pd: power-domain-cpu-cluster1 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>;
};
};
@ -1178,7 +1178,7 @@ opp-202000000 {
};
};
ufs_mem_hc: ufs@4804000 {
ufs_mem_hc: ufshc@4804000 {
compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
reg-names = "std", "ice";
@ -2405,7 +2405,7 @@ etm@9040000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU0>;
cpu = <&cpu0>;
status = "disabled";
@ -2426,7 +2426,7 @@ etm@9140000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU1>;
cpu = <&cpu1>;
status = "disabled";
@ -2447,7 +2447,7 @@ etm@9240000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU2>;
cpu = <&cpu2>;
status = "disabled";
@ -2468,7 +2468,7 @@ etm@9340000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU3>;
cpu = <&cpu3>;
status = "disabled";
@ -2489,7 +2489,7 @@ etm@9440000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU4>;
cpu = <&cpu4>;
status = "disabled";
@ -2510,7 +2510,7 @@ etm@9540000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU5>;
cpu = <&cpu5>;
status = "disabled";
@ -2531,7 +2531,7 @@ etm@9640000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU6>;
cpu = <&cpu6>;
status = "disabled";
@ -2552,7 +2552,7 @@ etm@9740000 {
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
cpu = <&CPU7>;
cpu = <&cpu7>;
status = "disabled";

54
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@ -37,122 +37,122 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x3>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
};
CPU4: cpu@100 {
cpu4: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1638>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&l2_1>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU5: cpu@101 {
cpu5: cpu@101 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1638>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
CPU6: cpu@102 {
cpu6: cpu@102 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1638>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
CPU7: cpu@103 {
cpu7: cpu@103 {
device_type = "cpu";
compatible = "qcom,kryo260";
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1638>;
next-level-cache = <&L2_1>;
next-level-cache = <&l2_1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -763,7 +763,7 @@ sdhc_2: mmc@4784000 {
status = "disabled";
};
ufs_mem_hc: ufs@4804000 {
ufs_mem_hc: ufshc@4804000 {
compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
reg-names = "std", "ice";

207
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -45,7 +45,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x0>;
@ -53,21 +53,21 @@ CPU0: cpu@0 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -75,7 +75,7 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x100>;
@ -83,24 +83,24 @@ CPU1: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x200>;
@ -108,24 +108,24 @@ CPU2: cpu@200 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x300>;
@ -133,24 +133,24 @@ CPU3: cpu@300 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x400>;
@ -158,24 +158,24 @@ CPU4: cpu@400 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x500>;
@ -183,24 +183,24 @@ CPU5: cpu@500 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x600>;
@ -208,24 +208,24 @@ CPU6: cpu@600 {
enable-method = "psci";
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x700>;
@ -233,61 +233,61 @@ CPU7: cpu@700 {
enable-method = "psci";
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
domain-idle-states {
CLUSTER_SLEEP_PC: cluster-sleep-0 {
cluster_sleep_pc: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
@ -295,7 +295,7 @@ CLUSTER_SLEEP_PC: cluster-sleep-0 {
min-residency-us = <6118>;
};
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
cluster_sleep_cx_ret: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41001244>;
entry-latency-us = <3638>;
@ -303,7 +303,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
min-residency-us = <8467>;
};
CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
cluster_aoss_sleep: cluster-sleep-2 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100b244>;
entry-latency-us = <3263>;
@ -315,7 +315,7 @@ CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
cpu_idle_states: idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -325,7 +325,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -335,7 +335,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -345,7 +345,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -504,59 +504,59 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_PC
&CLUSTER_SLEEP_CX_RET
&CLUSTER_AOSS_SLEEP>;
domain-idle-states = <&cluster_sleep_pc
&cluster_sleep_cx_ret
&cluster_aoss_sleep>;
};
};
@ -1136,7 +1136,7 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
ufs_mem_hc: ufs@1d84000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>,
@ -1376,43 +1376,43 @@ gpu_opp_table: opp-table {
opp-850000000 {
opp-hz = /bits/ 64 <850000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-supported-hw = <0x02>;
opp-supported-hw = <0x03>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-supported-hw = <0x04>;
opp-supported-hw = <0x07>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-supported-hw = <0x08>;
opp-supported-hw = <0x0f>;
};
opp-565000000 {
opp-hz = /bits/ 64 <565000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-supported-hw = <0x10>;
opp-supported-hw = <0x1f>;
};
opp-430000000 {
opp-hz = /bits/ 64 <430000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-supported-hw = <0xff>;
opp-supported-hw = <0x1f>;
};
opp-355000000 {
opp-hz = /bits/ 64 <355000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-supported-hw = <0xff>;
opp-supported-hw = <0x1f>;
};
opp-253000000 {
opp-hz = /bits/ 64 <253000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-supported-hw = <0xff>;
opp-supported-hw = <0x1f>;
};
};
};
@ -2685,6 +2685,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
intc: interrupt-controller@17a00000 {
@ -2776,7 +2777,7 @@ apps_rsc: rsc@18200000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
rpmhcc: clock-controller {
compatible = "qcom,sm6350-rpmh-clk";
@ -2953,7 +2954,7 @@ cpu0-crit {
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -2978,7 +2979,7 @@ cpu1-crit {
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3003,7 +3004,7 @@ cpu2-crit {
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3028,7 +3029,7 @@ cpu3-crit {
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3053,7 +3054,7 @@ cpu4-crit {
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3078,7 +3079,7 @@ cpu5-crit {
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3103,7 +3104,7 @@ cpu6-left-crit {
cooling-maps {
map0 {
trip = <&cpu6_left_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3128,7 +3129,7 @@ cpu6-right-crit {
cooling-maps {
map0 {
trip = <&cpu6_right_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3153,7 +3154,7 @@ cpu7-left-crit {
cooling-maps {
map0 {
trip = <&cpu7_left_alert0>;
cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3178,7 +3179,7 @@ cpu7-right-crit {
cooling-maps {
map0 {
trip = <&cpu7_right_alert0>;
cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

160
arch/arm64/boot/dts/qcom/sm6375.dtsi
View File

@ -38,25 +38,25 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -64,185 +64,185 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo660";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -250,7 +250,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -260,7 +260,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -270,7 +270,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@ -280,7 +280,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -292,7 +292,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
@ -455,58 +455,58 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
power-domains = <&mpm>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&cluster_sleep_0>;
};
};

16
arch/arm64/boot/dts/qcom/sm7125.dtsi
View File

@ -6,11 +6,11 @@
#include "sc7180.dtsi"
/* SM7125 uses Kryo 465 instead of Kryo 468 */
&CPU0 { compatible = "qcom,kryo465"; };
&CPU1 { compatible = "qcom,kryo465"; };
&CPU2 { compatible = "qcom,kryo465"; };
&CPU3 { compatible = "qcom,kryo465"; };
&CPU4 { compatible = "qcom,kryo465"; };
&CPU5 { compatible = "qcom,kryo465"; };
&CPU6 { compatible = "qcom,kryo465"; };
&CPU7 { compatible = "qcom,kryo465"; };
&cpu0 { compatible = "qcom,kryo465"; };
&cpu1 { compatible = "qcom,kryo465"; };
&cpu2 { compatible = "qcom,kryo465"; };
&cpu3 { compatible = "qcom,kryo465"; };
&cpu4 { compatible = "qcom,kryo465"; };
&cpu5 { compatible = "qcom,kryo465"; };
&cpu6 { compatible = "qcom,kryo465"; };
&cpu7 { compatible = "qcom,kryo465"; };

16
arch/arm64/boot/dts/qcom/sm7225.dtsi
View File

@ -6,14 +6,14 @@
#include "sm6350.dtsi"
/* SM7225 uses Kryo 570 instead of Kryo 560 */
&CPU0 { compatible = "qcom,kryo570"; };
&CPU1 { compatible = "qcom,kryo570"; };
&CPU2 { compatible = "qcom,kryo570"; };
&CPU3 { compatible = "qcom,kryo570"; };
&CPU4 { compatible = "qcom,kryo570"; };
&CPU5 { compatible = "qcom,kryo570"; };
&CPU6 { compatible = "qcom,kryo570"; };
&CPU7 { compatible = "qcom,kryo570"; };
&cpu0 { compatible = "qcom,kryo570"; };
&cpu1 { compatible = "qcom,kryo570"; };
&cpu2 { compatible = "qcom,kryo570"; };
&cpu3 { compatible = "qcom,kryo570"; };
&cpu4 { compatible = "qcom,kryo570"; };
&cpu5 { compatible = "qcom,kryo570"; };
&cpu6 { compatible = "qcom,kryo570"; };
&cpu7 { compatible = "qcom,kryo570"; };
&cpu0_opp_table {
opp-1804800000 {

1260
arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts Normal file
View File

File diff suppressed because it is too large Load Diff

17
arch/arm64/boot/dts/qcom/sm7325.dtsi Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Eugene Lepshy <fekz115@gmail.com>
* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
*/
#include "sc7280.dtsi"
/* SM7325 uses Kryo 670 */
&cpu0 { compatible = "qcom,kryo670"; };
&cpu1 { compatible = "qcom,kryo670"; };
&cpu2 { compatible = "qcom,kryo670"; };
&cpu3 { compatible = "qcom,kryo670"; };
&cpu4 { compatible = "qcom,kryo670"; };
&cpu5 { compatible = "qcom,kryo670"; };
&cpu6 { compatible = "qcom,kryo670"; };
&cpu7 { compatible = "qcom,kryo670"; };

371
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -48,7 +48,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
@ -56,20 +56,20 @@ CPU0: cpu@0 {
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -77,7 +77,7 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
@ -85,23 +85,23 @@ CPU1: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
@ -109,23 +109,23 @@ CPU2: cpu@200 {
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
@ -133,23 +133,23 @@ CPU3: cpu@300 {
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
@ -157,23 +157,23 @@ CPU4: cpu@400 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
@ -181,23 +181,23 @@ CPU5: cpu@500 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
@ -205,23 +205,23 @@ CPU6: cpu@600 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
@ -229,54 +229,54 @@ CPU7: cpu@700 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <421>;
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -284,7 +284,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -294,7 +294,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -306,7 +306,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3263>;
@ -628,57 +628,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&cluster_sleep_0>;
};
};
@ -3096,7 +3096,7 @@ etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3116,7 +3116,7 @@ etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3136,7 +3136,7 @@ etm@7240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07240000 0 0x1000>;
cpu = <&CPU2>;
cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3156,7 +3156,7 @@ etm@7340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07340000 0 0x1000>;
cpu = <&CPU3>;
cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3176,7 +3176,7 @@ etm@7440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07440000 0 0x1000>;
cpu = <&CPU4>;
cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3196,7 +3196,7 @@ etm@7540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07540000 0 0x1000>;
cpu = <&CPU5>;
cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3216,7 +3216,7 @@ etm@7640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07640000 0 0x1000>;
cpu = <&CPU6>;
cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3236,7 +3236,7 @@ etm@7740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -4296,6 +4296,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
remoteproc_adsp: remoteproc@17300000 {
@ -4457,7 +4458,7 @@ apps_rsc: rsc@18200000 {
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
rpmhcc: clock-controller {
compatible = "qcom,sm8150-rpmh-clk";
@ -4553,7 +4554,7 @@ lmh_cluster1: lmh@18350800 {
compatible = "qcom,sm8150-lmh";
reg = <0 0x18350800 0 0x400>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU4>;
cpus = <&cpu4>;
qcom,lmh-temp-arm-millicelsius = <60000>;
qcom,lmh-temp-low-millicelsius = <84500>;
qcom,lmh-temp-high-millicelsius = <85000>;
@ -4565,7 +4566,7 @@ lmh_cluster0: lmh@18358800 {
compatible = "qcom,sm8150-lmh";
reg = <0 0x18358800 0 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU0>;
cpus = <&cpu0>;
qcom,lmh-temp-arm-millicelsius = <60000>;
qcom,lmh-temp-low-millicelsius = <84500>;
qcom,lmh-temp-high-millicelsius = <85000>;
@ -4634,17 +4635,17 @@ cpu0_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4677,17 +4678,17 @@ cpu1_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4720,17 +4721,17 @@ cpu2_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4763,17 +4764,17 @@ cpu3_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4806,17 +4807,17 @@ cpu4_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4849,17 +4850,17 @@ cpu5_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4892,17 +4893,17 @@ cpu6_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4935,17 +4936,17 @@ cpu7_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4978,17 +4979,17 @@ cpu4_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -5021,17 +5022,17 @@ cpu5_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -5064,17 +5065,17 @@ cpu6_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -5107,17 +5108,17 @@ cpu7_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

366
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -93,7 +93,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
@ -101,21 +101,21 @@ CPU0: cpu@0 {
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-size = <0x400000>;
@ -124,7 +124,7 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
@ -132,24 +132,24 @@ CPU1: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
next-level-cache = <&l2_100>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
@ -157,24 +157,24 @@ CPU2: cpu@200 {
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
next-level-cache = <&l2_200>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
@ -182,24 +182,24 @@ CPU3: cpu@300 {
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
next-level-cache = <&l2_300>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
@ -207,24 +207,24 @@ CPU4: cpu@400 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD4>;
next-level-cache = <&l2_400>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
@ -232,24 +232,24 @@ CPU5: cpu@500 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD5>;
next-level-cache = <&l2_500>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
@ -257,24 +257,24 @@ CPU6: cpu@600 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD6>;
next-level-cache = <&l2_600>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
@ -282,55 +282,55 @@ CPU7: cpu@700 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <444>;
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD7>;
next-level-cache = <&l2_700>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -338,7 +338,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -348,7 +348,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -360,7 +360,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3264>;
@ -689,57 +689,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&cluster_sleep_0>;
};
};
@ -3522,7 +3522,7 @@ etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3541,7 +3541,7 @@ etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3560,7 +3560,7 @@ etm@7240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07240000 0 0x1000>;
cpu = <&CPU2>;
cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3579,7 +3579,7 @@ etm@7340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07340000 0 0x1000>;
cpu = <&CPU3>;
cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3598,7 +3598,7 @@ etm@7440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07440000 0 0x1000>;
cpu = <&CPU4>;
cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3617,7 +3617,7 @@ etm@7540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07540000 0 0x1000>;
cpu = <&CPU5>;
cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3636,7 +3636,7 @@ etm@7640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07640000 0 0x1000>;
cpu = <&CPU6>;
cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -3655,7 +3655,7 @@ etm@7740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@ -6165,7 +6165,7 @@ apps_rsc: rsc@18200000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
rpmhcc: clock-controller {
compatible = "qcom,sm8250-rpmh-clk";
@ -6302,17 +6302,17 @@ cpu0_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6345,17 +6345,17 @@ cpu1_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6388,17 +6388,17 @@ cpu2_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6431,17 +6431,17 @@ cpu3_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6474,17 +6474,17 @@ cpu4_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6517,17 +6517,17 @@ cpu5_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6560,17 +6560,17 @@ cpu6_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6603,17 +6603,17 @@ cpu7_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6646,17 +6646,17 @@ cpu4_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6689,17 +6689,17 @@ cpu5_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6732,17 +6732,17 @@ cpu6_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -6775,17 +6775,17 @@ cpu7_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

4
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
View File

@ -382,10 +382,6 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
&dispcc {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&vreg_l6b_1p2>;
status = "okay";

353
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -51,23 +51,23 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -75,171 +75,171 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x1";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 2>;
enable-method = "psci";
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -247,7 +247,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -257,7 +257,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -269,7 +269,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
cluster_sleep_apss_off: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
@ -277,7 +277,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
min-residency-us = <6118>;
};
CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
cluster_sleep_aoss_sleep: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <3263>;
@ -320,57 +320,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
};
};
@ -3282,6 +3282,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
adsp: remoteproc@17300000 {
@ -3504,7 +3505,7 @@ apps_rsc: rsc@18200000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 0>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
rpmhcc: clock-controller {
compatible = "qcom,sm8350-rpmh-clk";
@ -3728,17 +3729,17 @@ cpu0_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3771,17 +3772,17 @@ cpu1_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3814,17 +3815,17 @@ cpu2_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3857,17 +3858,17 @@ cpu3_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3900,17 +3901,17 @@ cpu4_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3943,17 +3944,17 @@ cpu5_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -3986,17 +3987,17 @@ cpu6_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4029,17 +4030,17 @@ cpu7_top_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4072,17 +4073,17 @@ cpu4_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu4_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4115,17 +4116,17 @@ cpu5_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu5_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4158,17 +4159,17 @@ cpu6_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu6_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -4201,17 +4202,17 @@ cpu7_bottom_crit: cpu-crit {
cooling-maps {
map0 {
trip = <&cpu7_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

161
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
View File

@ -26,6 +26,7 @@ / {
aliases {
serial0 = &uart7;
serial1 = &uart20;
};
wcd938x: audio-codec {
@ -247,6 +248,71 @@ active-config0 {
};
};
wcn6855-pmu {
compatible = "qcom,wcn6855-pmu";
pinctrl-0 = <&bt_en>, <&wlan_en>, <&xo_clk_default>;
pinctrl-names = "default";
wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>;
vddio-supply = <&vreg_s10b_1p8>;
vddaon-supply = <&vreg_s11b_0p95>;
vddpmu-supply = <&vreg_s12b_1p25>;
vddpmumx-supply = <&vreg_s2e_0p85>;
vddpmucx-supply = <&vreg_s11b_0p95>;
vddrfa0p95-supply = <&vreg_s11b_0p95>;
vddrfa1p3-supply = <&vreg_s12b_1p25>;
vddrfa1p9-supply = <&vreg_s1c_1p86>;
vddpcie1p3-supply = <&vreg_s12b_1p25>;
vddpcie1p9-supply = <&vreg_s1c_1p86>;
regulators {
vreg_pmu_rfa_cmn_0p8: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn_0p8";
};
vreg_pmu_aon_0p8: ldo1 {
regulator-name = "vreg_pmu_aon_0p8";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p8: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p8";
};
vreg_pmu_btcmx_0p8: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p8";
};
vreg_pmu_pcie_1p8: ldo5 {
regulator-name = "vreg_pmu_pcie_1p8";
};
vreg_pmu_pcie_0p9: ldo6 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_rfa_0p8: ldo7 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo8 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo9 {
regulator-name = "vreg_pmu_rfa_1p7";
};
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@ -575,10 +641,6 @@ vreg_l7e_2p8: ldo7 {
};
};
&dispcc {
status = "okay";
};
&gpu {
status = "okay";
@ -689,6 +751,23 @@ &pcie0_phy {
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&pcieport0 {
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
};
};
&pcie1 {
status = "okay";
};
@ -896,6 +975,10 @@ &qupv3_id_1 {
status = "okay";
};
&qupv3_id_2 {
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
@ -1073,6 +1156,26 @@ &uart7 {
status = "okay";
};
&uart20 {
pinctrl-0 = <&uart20_default>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "qcom,wcn6855-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
};
};
&ufs_mem_hc {
status = "okay";
@ -1134,6 +1237,14 @@ &vamacro {
};
&tlmm {
bt_en: bt-en-state {
pins = "gpio81";
function = "gpio";
drive-strength = <16>;
output-low;
bias-pull-down;
};
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio1";
function = "gpio";
@ -1157,4 +1268,46 @@ wcd_default: wcd-reset-n-active-state {
bias-disable;
output-low;
};
wlan_en: wlan-en-state {
pins = "gpio80";
function = "gpio";
drive-strength = <16>;
output-low;
bias-pull-down;
};
uart20_default: uart20-default-state {
cts-pins {
pins = "gpio76";
function = "qup20";
bias-disable;
};
rts-pins {
pins = "gpio77";
function = "qup20";
bias-disable;
};
rx-pins {
pins = "gpio78";
function = "qup20";
bias-disable;
};
tx-pins {
pins = "gpio79";
function = "qup20";
bias-disable;
};
};
xo_clk_default: xo-clk-state {
pins = "gpio204";
function = "gpio";
drive-strength = <16>;
output-low;
bias-pull-down;
};
};

4
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
View File

@ -349,6 +349,10 @@ vreg_l6e_1p2: ldo6 {
};
};
&dispcc {
status = "disabled";
};
&pcie0 {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
View File

@ -468,6 +468,10 @@ pmr735a_l7: ldo7 {
};
};
&dispcc {
status = "disabled";
};
&gpi_dma0 {
status = "okay";
};

176
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -51,23 +51,23 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -75,171 +75,171 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
next-level-cache = <&l2_100>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
next-level-cache = <&l2_200>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
next-level-cache = <&l2_300>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD4>;
next-level-cache = <&l2_400>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD5>;
next-level-cache = <&l2_500>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD6>;
next-level-cache = <&l2_600>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo780";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD7>;
next-level-cache = <&l2_700>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -247,7 +247,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -257,7 +257,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -269,7 +269,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <1050>;
@ -277,7 +277,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
min-residency-us = <5309>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2700>;
@ -323,57 +323,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
};
};
@ -1787,7 +1787,8 @@ pcie0: pcie@1c00000 {
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -1795,7 +1796,8 @@ pcie0: pcie@1c00000 {
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1880,7 +1882,7 @@ opp-8000000 {
};
};
pcie@0 {
pcieport0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@ -1949,7 +1951,8 @@ pcie1: pcie@1c08000 {
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -1957,7 +1960,8 @@ pcie1: pcie@1c08000 {
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -3435,7 +3439,6 @@ dispcc: clock-controller@af00000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
status = "disabled";
};
pdc: interrupt-controller@b220000 {
@ -4257,6 +4260,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
intc: interrupt-controller@17100000 {
@ -4354,7 +4358,7 @@ apps_rsc: rsc@17a00000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
<WAKE_TCS 2>, <CONTROL_TCS 0>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

2
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
View File

@ -98,7 +98,7 @@ rmtfs_mem: rmtfs-region@d4a80000 {
* The bootloader will only keep display hardware enabled
* if this memory region is named exactly 'splash_region'
*/
splash_region@b8000000 {
splash-region@b8000000 {
reg = <0x0 0xb8000000 0x0 0x2b00000>;
no-map;
};

167
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@ -64,25 +64,25 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0 0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -90,185 +90,185 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
next-level-cache = <&l2_100>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
next-level-cache = <&l2_200>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a715";
reg = <0 0x300>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
next-level-cache = <&l2_300>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a715";
reg = <0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD4>;
next-level-cache = <&l2_400>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a710";
reg = <0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD5>;
next-level-cache = <&l2_500>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a710";
reg = <0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD6>;
next-level-cache = <&l2_600>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x3";
reg = <0 0x700>;
clocks = <&cpufreq_hw 2>;
enable-method = "psci";
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD7>;
next-level-cache = <&l2_700>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -276,7 +276,7 @@ core7 {
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -286,7 +286,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -296,7 +296,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
prime_cpu_sleep_0: cpu-sleep-2-0 {
compatible = "arm,idle-state";
idle-state-name = "goldplus-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -308,7 +308,7 @@ PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <750>;
@ -316,7 +316,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
min-residency-us = <9144>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2800>;
@ -376,57 +376,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&PRIME_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&prime_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
};
};
@ -1989,7 +1989,7 @@ ufs_mem_phy: phy@1d80000 {
status = "disabled";
};
ufs_mem_hc: ufs@1d84000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
@ -2076,7 +2076,8 @@ opp-300000000 {
ice: crypto@1d88000 {
compatible = "qcom,sm8550-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0 0x01d88000 0 0x8000>;
reg = <0 0x01d88000 0 0x18000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
@ -4365,7 +4366,7 @@ apps_rsc: rsc@17a00000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
<WAKE_TCS 2>, <CONTROL_TCS 0>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

4
arch/arm64/boot/dts/qcom/sm8650-hdk.dts
View File

@ -814,10 +814,6 @@ vreg_l7n_3p3: ldo7 {
};
};
&dispcc {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sm8650-mtp.dts
View File

@ -585,10 +585,6 @@ vreg_l7n_3p3: ldo7 {
};
};
&dispcc {
status = "okay";
};
&lpass_tlmm {
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio21";

4
arch/arm64/boot/dts/qcom/sm8650-qrd.dts
View File

@ -741,10 +741,6 @@ vreg_l7n_3p3: ldo7 {
};
};
&dispcc {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};

162
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@ -68,18 +68,18 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a520";
reg = <0 0>;
clocks = <&cpufreq_hw 0>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@ -87,13 +87,13 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
L3_0: l3-cache {
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@ -101,18 +101,18 @@ L3_0: l3-cache {
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a520";
reg = <0 0x100>;
clocks = <&cpufreq_hw 0>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@ -121,18 +121,18 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x200>;
clocks = <&cpufreq_hw 3>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@ -140,26 +140,26 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x300>;
clocks = <&cpufreq_hw 3>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@ -168,18 +168,18 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x400>;
clocks = <&cpufreq_hw 3>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@ -187,26 +187,26 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x500>;
clocks = <&cpufreq_hw 1>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@ -214,26 +214,26 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x600>;
clocks = <&cpufreq_hw 1>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@ -241,26 +241,26 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x4";
reg = <0 0x700>;
clocks = <&cpufreq_hw 2>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
@ -268,46 +268,46 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@ -315,7 +315,7 @@ core7 {
idle-states {
entry-method = "psci";
SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
silver_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -325,7 +325,7 @@ SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
gold_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -335,7 +335,7 @@ GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-plus-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -347,7 +347,7 @@ GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <750>;
@ -355,7 +355,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
min-residency-us = <9144>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2800>;
@ -411,58 +411,58 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&SILVER_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&silver_cpu_sleep_0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&SILVER_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&silver_cpu_sleep_0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&SILVER_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&silver_cpu_sleep_0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&GOLD_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&GOLD_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&GOLD_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&GOLD_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_plus_cpu_sleep_0>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>,
<&CLUSTER_SLEEP_1>;
domain-idle-states = <&cluster_sleep_0>,
<&cluster_sleep_1>;
};
};
@ -2535,7 +2535,7 @@ ufs_mem_phy: phy@1d80000 {
status = "disabled";
};
ufs_mem_hc: ufs@1d84000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
@ -2595,7 +2595,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
ice: crypto@1d88000 {
compatible = "qcom,sm8650-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0 0x01d88000 0 0x8000>;
reg = <0 0x01d88000 0 0x18000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
@ -3841,8 +3841,6 @@ dispcc: clock-controller@af00000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
status = "disabled";
};
usb_1_hsphy: phy@88e3000 {
@ -5083,7 +5081,7 @@ apps_rsc: rsc@17a00000 {
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;

25
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
View File

@ -451,6 +451,9 @@ zap-shader {
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c0_data_clk>, <&tpad_default>;
pinctrl-names = "default";
status = "okay";
/* ELAN06E2 or ELAN06E3 */
@ -461,13 +464,19 @@ touchpad@15 {
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&tpad_default>;
pinctrl-names = "default";
wakeup-source;
};
/* TODO: second-sourced SYNA8022 or SYNA8024 touchpad @ 0x2c */
/* SYNA8022 or SYNA8024 */
touchpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
/* ELAN06F1 or SYNA06F2 */
keyboard@3a {
@ -762,10 +771,6 @@ &usb_1_ss0 {
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "host";
};
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
@ -794,10 +799,6 @@ &usb_1_ss1 {
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "host";
};
&usb_1_ss1_dwc3_hs {
remote-endpoint = <&pmic_glink_ss1_hs_in>;
};

26
arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts
View File

@ -94,17 +94,6 @@ linux,cma {
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
@ -135,6 +124,17 @@ vreg_nvme: regulator-nvme {
pinctrl-0 = <&nvme_reg_en>;
pinctrl-names = "default";
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
@ -592,8 +592,6 @@ &usb_1_ss0_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l1j_0p8>;
orientation-switch;
status = "okay";
};
@ -626,8 +624,6 @@ &usb_1_ss1_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
orientation-switch;
status = "okay";
};

74
arch/arm64/boot/dts/qcom/x1e80100-crd.dts
View File

@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "x1e80100.dtsi"
@ -261,17 +262,6 @@ platform {
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
@ -288,6 +278,23 @@ vreg_edp_3p3: regulator-edp-3p3 {
regulator-boot-on;
};
vreg_misc_3p3: regulator-misc-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_MISC_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&misc_3p3_reg_en>;
regulator-boot-on;
regulator-always-on;
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
@ -302,6 +309,17 @@ vreg_nvme: regulator-nvme {
pinctrl-0 = <&nvme_reg_en>;
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
vreg_wwan: regulator-wwan {
compatible = "regulator-fixed";
@ -689,6 +707,9 @@ touchpad@15 {
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l12b_1p2>;
pinctrl-0 = <&tpad_default>;
pinctrl-names = "default";
@ -702,6 +723,9 @@ keyboard@3a {
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l12b_1p2>;
pinctrl-0 = <&kybd_default>;
pinctrl-names = "default";
@ -721,6 +745,9 @@ touchscreen@10 {
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_1p8>;
pinctrl-0 = <&ts0_default>;
pinctrl-names = "default";
};
@ -854,6 +881,19 @@ &pcie6a_phy {
status = "okay";
};
&pm8550ve_8_gpios {
misc_3p3_reg_en: misc-3p3-reg-en-state {
pins = "gpio6";
function = "normal";
bias-disable;
input-disable;
output-enable;
drive-push-pull;
power-source = <1>; /* 1.8 V */
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
};
&pmc8380_3_gpios {
edp_bl_en: edp-bl-en-state {
pins = "gpio4";
@ -1155,10 +1195,6 @@ &usb_1_ss0 {
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "host";
};
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
@ -1187,10 +1223,6 @@ &usb_1_ss1 {
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "host";
};
&usb_1_ss1_dwc3_hs {
remote-endpoint = <&pmic_glink_ss1_hs_in>;
};
@ -1219,10 +1251,6 @@ &usb_1_ss2 {
status = "okay";
};
&usb_1_ss2_dwc3 {
dr_mode = "host";
};
&usb_1_ss2_dwc3_hs {
remote-endpoint = <&pmic_glink_ss2_hs_in>;
};

875
arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts Normal file
View File

@ -0,0 +1,875 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024 Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "x1e80100.dtsi"
#include "x1e80100-pmics.dtsi"
/ {
model = "Dell XPS 13 9345";
compatible = "dell,xps13-9345", "qcom,x1e80100";
chassis-type = "laptop";
aliases {
serial0 = &uart21;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&hall_int_n_default>;
pinctrl-names = "default";
switch-lid {
gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
wakeup-event-action = <EV_ACT_DEASSERTED>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&cam_indicator_en>;
led-camera-indicator {
label = "white:camera-indicator";
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
/* Reuse as a panic indicator until we get a "camera on" trigger */
panic-indicator;
};
};
pmic-glink {
compatible = "qcom,x1e80100-pmic-glink",
"qcom,sm8550-pmic-glink",
"qcom,pmic-glink";
orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
<&tlmm 123 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/* Right-side USB Type-C port */
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_ss0_hs_in: endpoint {
remote-endpoint = <&usb_1_ss0_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss0_ss_in: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
};
};
};
};
/* Left-side USB Type-C port */
connector@1 {
compatible = "usb-c-connector";
reg = <1>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_ss1_hs_in: endpoint {
remote-endpoint = <&usb_1_ss1_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss1_ss_in: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
};
};
};
};
};
reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
reusable;
linux,cma-default;
};
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_EDP_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
regulator-name = "VREG_NVME_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&nvme_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8550-rpmh-regulators";
qcom,pmic-id = "b";
vdd-bob1-supply = <&vreg_vph_pwr>;
vdd-bob2-supply = <&vreg_vph_pwr>;
vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
vdd-l2-l13-l14-supply = <&vreg_bob1>;
vdd-l5-l16-supply = <&vreg_bob1>;
vdd-l6-l7-supply = <&vreg_bob2>;
vdd-l8-l9-supply = <&vreg_bob1>;
vdd-l12-supply = <&vreg_s5j_1p2>;
vdd-l15-supply = <&vreg_s4c_1p8>;
vdd-l17-supply = <&vreg_bob2>;
vreg_bob1: bob1 {
regulator-name = "vreg_bob1";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob2: bob2 {
regulator-name = "vreg_bob2";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p0: ldo2 {
regulator-name = "vreg_l2b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4b_1p8: ldo4 {
regulator-name = "vreg_l4b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p8: ldo6 {
regulator-name = "vreg_l6b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8b_3p0: ldo8 {
regulator-name = "vreg_l8b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_2p9: ldo9 {
regulator-name = "vreg_l9b_2p9";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b_1p2: ldo12 {
regulator-name = "vreg_l12b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13b_3p0: ldo13 {
regulator-name = "vreg_l13b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14b_3p0: ldo14 {
regulator-name = "vreg_l14b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b_1p8: ldo15 {
regulator-name = "vreg_l15b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b_2p5: ldo17 {
regulator-name = "vreg_l17b_2p5";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pm8550ve-rpmh-regulators";
qcom,pmic-id = "c";
vdd-l1-supply = <&vreg_s5j_1p2>;
vdd-l2-supply = <&vreg_s1f_0p7>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vreg_s4c_1p8: smps4 {
regulator-name = "vreg_s4c_1p8";
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c_1p2: ldo1 {
regulator-name = "vreg_l1c_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_0p8: ldo2 {
regulator-name = "vreg_l2c_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_0p9: ldo3 {
regulator-name = "vreg_l3c_0p9";
regulator-min-microvolt = <920000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pmc8380-rpmh-regulators";
qcom,pmic-id = "d";
vdd-l1-supply = <&vreg_s1f_0p7>;
vdd-l2-supply = <&vreg_s1f_0p7>;
vdd-l3-supply = <&vreg_s4c_1p8>;
vdd-s1-supply = <&vreg_vph_pwr>;
vreg_l1d_0p8: ldo1 {
regulator-name = "vreg_l1d_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2d_0p9: ldo2 {
regulator-name = "vreg_l2d_0p9";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3d_1p8: ldo3 {
regulator-name = "vreg_l3d_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-3 {
compatible = "qcom,pmc8380-rpmh-regulators";
qcom,pmic-id = "e";
vdd-l2-supply = <&vreg_s1f_0p7>;
vdd-l3-supply = <&vreg_s5j_1p2>;
vreg_l2e_0p8: ldo2 {
regulator-name = "vreg_l2e_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3e_1p2: ldo3 {
regulator-name = "vreg_l3e_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-4 {
compatible = "qcom,pmc8380-rpmh-regulators";
qcom,pmic-id = "f";
vdd-l1-supply = <&vreg_s5j_1p2>;
vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s5j_1p2>;
vdd-s1-supply = <&vreg_vph_pwr>;
vreg_s1f_0p7: smps1 {
regulator-name = "vreg_s1f_0p7";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-6 {
compatible = "qcom,pm8550ve-rpmh-regulators";
qcom,pmic-id = "i";
vdd-l1-supply = <&vreg_s4c_1p8>;
vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s1-supply = <&vreg_vph_pwr>;
vdd-s2-supply = <&vreg_vph_pwr>;
vreg_s1i_0p9: smps1 {
regulator-name = "vreg_s1i_0p9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s2i_1p0: smps2 {
regulator-name = "vreg_s2i_1p0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1i_1p8: ldo1 {
regulator-name = "vreg_l1i_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2i_1p2: ldo2 {
regulator-name = "vreg_l2i_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3i_0p8: ldo3 {
regulator-name = "vreg_l3i_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-7 {
compatible = "qcom,pm8550ve-rpmh-regulators";
qcom,pmic-id = "j";
vdd-l1-supply = <&vreg_s1f_0p7>;
vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s5-supply = <&vreg_vph_pwr>;
vreg_s5j_1p2: smps5 {
regulator-name = "vreg_s5j_1p2";
regulator-min-microvolt = <1256000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1j_0p9: ldo1 {
regulator-name = "vreg_l1j_0p9";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2j_1p2: ldo2 {
regulator-name = "vreg_l2j_1p2";
regulator-min-microvolt = <1256000>;
regulator-max-microvolt = <1256000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3j_0p8: ldo3 {
regulator-name = "vreg_l3j_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&gpu {
status = "okay";
zap-shader {
firmware-name = "qcom/x1e80100/dell/xps13-9345/qcdxkmsuc8380.mbn";
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
keyboard@5 {
compatible = "hid-over-i2c";
reg = <0x5>;
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&kybd_default>;
pinctrl-names = "default";
wakeup-source;
};
};
&i2c3 {
clock-frequency = <400000>;
status = "disabled";
/* PS8830 Retimer @0x8 */
/* Unknown device @0x9 */
};
&i2c5 {
clock-frequency = <100000>;
status = "disabled";
/* EC @0x3b */
};
&i2c7 {
clock-frequency = <400000>;
status = "disabled";
/* PS8830 Retimer @0x8 */
/* Unknown device @0x9 */
};
&i2c8 {
clock-frequency = <400000>;
status = "okay";
touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&ts0_default>;
pinctrl-names = "default";
};
};
&i2c9 {
clock-frequency = <400000>;
status = "disabled";
/* USB3 retimer device @0x4f */
};
&i2c17 {
clock-frequency = <400000>;
status = "okay";
touchpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&tpad_default>;
pinctrl-names = "default";
wakeup-source;
};
};
&mdss {
status = "okay";
};
&mdss_dp3 {
/delete-property/ #sound-dai-cells;
status = "okay";
aux-bus {
panel {
compatible = "edp-panel";
enable-gpios = <&tlmm 74 GPIO_ACTIVE_HIGH>;
power-supply = <&vreg_edp_3p3>;
pinctrl-0 = <&edp_bl_en>;
pinctrl-names = "default";
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
};
};
};
};
ports {
port@1 {
reg = <1>;
mdss_dp3_out: endpoint {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&edp_panel_in>;
};
};
};
};
&mdss_dp3_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&qupv3_0 {
status = "okay";
};
&qupv3_1 {
status = "okay";
};
&qupv3_2 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/x1e80100/dell/xps13-9345/qcadsp8380.mbn",
"qcom/x1e80100/dell/xps13-9345/adsp_dtbs.elf";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/x1e80100/dell/xps13-9345/qccdsp8380.mbn",
"qcom/x1e80100/dell/xps13-9345/cdsp_dtbs.elf";
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l14b_3p0>;
};
&tlmm {
gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */
<76 4>, /* SPI19 (TZ Protected) */
<238 1>; /* UFS Reset */
cam_indicator_en: cam-indicator-en-state {
pins = "gpio110";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
edp_bl_en: edp-bl-en-state {
pins = "gpio74";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
edp_reg_en: edp-reg-en-state {
pins = "gpio70";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
hall_int_n_default: hall-int-n-state {
pins = "gpio92";
function = "gpio";
bias-disable;
};
kybd_default: kybd-default-state {
pins = "gpio67";
function = "gpio";
bias-pull-up;
};
nvme_reg_en: nvme-reg-en-state {
pins = "gpio18";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
function = "pcie4_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio146";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio148";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6a_default: pcie6a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio154";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
tpad_default: tpad-default-state {
disable-pins {
pins = "gpio38";
function = "gpio";
output-high;
};
int-n-pins {
pins = "gpio3";
function = "gpio";
bias-pull-up;
};
reset-n-pins {
pins = "gpio52";
function = "gpio";
bias-disable;
};
};
ts0_default: ts0-default-state {
disable-pins {
pins = "gpio75";
function = "gpio";
output-high;
};
int-n-pins {
pins = "gpio51";
function = "gpio";
bias-pull-up;
};
reset-n-pins {
/* Technically should be High-Z input */
pins = "gpio48";
function = "gpio";
output-low;
drive-strength = <2>;
};
};
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb_1_ss0_hsphy {
vdd-supply = <&vreg_l3j_0p8>;
vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_0_eusb2_repeater>;
status = "okay";
};
&usb_1_ss0_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l1j_0p9>;
status = "okay";
};
&usb_1_ss0 {
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "host";
};
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
&usb_1_ss0_qmpphy_out {
remote-endpoint = <&pmic_glink_ss0_ss_in>;
};
&usb_1_ss1_hsphy {
vdd-supply = <&vreg_l3j_0p8>;
vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_1_eusb2_repeater>;
status = "okay";
};
&usb_1_ss1_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
status = "okay";
};
&usb_1_ss1 {
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "host";
};
&usb_1_ss1_dwc3_hs {
remote-endpoint = <&pmic_glink_ss1_hs_in>;
};
&usb_1_ss1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss1_ss_in>;
};

39
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
View File

@ -15,6 +15,14 @@ / {
model = "Lenovo Yoga Slim 7x";
compatible = "lenovo,yoga-slim7x", "qcom,x1e80100";
aliases {
serial0 = &uart21;
};
chosen {
stdout-path = "serial0:115200n8";
};
pmic-glink {
compatible = "qcom,x1e80100-pmic-glink",
"qcom,sm8550-pmic-glink",
@ -166,17 +174,6 @@ platform {
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
@ -206,6 +203,17 @@ vreg_nvme: regulator-nvme {
pinctrl-0 = <&nvme_reg_en>;
pinctrl-names = "default";
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
@ -883,6 +891,11 @@ reset-n-pins {
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb_1_ss0_hsphy {
vdd-supply = <&vreg_l3j_0p8>;
vdda12-supply = <&vreg_l2j_1p2>;
@ -896,8 +909,6 @@ &usb_1_ss0_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l1j_0p8>;
orientation-switch;
status = "okay";
};
@ -930,8 +941,6 @@ &usb_1_ss1_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
orientation-switch;
status = "okay";
};

104
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
View File

@ -4,6 +4,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -30,6 +32,21 @@ backlight: backlight {
pinctrl-names = "default";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&hall_int_n_default>;
pinctrl-names = "default";
switch-lid {
gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
wakeup-event-action = <EV_ACT_DEASSERTED>;
};
};
leds {
compatible = "gpio-leds";
@ -125,17 +142,6 @@ linux,cma {
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
@ -165,6 +171,17 @@ vreg_nvme: regulator-nvme {
pinctrl-0 = <&nvme_reg_en>;
pinctrl-names = "default";
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
@ -555,7 +572,17 @@ &i2c5 {
status = "okay";
/* Something @4f */
ptn3222: redriver@4f {
compatible = "nxp,ptn3222";
reg = <0x4f>;
reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l13b>;
vdd1v8-supply = <&vreg_l4b>;
#phy-cells = <0>;
};
};
&i2c7 {
@ -566,7 +593,6 @@ &i2c7 {
/* PS8830 USB retimer @8 */
};
&mdss {
status = "okay";
};
@ -700,10 +726,25 @@ &smb2360_1_eusb2_repeater {
vdd3-supply = <&vreg_l14b>;
};
&smb2360_2 {
status = "okay";
};
&smb2360_2_eusb2_repeater {
vdd18-supply = <&vreg_l3d>;
vdd3-supply = <&vreg_l8b>;
};
&tlmm {
gpio-reserved-ranges = <44 4>, /* SPI (TPM) */
<238 1>; /* UFS Reset */
hall_int_n_default: hall-int-n-state {
pins = "gpio2";
function = "gpio";
bias-disable;
};
nvme_reg_en: nvme-reg-en-state {
pins = "gpio18";
function = "gpio";
@ -833,3 +874,40 @@ &usb_1_ss1_dwc3_hs {
&usb_1_ss1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss1_ss_in>;
};
/* MP0 goes to the Surface Connector, MP1 goes to the USB-A port */
&usb_mp {
status = "okay";
};
&usb_mp_hsphy0 {
vdd-supply = <&vreg_l2e>;
vdda12-supply = <&vreg_l2j>;
phys = <&smb2360_2_eusb2_repeater>;
status = "okay";
};
&usb_mp_hsphy1 {
vdd-supply = <&vreg_l2e>;
vdda12-supply = <&vreg_l2j>;
phys = <&ptn3222>;
status = "okay";
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l3e>;
vdda-pll-supply = <&vreg_l3c>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l3e>;
vdda-pll-supply = <&vreg_l3c>;
status = "okay";
};

229
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View File

@ -65,208 +65,208 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD1>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD2>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD3>;
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU4: cpu@10000 {
cpu4: cpu@10000 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10000>;
enable-method = "psci";
next-level-cache = <&L2_1>;
power-domains = <&CPU_PD4>;
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
L2_1: l2-cache {
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU5: cpu@10100 {
cpu5: cpu@10100 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10100>;
enable-method = "psci";
next-level-cache = <&L2_1>;
power-domains = <&CPU_PD5>;
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU6: cpu@10200 {
cpu6: cpu@10200 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10200>;
enable-method = "psci";
next-level-cache = <&L2_1>;
power-domains = <&CPU_PD6>;
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU7: cpu@10300 {
cpu7: cpu@10300 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10300>;
enable-method = "psci";
next-level-cache = <&L2_1>;
power-domains = <&CPU_PD7>;
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU8: cpu@20000 {
cpu8: cpu@20000 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x20000>;
enable-method = "psci";
next-level-cache = <&L2_2>;
power-domains = <&CPU_PD8>;
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd8>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
L2_2: l2-cache {
l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
CPU9: cpu@20100 {
cpu9: cpu@20100 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x20100>;
enable-method = "psci";
next-level-cache = <&L2_2>;
power-domains = <&CPU_PD9>;
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd9>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU10: cpu@20200 {
cpu10: cpu@20200 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x20200>;
enable-method = "psci";
next-level-cache = <&L2_2>;
power-domains = <&CPU_PD10>;
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd10>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
CPU11: cpu@20300 {
cpu11: cpu@20300 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x20300>;
enable-method = "psci";
next-level-cache = <&L2_2>;
power-domains = <&CPU_PD11>;
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd11>;
power-domain-names = "psci";
cpu-idle-states = <&CLUSTER_C4>;
cpu-idle-states = <&cluster_c4>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core1 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core2 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core3 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
cluster2 {
core0 {
cpu = <&CPU8>;
cpu = <&cpu8>;
};
core1 {
cpu = <&CPU9>;
cpu = <&cpu9>;
};
core2 {
cpu = <&CPU10>;
cpu = <&cpu10>;
};
core3 {
cpu = <&CPU11>;
cpu = <&cpu11>;
};
};
};
@ -274,32 +274,30 @@ core3 {
idle-states {
entry-method = "psci";
CLUSTER_C4: cpu-sleep-0 {
cluster_c4: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <180>;
exit-latency-us = <320>;
min-residency-us = <1000>;
exit-latency-us = <500>;
min-residency-us = <600>;
};
};
domain-idle-states {
CLUSTER_CL4: cluster-sleep-0 {
cluster_cl4: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "l2-ret";
arm,psci-suspend-param = <0x01000044>;
entry-latency-us = <350>;
exit-latency-us = <500>;
min-residency-us = <2500>;
};
CLUSTER_CL5: cluster-sleep-1 {
cluster_cl5: cluster-sleep-1 {
compatible = "domain-idle-state";
idle-state-name = "ret-pll-off";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2200>;
exit-latency-us = <2500>;
exit-latency-us = <4000>;
min-residency-us = <7000>;
};
};
@ -310,6 +308,7 @@ scm: scm {
compatible = "qcom,scm-x1e80100", "qcom,scm";
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
qcom,dload-mode = <&tcsr 0x19000>;
};
};
@ -340,85 +339,85 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD0>;
power-domains = <&cluster_pd0>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD0>;
power-domains = <&cluster_pd0>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD0>;
power-domains = <&cluster_pd0>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD0>;
power-domains = <&cluster_pd0>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD1>;
power-domains = <&cluster_pd1>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD1>;
power-domains = <&cluster_pd1>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD1>;
power-domains = <&cluster_pd1>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD1>;
power-domains = <&cluster_pd1>;
};
CPU_PD8: power-domain-cpu8 {
cpu_pd8: power-domain-cpu8 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD2>;
power-domains = <&cluster_pd2>;
};
CPU_PD9: power-domain-cpu9 {
cpu_pd9: power-domain-cpu9 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD2>;
power-domains = <&cluster_pd2>;
};
CPU_PD10: power-domain-cpu10 {
cpu_pd10: power-domain-cpu10 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD2>;
power-domains = <&cluster_pd2>;
};
CPU_PD11: power-domain-cpu11 {
cpu_pd11: power-domain-cpu11 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD2>;
power-domains = <&cluster_pd2>;
};
CLUSTER_PD0: power-domain-cpu-cluster0 {
cluster_pd0: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
power-domains = <&SYSTEM_PD>;
domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
power-domains = <&system_pd>;
};
CLUSTER_PD1: power-domain-cpu-cluster1 {
cluster_pd1: power-domain-cpu-cluster1 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
power-domains = <&SYSTEM_PD>;
domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
power-domains = <&system_pd>;
};
CLUSTER_PD2: power-domain-cpu-cluster2 {
cluster_pd2: power-domain-cpu-cluster2 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
power-domains = <&SYSTEM_PD>;
domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
power-domains = <&system_pd>;
};
SYSTEM_PD: power-domain-system {
system_pd: power-domain-system {
#power-domain-cells = <0>;
/* TODO: system-wide idle states */
};
@ -2933,6 +2932,8 @@ pcie6a: pci@1bf8000 {
linux,pci-domain = <6>;
num-lanes = <2>;
msi-map = <0x0 &gic_its 0xe0000 0x10000>;
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
@ -3175,6 +3176,8 @@ pcie4: pci@1c08000 {
linux,pci-domain = <4>;
num-lanes = <2>;
msi-map = <0x0 &gic_its 0xc0000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
@ -3386,7 +3389,7 @@ gmu: gmu@3d6a000 {
reg = <0x0 0x03d6a000 0x0 0x35000>,
<0x0 0x03d50000 0x0 0x10000>,
<0x0 0x0b280000 0x0 0x10000>;
reg-names = "gmu", "rscc", "gmu_pdc";
reg-names = "gmu", "rscc", "gmu_pdc";
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
@ -4054,6 +4057,8 @@ usb_1_ss2_dwc3: usb@a000000 {
dma-coherent;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -4307,6 +4312,8 @@ usb_1_ss0_dwc3: usb@a600000 {
dma-coherent;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -4405,6 +4412,8 @@ usb_1_ss1_dwc3: usb@a800000 {
dma-coherent;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -5738,12 +5747,14 @@ apps_smmu: iommu@15000000 {
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
};
intc: interrupt-controller@17000000 {
compatible = "arm,gic-v3";
reg = <0 0x17000000 0 0x10000>, /* GICD */
<0 0x17080000 0 0x480000>; /* GICR * 12 */
<0 0x17080000 0 0x300000>; /* GICR * 12 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
@ -5763,8 +5774,6 @@ gic_its: msi-controller@17040000 {
msi-controller;
#msi-cells = <1>;
status = "disabled";
};
};
@ -5784,7 +5793,7 @@ apps_rsc: rsc@17500000 {
<WAKE_TCS 2>, <CONTROL_TCS 0>;
label = "apps_rsc";
power-domains = <&SYSTEM_PD>;
power-domains = <&system_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";

108
include/dt-bindings/clock/qcom,sa8775p-camcc.h Normal file
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@ -0,0 +1,108 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
#define _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
/* CAM_CC clocks */
#define CAM_CC_CAMNOC_AXI_CLK 0
#define CAM_CC_CAMNOC_AXI_CLK_SRC 1
#define CAM_CC_CAMNOC_DCD_XO_CLK 2
#define CAM_CC_CAMNOC_XO_CLK 3
#define CAM_CC_CCI_0_CLK 4
#define CAM_CC_CCI_0_CLK_SRC 5
#define CAM_CC_CCI_1_CLK 6
#define CAM_CC_CCI_1_CLK_SRC 7
#define CAM_CC_CCI_2_CLK 8
#define CAM_CC_CCI_2_CLK_SRC 9
#define CAM_CC_CCI_3_CLK 10
#define CAM_CC_CCI_3_CLK_SRC 11
#define CAM_CC_CORE_AHB_CLK 12
#define CAM_CC_CPAS_AHB_CLK 13
#define CAM_CC_CPAS_FAST_AHB_CLK 14
#define CAM_CC_CPAS_IFE_0_CLK 15
#define CAM_CC_CPAS_IFE_1_CLK 16
#define CAM_CC_CPAS_IFE_LITE_CLK 17
#define CAM_CC_CPAS_IPE_CLK 18
#define CAM_CC_CPAS_SFE_LITE_0_CLK 19
#define CAM_CC_CPAS_SFE_LITE_1_CLK 20
#define CAM_CC_CPHY_RX_CLK_SRC 21
#define CAM_CC_CSI0PHYTIMER_CLK 22
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 23
#define CAM_CC_CSI1PHYTIMER_CLK 24
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 25
#define CAM_CC_CSI2PHYTIMER_CLK 26
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 27
#define CAM_CC_CSI3PHYTIMER_CLK 28
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 29
#define CAM_CC_CSID_CLK 30
#define CAM_CC_CSID_CLK_SRC 31
#define CAM_CC_CSID_CSIPHY_RX_CLK 32
#define CAM_CC_CSIPHY0_CLK 33
#define CAM_CC_CSIPHY1_CLK 34
#define CAM_CC_CSIPHY2_CLK 35
#define CAM_CC_CSIPHY3_CLK 36
#define CAM_CC_FAST_AHB_CLK_SRC 37
#define CAM_CC_GDSC_CLK 38
#define CAM_CC_ICP_AHB_CLK 39
#define CAM_CC_ICP_CLK 40
#define CAM_CC_ICP_CLK_SRC 41
#define CAM_CC_IFE_0_CLK 42
#define CAM_CC_IFE_0_CLK_SRC 43
#define CAM_CC_IFE_0_FAST_AHB_CLK 44
#define CAM_CC_IFE_1_CLK 45
#define CAM_CC_IFE_1_CLK_SRC 46
#define CAM_CC_IFE_1_FAST_AHB_CLK 47
#define CAM_CC_IFE_LITE_AHB_CLK 48
#define CAM_CC_IFE_LITE_CLK 49
#define CAM_CC_IFE_LITE_CLK_SRC 50
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 51
#define CAM_CC_IFE_LITE_CSID_CLK 52
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 53
#define CAM_CC_IPE_AHB_CLK 54
#define CAM_CC_IPE_CLK 55
#define CAM_CC_IPE_CLK_SRC 56
#define CAM_CC_IPE_FAST_AHB_CLK 57
#define CAM_CC_MCLK0_CLK 58
#define CAM_CC_MCLK0_CLK_SRC 59
#define CAM_CC_MCLK1_CLK 60
#define CAM_CC_MCLK1_CLK_SRC 61
#define CAM_CC_MCLK2_CLK 62
#define CAM_CC_MCLK2_CLK_SRC 63
#define CAM_CC_MCLK3_CLK 64
#define CAM_CC_MCLK3_CLK_SRC 65
#define CAM_CC_PLL0 66
#define CAM_CC_PLL0_OUT_EVEN 67
#define CAM_CC_PLL0_OUT_ODD 68
#define CAM_CC_PLL2 69
#define CAM_CC_PLL3 70
#define CAM_CC_PLL3_OUT_EVEN 71
#define CAM_CC_PLL4 72
#define CAM_CC_PLL4_OUT_EVEN 73
#define CAM_CC_PLL5 74
#define CAM_CC_PLL5_OUT_EVEN 75
#define CAM_CC_SFE_LITE_0_CLK 76
#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 77
#define CAM_CC_SFE_LITE_1_CLK 78
#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 79
#define CAM_CC_SLEEP_CLK 80
#define CAM_CC_SLEEP_CLK_SRC 81
#define CAM_CC_SLOW_AHB_CLK_SRC 82
#define CAM_CC_SM_OBS_CLK 83
#define CAM_CC_XO_CLK_SRC 84
#define CAM_CC_QDSS_DEBUG_XO_CLK 85
/* CAM_CC power domains */
#define CAM_CC_TITAN_TOP_GDSC 0
/* CAM_CC resets */
#define CAM_CC_ICP_BCR 0
#define CAM_CC_IFE_0_BCR 1
#define CAM_CC_IFE_1_BCR 2
#define CAM_CC_IPE_0_BCR 3
#define CAM_CC_SFE_LITE_0_BCR 4
#define CAM_CC_SFE_LITE_1_BCR 5
#endif

87
include/dt-bindings/clock/qcom,sa8775p-dispcc.h Normal file
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@ -0,0 +1,87 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
/* DISP_CC_0/1 clocks */
#define MDSS_DISP_CC_MDSS_AHB1_CLK 0
#define MDSS_DISP_CC_MDSS_AHB_CLK 1
#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 2
#define MDSS_DISP_CC_MDSS_BYTE0_CLK 3
#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 6
#define MDSS_DISP_CC_MDSS_BYTE1_CLK 7
#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 8
#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9
#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 10
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 11
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC 14
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 15
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 23
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 24
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 25
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 26
#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 28
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC 31
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39
#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 40
#define MDSS_DISP_CC_MDSS_ESC0_CLK 41
#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 42
#define MDSS_DISP_CC_MDSS_ESC1_CLK 43
#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 44
#define MDSS_DISP_CC_MDSS_MDP1_CLK 45
#define MDSS_DISP_CC_MDSS_MDP_CLK 46
#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 47
#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 48
#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 49
#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 50
#define MDSS_DISP_CC_MDSS_PCLK0_CLK 51
#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 52
#define MDSS_DISP_CC_MDSS_PCLK1_CLK 53
#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 54
#define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK 55
#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 56
#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 57
#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 58
#define MDSS_DISP_CC_MDSS_VSYNC_CLK 59
#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 60
#define MDSS_DISP_CC_PLL0 61
#define MDSS_DISP_CC_PLL1 62
#define MDSS_DISP_CC_SLEEP_CLK 63
#define MDSS_DISP_CC_SLEEP_CLK_SRC 64
#define MDSS_DISP_CC_SM_OBS_CLK 65
#define MDSS_DISP_CC_XO_CLK 66
#define MDSS_DISP_CC_XO_CLK_SRC 67
/* DISP_CC_0/1 power domains */
#define MDSS_DISP_CC_MDSS_CORE_GDSC 0
#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC_0/1 resets */
#define MDSS_DISP_CC_MDSS_CORE_BCR 0
#define MDSS_DISP_CC_MDSS_RSCC_BCR 1
#endif

47
include/dt-bindings/clock/qcom,sa8775p-videocc.h Normal file
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@ -0,0 +1,47 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
#define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
/* VIDEO_CC clocks */
#define VIDEO_CC_AHB_CLK 0
#define VIDEO_CC_AHB_CLK_SRC 1
#define VIDEO_CC_MVS0_CLK 2
#define VIDEO_CC_MVS0_CLK_SRC 3
#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
#define VIDEO_CC_MVS0C_CLK 5
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6
#define VIDEO_CC_MVS1_CLK 7
#define VIDEO_CC_MVS1_CLK_SRC 8
#define VIDEO_CC_MVS1_DIV_CLK_SRC 9
#define VIDEO_CC_MVS1C_CLK 10
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11
#define VIDEO_CC_PLL_LOCK_MONITOR_CLK 12
#define VIDEO_CC_SLEEP_CLK 13
#define VIDEO_CC_SLEEP_CLK_SRC 14
#define VIDEO_CC_SM_DIV_CLK_SRC 15
#define VIDEO_CC_SM_OBS_CLK 16
#define VIDEO_CC_XO_CLK 17
#define VIDEO_CC_XO_CLK_SRC 18
#define VIDEO_PLL0 19
#define VIDEO_PLL1 20
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0C_GDSC 0
#define VIDEO_CC_MVS0_GDSC 1
#define VIDEO_CC_MVS1C_GDSC 2
#define VIDEO_CC_MVS1_GDSC 3
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0C_CLK_ARES 2
#define VIDEO_CC_MVS0C_BCR 3
#define VIDEO_CC_MVS1_BCR 4
#define VIDEO_CC_MVS1C_CLK_ARES 5
#define VIDEO_CC_MVS1C_BCR 6
#endif