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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge branch 'pci/controller/qcom'
- Enable MSI interrupts if 'global' IRQ is supported, since a previous commit unintentionally masked them (Manivannan Sadhasivam) - Move endpoint controller cleanups that depend on refclk from the host to the notifier that tells us the host has deasserted PERST# (Manivannan Sadhasivam) - Add DT binding and driver support for IPQ9574, with Synopsys IP v5.80a and Qcom IP 1.27.0 (devi priya) - Move the OPP "operating-points-v2" table from the qcom,pcie-sm8450.yaml DT binding to qcom,pcie-common.yaml, where it can be used by other Qcom platforms (Qiang Yu) - Add 'global' SPI interrupt for events like link-up, link-down to qcom,pcie-x1e80100 DT binding so we can start enumeration when the link comes up (Qiang Yu) - Disable ASPM L0s for qcom,pcie-x1e80100 since the PHY is not tuned to support this (Qiang Yu) - Add ops_1_21_0 for SC8280X family SoC, which doesn't use the 'iommu-map' DT property and doesn't need BDF-to-SID translation (Qiang Yu) * pci/controller/qcom: PCI: qcom: Disable ASPM L0s for X1E80100 PCI: qcom: Remove BDF2SID mapping config for SC8280X family SoC dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml PCI: qcom: Add support for IPQ9574 dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller PCI: qcom-ep: Move controller cleanups to qcom_pcie_perst_deassert() PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported
This commit is contained in:
Bjorn Helgaas
commit
f54ff407e6
@ -81,6 +81,10 @@ properties:
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vddpe-3v3-supply:
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description: PCIe endpoint power supply
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- reg
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- reg-names
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@ -70,10 +70,6 @@ properties:
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- const: msi7
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- const: global
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operating-points-v2: true
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opp-table:
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type: object
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resets:
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maxItems: 1
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@ -47,9 +47,10 @@ properties:
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interrupts:
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minItems: 8
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maxItems: 8
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maxItems: 9
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interrupt-names:
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minItems: 8
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items:
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- const: msi0
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- const: msi1
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@ -59,6 +60,7 @@ properties:
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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resets:
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minItems: 1
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@ -130,9 +132,10 @@ examples:
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7";
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"msi4", "msi5", "msi6", "msi7", "global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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@ -26,6 +26,7 @@ properties:
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- qcom,pcie-ipq8064-v2
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- qcom,pcie-ipq8074
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-ipq9574
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- qcom,pcie-msm8996
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- qcom,pcie-qcs404
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- qcom,pcie-sdm845
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@ -164,6 +165,7 @@ allOf:
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enum:
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-ipq9574
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then:
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properties:
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reg:
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@ -400,6 +402,53 @@ allOf:
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- const: axi_m_sticky # AXI Master Sticky reset
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- const: axi_s_sticky # AXI Slave Sticky reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq9574
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then:
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properties:
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: axi_bridge
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- const: rchng
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- const: ahb
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- const: aux
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resets:
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minItems: 8
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maxItems: 8
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reset-names:
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items:
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- const: pipe # PIPE reset
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- const: sticky # Core Sticky reset
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- const: axi_s_sticky # AXI Slave Sticky reset
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- const: axi_s # AXI Slave reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- const: axi_m # AXI Master reset
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- const: aux # AUX Reset
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- const: ahb # AHB Reset
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interrupts:
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minItems: 8
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- if:
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properties:
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compatible:
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@ -510,6 +559,7 @@ allOf:
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- qcom,pcie-ipq8064v2
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- qcom,pcie-ipq8074
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-ipq9574
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- qcom,pcie-qcs404
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then:
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required:
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@ -396,6 +396,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
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return ret;
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}
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/* Perform cleanup that requires refclk */
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pci_epc_deinit_notify(pci->ep.epc);
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dw_pcie_ep_cleanup(&pci->ep);
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/* Assert WAKE# to RC to indicate device is ready */
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gpiod_set_value_cansleep(pcie_ep->wake, 1);
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usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
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@ -540,8 +544,6 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci)
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{
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struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
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pci_epc_deinit_notify(pci->ep.epc);
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dw_pcie_ep_cleanup(&pci->ep);
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qcom_pcie_disable_resources(pcie_ep);
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pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
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}
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@ -133,6 +133,7 @@
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/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
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#define PARF_INT_ALL_LINK_UP BIT(13)
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#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
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/* PARF_NO_SNOOP_OVERIDE register fields */
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#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
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@ -1364,6 +1365,16 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
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.config_sid = qcom_pcie_config_sid_1_9_0,
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};
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/* Qcom IP rev.: 1.21.0 Synopsys IP rev.: 5.60a */
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static const struct qcom_pcie_ops ops_1_21_0 = {
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.get_resources = qcom_pcie_get_resources_2_7_0,
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.init = qcom_pcie_init_2_7_0,
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.post_init = qcom_pcie_post_init_2_7_0,
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.host_post_init = qcom_pcie_host_post_init_2_7_0,
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.deinit = qcom_pcie_deinit_2_7_0,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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};
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/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
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static const struct qcom_pcie_ops ops_2_9_0 = {
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.get_resources = qcom_pcie_get_resources_2_9_0,
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@ -1411,7 +1422,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
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};
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static const struct qcom_pcie_cfg cfg_sc8280xp = {
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.ops = &ops_1_9_0,
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.ops = &ops_1_21_0,
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.no_l0s = true,
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};
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@ -1716,7 +1727,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
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goto err_host_deinit;
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}
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writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK);
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writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7,
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pcie->parf + PARF_INT_ALL_MASK);
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}
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qcom_pcie_icc_opp_update(pcie);
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@ -1828,6 +1840,7 @@ static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
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{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
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{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
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{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
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{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
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{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
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{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
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@ -1843,7 +1856,7 @@ static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
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{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
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{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
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{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
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{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
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{ }
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};
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