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clk: Add Ingenic JZ4755 CGU driver
Add support for the clocks provided by the CGU in the Ingenic JZ4755 SoC. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Link: https://lore.kernel.org/r/20221031183930.1338009-2-lis8215@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Siarhei Volkau
Stephen Boyd
parent
4cb21b9ede
commit
ff0d3ae04f
@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740
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If building for a JZ4740 SoC, you want to say Y here.
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config INGENIC_CGU_JZ4755
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bool "Ingenic JZ4755 CGU driver"
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default MACH_JZ4755
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select INGENIC_CGU_COMMON
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help
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Support the clocks provided by the CGU hardware on Ingenic JZ4755
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and compatible SoCs.
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If building for a JZ4755 SoC, you want to say Y here.
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config INGENIC_CGU_JZ4725B
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bool "Ingenic JZ4725B CGU driver"
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default MACH_JZ4725B
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
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obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
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obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o
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obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
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obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
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obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
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346
drivers/clk/ingenic/jz4755-cgu.c
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346
drivers/clk/ingenic/jz4755-cgu.c
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@ -0,0 +1,346 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Ingenic JZ4755 SoC CGU driver
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* Heavily based on JZ4725b CGU driver
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*
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* Copyright (C) 2022 Siarhei Volkau
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* Author: Siarhei Volkau <lis8215@gmail.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/ingenic,jz4755-cgu.h>
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#include "cgu.h"
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#include "pm.h"
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/* CGU register offsets */
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#define CGU_REG_CPCCR 0x00
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#define CGU_REG_CPPCR 0x10
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#define CGU_REG_CLKGR 0x20
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#define CGU_REG_OPCR 0x24
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#define CGU_REG_I2SCDR 0x60
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#define CGU_REG_LPCDR 0x64
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#define CGU_REG_MSCCDR 0x68
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#define CGU_REG_SSICDR 0x74
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#define CGU_REG_CIMCDR 0x7C
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static struct ingenic_cgu *cgu;
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static const s8 pll_od_encoding[4] = {
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0x0, 0x1, -1, 0x3,
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};
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static const u8 jz4755_cgu_cpccr_div_table[] = {
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1, 2, 3, 4, 6, 8,
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};
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static const u8 jz4755_cgu_pll_half_div_table[] = {
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2, 1,
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};
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static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = {
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/* External clocks */
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[JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT },
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[JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
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[JZ4755_CLK_PLL] = {
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"pll", CGU_CLK_PLL,
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.parents = { JZ4755_CLK_EXT, },
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.pll = {
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.reg = CGU_REG_CPPCR,
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.rate_multiplier = 1,
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.m_shift = 23,
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.m_bits = 9,
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.m_offset = 2,
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.n_shift = 18,
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.n_bits = 5,
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.n_offset = 2,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 4,
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.od_encoding = pll_od_encoding,
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.stable_bit = 10,
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.bypass_reg = CGU_REG_CPPCR,
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.bypass_bit = 9,
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.enable_bit = 8,
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},
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},
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/* Muxes & dividers */
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[JZ4755_CLK_PLL_HALF] = {
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"pll half", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_PLL, },
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.div = {
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CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
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jz4755_cgu_pll_half_div_table,
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},
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},
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[JZ4755_CLK_EXT_HALF] = {
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"ext half", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_EXT, },
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.div = {
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CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0,
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NULL,
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},
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},
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[JZ4755_CLK_CCLK] = {
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"cclk", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_PLL, },
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.div = {
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
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jz4755_cgu_cpccr_div_table,
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},
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},
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[JZ4755_CLK_H0CLK] = {
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"hclk", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_PLL, },
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.div = {
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CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
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jz4755_cgu_cpccr_div_table,
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},
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},
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[JZ4755_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_PLL, },
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.div = {
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CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
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jz4755_cgu_cpccr_div_table,
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},
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},
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[JZ4755_CLK_MCLK] = {
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"mclk", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_PLL, },
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.div = {
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CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
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jz4755_cgu_cpccr_div_table,
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},
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},
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[JZ4755_CLK_H1CLK] = {
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"h1clk", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_PLL, },
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.div = {
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CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
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jz4755_cgu_cpccr_div_table,
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},
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},
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[JZ4755_CLK_UDC] = {
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"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, },
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.mux = { CGU_REG_CPCCR, 29, 1 },
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.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 10 },
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},
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[JZ4755_CLK_LCD] = {
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"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4755_CLK_PLL_HALF, },
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.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 9 },
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},
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[JZ4755_CLK_MMC] = {
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"mmc", CGU_CLK_DIV,
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.parents = { JZ4755_CLK_PLL_HALF, },
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.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
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},
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[JZ4755_CLK_I2S] = {
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"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, },
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.mux = { CGU_REG_CPCCR, 31, 1 },
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.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
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},
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[JZ4755_CLK_SPI] = {
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"spi", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4755_CLK_PLL_HALF, },
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.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 4 },
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},
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[JZ4755_CLK_TVE] = {
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"tve", CGU_CLK_MUX | CGU_CLK_GATE,
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.parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, },
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.mux = { CGU_REG_LPCDR, 31, 1 },
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.gate = { CGU_REG_CLKGR, 18 },
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},
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[JZ4755_CLK_RTC] = {
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"rtc", CGU_CLK_MUX | CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, },
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.mux = { CGU_REG_OPCR, 2, 1},
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.gate = { CGU_REG_CLKGR, 2 },
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},
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[JZ4755_CLK_CIM] = {
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"cim", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4755_CLK_PLL_HALF, },
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.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 8 },
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},
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/* Gate-only clocks */
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[JZ4755_CLK_UART0] = {
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"uart0", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, },
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.gate = { CGU_REG_CLKGR, 0 },
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},
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[JZ4755_CLK_UART1] = {
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"uart1", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, },
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.gate = { CGU_REG_CLKGR, 14 },
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},
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[JZ4755_CLK_UART2] = {
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"uart2", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, },
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.gate = { CGU_REG_CLKGR, 15 },
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},
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[JZ4755_CLK_ADC] = {
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"adc", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, },
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.gate = { CGU_REG_CLKGR, 7 },
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},
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[JZ4755_CLK_AIC] = {
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"aic", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, },
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.gate = { CGU_REG_CLKGR, 5 },
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},
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[JZ4755_CLK_I2C] = {
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"i2c", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, },
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.gate = { CGU_REG_CLKGR, 3 },
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},
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[JZ4755_CLK_BCH] = {
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"bch", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_H1CLK, },
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.gate = { CGU_REG_CLKGR, 11 },
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},
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[JZ4755_CLK_TCU] = {
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"tcu", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT, },
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.gate = { CGU_REG_CLKGR, 1 },
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},
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[JZ4755_CLK_DMA] = {
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"dma", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_PCLK, },
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.gate = { CGU_REG_CLKGR, 12 },
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},
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[JZ4755_CLK_MMC0] = {
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"mmc0", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_MMC, },
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.gate = { CGU_REG_CLKGR, 6 },
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},
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[JZ4755_CLK_MMC1] = {
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"mmc1", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_MMC, },
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.gate = { CGU_REG_CLKGR, 16 },
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},
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[JZ4755_CLK_AUX_CPU] = {
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"aux_cpu", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_H1CLK, },
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.gate = { CGU_REG_CLKGR, 24 },
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},
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[JZ4755_CLK_AHB1] = {
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"ahb1", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_H1CLK, },
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.gate = { CGU_REG_CLKGR, 23 },
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},
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[JZ4755_CLK_IDCT] = {
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"idct", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_H1CLK, },
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.gate = { CGU_REG_CLKGR, 22 },
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},
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[JZ4755_CLK_DB] = {
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"db", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_H1CLK, },
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.gate = { CGU_REG_CLKGR, 21 },
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},
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[JZ4755_CLK_ME] = {
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"me", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_H1CLK, },
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.gate = { CGU_REG_CLKGR, 20 },
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},
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[JZ4755_CLK_MC] = {
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"mc", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_H1CLK, },
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.gate = { CGU_REG_CLKGR, 19 },
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},
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[JZ4755_CLK_TSSI] = {
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"tssi", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF/* not sure */, },
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.gate = { CGU_REG_CLKGR, 17 },
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},
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[JZ4755_CLK_IPU] = {
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"ipu", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_PLL_HALF/* not sure */, },
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.gate = { CGU_REG_CLKGR, 13 },
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},
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[JZ4755_CLK_EXT512] = {
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"ext/512", CGU_CLK_FIXDIV,
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.parents = { JZ4755_CLK_EXT, },
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.fixdiv = { 512 },
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},
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[JZ4755_CLK_UDC_PHY] = {
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"udc_phy", CGU_CLK_GATE,
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.parents = { JZ4755_CLK_EXT_HALF, },
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.gate = { CGU_REG_OPCR, 6, true },
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},
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};
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static void __init jz4755_cgu_init(struct device_node *np)
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{
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int retval;
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cgu = ingenic_cgu_new(jz4755_cgu_clocks,
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ARRAY_SIZE(jz4755_cgu_clocks), np);
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if (!cgu) {
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pr_err("%s: failed to initialise CGU\n", __func__);
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return;
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}
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retval = ingenic_cgu_register_clocks(cgu);
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if (retval)
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pr_err("%s: failed to register CGU Clocks\n", __func__);
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ingenic_cgu_register_syscore_ops(cgu);
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}
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/*
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* CGU has some children devices, this is useful for probing children devices
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* in the case where the device node is compatible with "simple-mfd".
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*/
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CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);
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